EMU Bit FieldsDevices > EMU

Macros

#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN   0x00000002UL
 
#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_BUACTPWRCON_MAINBU   0x00000001UL
 
#define _EMU_BUCTRL_BUACTPWRCON_MASK   0x30000UL
 
#define _EMU_BUCTRL_BUACTPWRCON_NODIODE   0x00000003UL
 
#define _EMU_BUCTRL_BUACTPWRCON_NONE   0x00000000UL
 
#define _EMU_BUCTRL_BUACTPWRCON_SHIFT   16
 
#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN   0x00000002UL
 
#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU   0x00000001UL
 
#define _EMU_BUCTRL_BUINACTPWRCON_MASK   0x300000UL
 
#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE   0x00000003UL
 
#define _EMU_BUCTRL_BUINACTPWRCON_NONE   0x00000000UL
 
#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT   20
 
#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_BUVINPROBEEN_MASK   0x4UL
 
#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT   2
 
#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_DISMAXCOMP_MASK   0x80000000UL
 
#define _EMU_BUCTRL_DISMAXCOMP_SHIFT   31
 
#define _EMU_BUCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_EN_MASK   0x1UL
 
#define _EMU_BUCTRL_EN_SHIFT   0
 
#define _EMU_BUCTRL_MASK   0x80333307UL
 
#define _EMU_BUCTRL_PWRRES_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_PWRRES_MASK   0x3000UL
 
#define _EMU_BUCTRL_PWRRES_RES0   0x00000000UL
 
#define _EMU_BUCTRL_PWRRES_RES1   0x00000001UL
 
#define _EMU_BUCTRL_PWRRES_RES2   0x00000002UL
 
#define _EMU_BUCTRL_PWRRES_RES3   0x00000003UL
 
#define _EMU_BUCTRL_PWRRES_SHIFT   12
 
#define _EMU_BUCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_BUCTRL_STATEN_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_STATEN_MASK   0x2UL
 
#define _EMU_BUCTRL_STATEN_SHIFT   1
 
#define _EMU_BUCTRL_VOUTRES_DEFAULT   0x00000000UL
 
#define _EMU_BUCTRL_VOUTRES_DIS   0x00000000UL
 
#define _EMU_BUCTRL_VOUTRES_MASK   0x300UL
 
#define _EMU_BUCTRL_VOUTRES_MED   0x00000002UL
 
#define _EMU_BUCTRL_VOUTRES_SHIFT   8
 
#define _EMU_BUCTRL_VOUTRES_STRONG   0x00000003UL
 
#define _EMU_BUCTRL_VOUTRES_WEAK   0x00000001UL
 
#define _EMU_CMD_EM01VSCALE0_DEFAULT   0x00000000UL
 
#define _EMU_CMD_EM01VSCALE0_MASK   0x10UL
 
#define _EMU_CMD_EM01VSCALE0_SHIFT   4
 
#define _EMU_CMD_EM01VSCALE2_DEFAULT   0x00000000UL
 
#define _EMU_CMD_EM01VSCALE2_MASK   0x40UL
 
#define _EMU_CMD_EM01VSCALE2_SHIFT   6
 
#define _EMU_CMD_EM4UNLATCH_DEFAULT   0x00000000UL
 
#define _EMU_CMD_EM4UNLATCH_MASK   0x1UL
 
#define _EMU_CMD_EM4UNLATCH_SHIFT   0
 
#define _EMU_CMD_MASK   0x00000051UL
 
#define _EMU_CMD_RESETVALUE   0x00000000UL
 
#define _EMU_CTRL_EM01LD_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM01LD_MASK   0x8UL
 
#define _EMU_CTRL_EM01LD_SHIFT   3
 
#define _EMU_CTRL_EM23VSCALE_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM23VSCALE_MASK   0x300UL
 
#define _EMU_CTRL_EM23VSCALE_RESV   0x00000003UL
 
#define _EMU_CTRL_EM23VSCALE_SHIFT   8
 
#define _EMU_CTRL_EM23VSCALE_VSCALE0   0x00000002UL
 
#define _EMU_CTRL_EM23VSCALE_VSCALE2   0x00000000UL
 
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK   0x10UL
 
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT   4
 
#define _EMU_CTRL_EM2BLOCK_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM2BLOCK_MASK   0x2UL
 
#define _EMU_CTRL_EM2BLOCK_SHIFT   1
 
#define _EMU_CTRL_EM2BODDIS_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM2BODDIS_MASK   0x4UL
 
#define _EMU_CTRL_EM2BODDIS_SHIFT   2
 
#define _EMU_CTRL_EM4HVSCALE_DEFAULT   0x00000000UL
 
#define _EMU_CTRL_EM4HVSCALE_MASK   0x30000UL
 
#define _EMU_CTRL_EM4HVSCALE_RESV   0x00000003UL
 
#define _EMU_CTRL_EM4HVSCALE_SHIFT   16
 
#define _EMU_CTRL_EM4HVSCALE_VSCALE0   0x00000002UL
 
#define _EMU_CTRL_EM4HVSCALE_VSCALE2   0x00000000UL
 
#define _EMU_CTRL_MASK   0x0003031EUL
 
#define _EMU_CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT   0x00000000UL
 
#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK   0x2000UL
 
#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT   13
 
#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT   0x00000001UL
 
#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK   0x300UL
 
#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT   8
 
#define _EMU_DCDCCLIMCTRL_MASK   0x00002300UL
 
#define _EMU_DCDCCLIMCTRL_RESETVALUE   0x00000100UL
 
#define _EMU_DCDCCTRL_DCDCMODE_BYPASS   0x00000000UL
 
#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT   0x00000003UL
 
#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER   0x00000002UL
 
#define _EMU_DCDCCTRL_DCDCMODE_MASK   0x3UL
 
#define _EMU_DCDCCTRL_DCDCMODE_OFF   0x00000003UL
 
#define _EMU_DCDCCTRL_DCDCMODE_SHIFT   0
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW   0x00000000UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK   0x10UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT   4
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER   0x00000001UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW   0x00000000UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK   0x20UL
 
#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT   5
 
#define _EMU_DCDCCTRL_MASK   0x00000033UL
 
#define _EMU_DCDCCTRL_RESETVALUE   0x00000033UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT   0x00000002UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK   0x300000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT   20
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT   0x00000007UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK   0x7000000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT   24
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT   0x00000005UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK   0xF0000000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT   28
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT   0x00000007UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK   0x7UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT   0
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT   0x00000007UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK   0x1F0UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT   4
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT   0x00000004UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK   0xF000UL
 
#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT   12
 
#define _EMU_DCDCLNCOMPCTRL_MASK   0xF730F1F7UL
 
#define _EMU_DCDCLNCOMPCTRL_RESETVALUE   0x57204077UL
 
#define _EMU_DCDCLNFREQCTRL_MASK   0x1F000007UL
 
#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK   0x7UL
 
#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT   0
 
#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT   0x00000010UL
 
#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK   0x1F000000UL
 
#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT   24
 
#define _EMU_DCDCLNFREQCTRL_RESETVALUE   0x10000000UL
 
#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLNVCTRL_LNATT_DIV3   0x00000000UL
 
#define _EMU_DCDCLNVCTRL_LNATT_DIV6   0x00000001UL
 
#define _EMU_DCDCLNVCTRL_LNATT_MASK   0x2UL
 
#define _EMU_DCDCLNVCTRL_LNATT_SHIFT   1
 
#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT   0x00000071UL
 
#define _EMU_DCDCLNVCTRL_LNVREF_MASK   0x7F00UL
 
#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT   8
 
#define _EMU_DCDCLNVCTRL_MASK   0x00007F02UL
 
#define _EMU_DCDCLNVCTRL_RESETVALUE   0x00007100UL
 
#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT   0x00000001UL
 
#define _EMU_DCDCLPCTRL_LPBLANK_MASK   0x6000000UL
 
#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT   25
 
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK   0xF000UL
 
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT   12
 
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT   0x00000001UL
 
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK   0x1000000UL
 
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT   24
 
#define _EMU_DCDCLPCTRL_MASK   0x0700F000UL
 
#define _EMU_DCDCLPCTRL_RESETVALUE   0x03000000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0   0x00000000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1   0x00000001UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2   0x00000002UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3   0x00000003UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT   0x00000003UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK   0x300UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT   8
 
#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK   0xF000UL
 
#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT   12
 
#define _EMU_DCDCLPEM01CFG_MASK   0x0000F300UL
 
#define _EMU_DCDCLPEM01CFG_RESETVALUE   0x00000300UL
 
#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT   0x00000000UL
 
#define _EMU_DCDCLPVCTRL_LPATT_DIV4   0x00000000UL
 
#define _EMU_DCDCLPVCTRL_LPATT_DIV8   0x00000001UL
 
#define _EMU_DCDCLPVCTRL_LPATT_MASK   0x1UL
 
#define _EMU_DCDCLPVCTRL_LPATT_SHIFT   0
 
#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT   0x000000B4UL
 
#define _EMU_DCDCLPVCTRL_LPVREF_MASK   0x1FEUL
 
#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT   1
 
#define _EMU_DCDCLPVCTRL_MASK   0x000001FFUL
 
#define _EMU_DCDCLPVCTRL_RESETVALUE   0x00000168UL
 
#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK   0xF0000UL
 
#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT   16
 
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT   0x00000003UL
 
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK   0x7000000UL
 
#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT   24
 
#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK   0x1UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT   0
 
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK   0x20UL
 
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT   5
 
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK   0x700000UL
 
#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT   20
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2   0x00000002UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3   0x00000003UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT   0x00000000UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK   0x30000000UL
 
#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT   28
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK   0x2UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT   1
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT   0x00000001UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK   0x4UL
 
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT   2
 
#define _EMU_DCDCMISCCTRL_MASK   0x377FFF27UL
 
#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT   0x00000007UL
 
#define _EMU_DCDCMISCCTRL_NFETCNT_MASK   0xF000UL
 
#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT   12
 
#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT   0x00000007UL
 
#define _EMU_DCDCMISCCTRL_PFETCNT_MASK   0xF00UL
 
#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT   8
 
#define _EMU_DCDCMISCCTRL_RESETVALUE   0x03107706UL
 
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT   0x00000000UL
 
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK   0x1UL
 
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT   0
 
#define _EMU_DCDCSYNC_MASK   0x00000001UL
 
#define _EMU_DCDCSYNC_RESETVALUE   0x00000000UL
 
#define _EMU_DCDCZDETCTRL_MASK   0x00000370UL
 
#define _EMU_DCDCZDETCTRL_RESETVALUE   0x00000150UL
 
#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT   0x00000001UL
 
#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK   0x300UL
 
#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT   8
 
#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT   0x00000005UL
 
#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK   0x70UL
 
#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT   4
 
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK   0x1UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT   0
 
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK   0x2UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT   1
 
#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK   0x200000UL
 
#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT   21
 
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK   0x200UL
 
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT   9
 
#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK   0x100000UL
 
#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT   20
 
#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK   0x4000UL
 
#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT   14
 
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK   0x80UL
 
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT   7
 
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK   0x20UL
 
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT   5
 
#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK   0x40UL
 
#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT   6
 
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK   0x100UL
 
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT   8
 
#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK   0x20000UL
 
#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT   17
 
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK   0x2000UL
 
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT   13
 
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK   0x400UL
 
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT   10
 
#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK   0x40000UL
 
#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT   18
 
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK   0x8000UL
 
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT   15
 
#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK   0x10000UL
 
#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT   16
 
#define _EMU_EM23PERNORETAINCMD_MASK   0x01B7FFFFUL
 
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK   0x4UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT   2
 
#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK   0x8UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT   3
 
#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK   0x10UL
 
#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT   4
 
#define _EMU_EM23PERNORETAINCMD_RESETVALUE   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK   0x800000UL
 
#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT   23
 
#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_MASK   0x1000000UL
 
#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_SHIFT   24
 
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK   0x800UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT   11
 
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK   0x1000UL
 
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT   12
 
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK   0x1UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT   0
 
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK   0x2UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT   1
 
#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK   0x200000UL
 
#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT   21
 
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK   0x200UL
 
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT   9
 
#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK   0x100000UL
 
#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT   20
 
#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK   0x4000UL
 
#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT   14
 
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK   0x20UL
 
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT   5
 
#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK   0x40UL
 
#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT   6
 
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK   0x100UL
 
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT   8
 
#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK   0x20000UL
 
#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT   17
 
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK   0x2000UL
 
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT   13
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK   0x400UL
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT   10
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK   0x40000UL
 
#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT   18
 
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK   0x8000UL
 
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT   15
 
#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK   0x10000UL
 
#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT   16
 
#define _EMU_EM23PERNORETAINCTRL_MASK   0x01B7FFFFUL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK   0x4UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT   2
 
#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK   0x8UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT   3
 
#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK   0x10UL
 
#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT   4
 
#define _EMU_EM23PERNORETAINCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK   0x800000UL
 
#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT   23
 
#define _EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_USBDIS_MASK   0x1000000UL
 
#define _EMU_EM23PERNORETAINCTRL_USBDIS_SHIFT   24
 
#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK   0x80UL
 
#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT   7
 
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK   0x800UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT   11
 
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK   0x1000UL
 
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT   12
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK   0x1UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT   0
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK   0x2UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT   1
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK   0x200000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT   21
 
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK   0x200UL
 
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT   9
 
#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK   0x100000UL
 
#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT   20
 
#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK   0x4000UL
 
#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT   14
 
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK   0x80UL
 
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT   7
 
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK   0x20UL
 
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT   5
 
#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK   0x40UL
 
#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT   6
 
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK   0x100UL
 
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT   8
 
#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK   0x20000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT   17
 
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK   0x2000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT   13
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK   0x400UL
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT   10
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK   0x40000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT   18
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK   0x8000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT   15
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK   0x10000UL
 
#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT   16
 
#define _EMU_EM23PERNORETAINSTATUS_MASK   0x01B7FFFFUL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK   0x4UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT   2
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK   0x8UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT   3
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK   0x10UL
 
#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT   4
 
#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK   0x800000UL
 
#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT   23
 
#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_MASK   0x1000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_SHIFT   24
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK   0x800UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT   11
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT   0x00000000UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK   0x1000UL
 
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT   12
 
#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_EM4ENTRY_MASK   0x30000UL
 
#define _EMU_EM4CTRL_EM4ENTRY_SHIFT   16
 
#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE   0x00000000UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT   0x00000001UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_MASK   0x30UL
 
#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT   4
 
#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH   0x00000002UL
 
#define _EMU_EM4CTRL_EM4STATE_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_EM4STATE_EM4H   0x00000001UL
 
#define _EMU_EM4CTRL_EM4STATE_EM4S   0x00000000UL
 
#define _EMU_EM4CTRL_EM4STATE_MASK   0x1UL
 
#define _EMU_EM4CTRL_EM4STATE_SHIFT   0
 
#define _EMU_EM4CTRL_MASK   0x0003003FUL
 
#define _EMU_EM4CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINLFRCO_MASK   0x2UL
 
#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT   1
 
#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINLFXO_MASK   0x4UL
 
#define _EMU_EM4CTRL_RETAINLFXO_SHIFT   2
 
#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT   0x00000000UL
 
#define _EMU_EM4CTRL_RETAINULFRCO_MASK   0x8UL
 
#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT   3
 
#define _EMU_IEN_BURDY_DEFAULT   0x00000000UL
 
#define _EMU_IEN_BURDY_MASK   0x400000UL
 
#define _EMU_IEN_BURDY_SHIFT   22
 
#define _EMU_IEN_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IEN_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IEN_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IEN_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IEN_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IEN_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IEN_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IEN_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IEN_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IEN_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IEN_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IEN_EM23WAKEUP_SHIFT   24
 
#define _EMU_IEN_MASK   0xE3DF37FFUL
 
#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IEN_R5VREADY_DEFAULT   0x00000000UL
 
#define _EMU_IEN_R5VREADY_MASK   0x400UL
 
#define _EMU_IEN_R5VREADY_SHIFT   10
 
#define _EMU_IEN_R5VVSINT_DEFAULT   0x00000000UL
 
#define _EMU_IEN_R5VVSINT_MASK   0x800000UL
 
#define _EMU_IEN_R5VVSINT_SHIFT   23
 
#define _EMU_IEN_RESETVALUE   0x00000000UL
 
#define _EMU_IEN_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IEN_TEMP_MASK   0x20000000UL
 
#define _EMU_IEN_TEMP_SHIFT   29
 
#define _EMU_IEN_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IEN_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IEN_TEMPHIGH_SHIFT   31
 
#define _EMU_IEN_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IEN_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IEN_TEMPLOW_SHIFT   30
 
#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IEN_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IEN_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IEN_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IEN_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IEN_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IEN_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IEN_VMONBUVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONBUVDDFALL_MASK   0x1000UL
 
#define _EMU_IEN_VMONBUVDDFALL_SHIFT   12
 
#define _EMU_IEN_VMONBUVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONBUVDDRISE_MASK   0x2000UL
 
#define _EMU_IEN_VMONBUVDDRISE_SHIFT   13
 
#define _EMU_IEN_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IEN_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IEN_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IEN_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IEN_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IEN_VMONIO0FALL_SHIFT   6
 
#define _EMU_IEN_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IEN_VMONIO0RISE_SHIFT   7
 
#define _EMU_IEN_VMONIO1FALL_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONIO1FALL_MASK   0x100UL
 
#define _EMU_IEN_VMONIO1FALL_SHIFT   8
 
#define _EMU_IEN_VMONIO1RISE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VMONIO1RISE_MASK   0x200UL
 
#define _EMU_IEN_VMONIO1RISE_SHIFT   9
 
#define _EMU_IEN_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IEN_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IEN_VSCALEDONE_SHIFT   25
 
#define _EMU_IF_BURDY_DEFAULT   0x00000000UL
 
#define _EMU_IF_BURDY_MASK   0x400000UL
 
#define _EMU_IF_BURDY_SHIFT   22
 
#define _EMU_IF_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IF_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IF_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IF_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IF_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IF_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IF_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IF_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IF_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IF_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IF_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IF_EM23WAKEUP_SHIFT   24
 
#define _EMU_IF_MASK   0xE3DF37FFUL
 
#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IF_R5VREADY_DEFAULT   0x00000000UL
 
#define _EMU_IF_R5VREADY_MASK   0x400UL
 
#define _EMU_IF_R5VREADY_SHIFT   10
 
#define _EMU_IF_R5VVSINT_DEFAULT   0x00000000UL
 
#define _EMU_IF_R5VVSINT_MASK   0x800000UL
 
#define _EMU_IF_R5VVSINT_SHIFT   23
 
#define _EMU_IF_RESETVALUE   0x00000000UL
 
#define _EMU_IF_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IF_TEMP_MASK   0x20000000UL
 
#define _EMU_IF_TEMP_SHIFT   29
 
#define _EMU_IF_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IF_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IF_TEMPHIGH_SHIFT   31
 
#define _EMU_IF_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IF_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IF_TEMPLOW_SHIFT   30
 
#define _EMU_IF_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IF_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IF_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IF_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IF_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IF_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IF_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IF_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IF_VMONBUVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONBUVDDFALL_MASK   0x1000UL
 
#define _EMU_IF_VMONBUVDDFALL_SHIFT   12
 
#define _EMU_IF_VMONBUVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONBUVDDRISE_MASK   0x2000UL
 
#define _EMU_IF_VMONBUVDDRISE_SHIFT   13
 
#define _EMU_IF_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IF_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IF_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IF_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IF_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IF_VMONIO0FALL_SHIFT   6
 
#define _EMU_IF_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IF_VMONIO0RISE_SHIFT   7
 
#define _EMU_IF_VMONIO1FALL_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONIO1FALL_MASK   0x100UL
 
#define _EMU_IF_VMONIO1FALL_SHIFT   8
 
#define _EMU_IF_VMONIO1RISE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VMONIO1RISE_MASK   0x200UL
 
#define _EMU_IF_VMONIO1RISE_SHIFT   9
 
#define _EMU_IF_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IF_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IF_VSCALEDONE_SHIFT   25
 
#define _EMU_IFC_BURDY_DEFAULT   0x00000000UL
 
#define _EMU_IFC_BURDY_MASK   0x400000UL
 
#define _EMU_IFC_BURDY_SHIFT   22
 
#define _EMU_IFC_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IFC_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IFC_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IFC_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFC_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IFC_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IFC_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFC_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IFC_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IFC_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IFC_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IFC_EM23WAKEUP_SHIFT   24
 
#define _EMU_IFC_MASK   0xE3DF37FFUL
 
#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IFC_R5VREADY_DEFAULT   0x00000000UL
 
#define _EMU_IFC_R5VREADY_MASK   0x400UL
 
#define _EMU_IFC_R5VREADY_SHIFT   10
 
#define _EMU_IFC_R5VVSINT_DEFAULT   0x00000000UL
 
#define _EMU_IFC_R5VVSINT_MASK   0x800000UL
 
#define _EMU_IFC_R5VVSINT_SHIFT   23
 
#define _EMU_IFC_RESETVALUE   0x00000000UL
 
#define _EMU_IFC_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IFC_TEMP_MASK   0x20000000UL
 
#define _EMU_IFC_TEMP_SHIFT   29
 
#define _EMU_IFC_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IFC_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IFC_TEMPHIGH_SHIFT   31
 
#define _EMU_IFC_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IFC_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IFC_TEMPLOW_SHIFT   30
 
#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IFC_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IFC_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IFC_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IFC_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IFC_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IFC_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IFC_VMONBUVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONBUVDDFALL_MASK   0x1000UL
 
#define _EMU_IFC_VMONBUVDDFALL_SHIFT   12
 
#define _EMU_IFC_VMONBUVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONBUVDDRISE_MASK   0x2000UL
 
#define _EMU_IFC_VMONBUVDDRISE_SHIFT   13
 
#define _EMU_IFC_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IFC_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IFC_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IFC_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IFC_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IFC_VMONIO0FALL_SHIFT   6
 
#define _EMU_IFC_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IFC_VMONIO0RISE_SHIFT   7
 
#define _EMU_IFC_VMONIO1FALL_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONIO1FALL_MASK   0x100UL
 
#define _EMU_IFC_VMONIO1FALL_SHIFT   8
 
#define _EMU_IFC_VMONIO1RISE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VMONIO1RISE_MASK   0x200UL
 
#define _EMU_IFC_VMONIO1RISE_SHIFT   9
 
#define _EMU_IFC_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IFC_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IFC_VSCALEDONE_SHIFT   25
 
#define _EMU_IFS_BURDY_DEFAULT   0x00000000UL
 
#define _EMU_IFS_BURDY_MASK   0x400000UL
 
#define _EMU_IFS_BURDY_SHIFT   22
 
#define _EMU_IFS_DCDCINBYPASS_DEFAULT   0x00000000UL
 
#define _EMU_IFS_DCDCINBYPASS_MASK   0x100000UL
 
#define _EMU_IFS_DCDCINBYPASS_SHIFT   20
 
#define _EMU_IFS_DCDCLNRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFS_DCDCLNRUNNING_MASK   0x80000UL
 
#define _EMU_IFS_DCDCLNRUNNING_SHIFT   19
 
#define _EMU_IFS_DCDCLPRUNNING_DEFAULT   0x00000000UL
 
#define _EMU_IFS_DCDCLPRUNNING_MASK   0x40000UL
 
#define _EMU_IFS_DCDCLPRUNNING_SHIFT   18
 
#define _EMU_IFS_EM23WAKEUP_DEFAULT   0x00000000UL
 
#define _EMU_IFS_EM23WAKEUP_MASK   0x1000000UL
 
#define _EMU_IFS_EM23WAKEUP_SHIFT   24
 
#define _EMU_IFS_MASK   0xE3DF37FFUL
 
#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK   0x20000UL
 
#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT   17
 
#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL
 
#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK   0x10000UL
 
#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT   16
 
#define _EMU_IFS_R5VREADY_DEFAULT   0x00000000UL
 
#define _EMU_IFS_R5VREADY_MASK   0x400UL
 
#define _EMU_IFS_R5VREADY_SHIFT   10
 
#define _EMU_IFS_R5VVSINT_DEFAULT   0x00000000UL
 
#define _EMU_IFS_R5VVSINT_MASK   0x800000UL
 
#define _EMU_IFS_R5VVSINT_SHIFT   23
 
#define _EMU_IFS_RESETVALUE   0x00000000UL
 
#define _EMU_IFS_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_IFS_TEMP_MASK   0x20000000UL
 
#define _EMU_IFS_TEMP_SHIFT   29
 
#define _EMU_IFS_TEMPHIGH_DEFAULT   0x00000000UL
 
#define _EMU_IFS_TEMPHIGH_MASK   0x80000000UL
 
#define _EMU_IFS_TEMPHIGH_SHIFT   31
 
#define _EMU_IFS_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_IFS_TEMPLOW_MASK   0x40000000UL
 
#define _EMU_IFS_TEMPLOW_SHIFT   30
 
#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONALTAVDDFALL_MASK   0x4UL
 
#define _EMU_IFS_VMONALTAVDDFALL_SHIFT   2
 
#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONALTAVDDRISE_MASK   0x8UL
 
#define _EMU_IFS_VMONALTAVDDRISE_SHIFT   3
 
#define _EMU_IFS_VMONAVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONAVDDFALL_MASK   0x1UL
 
#define _EMU_IFS_VMONAVDDFALL_SHIFT   0
 
#define _EMU_IFS_VMONAVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONAVDDRISE_MASK   0x2UL
 
#define _EMU_IFS_VMONAVDDRISE_SHIFT   1
 
#define _EMU_IFS_VMONBUVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONBUVDDFALL_MASK   0x1000UL
 
#define _EMU_IFS_VMONBUVDDFALL_SHIFT   12
 
#define _EMU_IFS_VMONBUVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONBUVDDRISE_MASK   0x2000UL
 
#define _EMU_IFS_VMONBUVDDRISE_SHIFT   13
 
#define _EMU_IFS_VMONDVDDFALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONDVDDFALL_MASK   0x10UL
 
#define _EMU_IFS_VMONDVDDFALL_SHIFT   4
 
#define _EMU_IFS_VMONDVDDRISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONDVDDRISE_MASK   0x20UL
 
#define _EMU_IFS_VMONDVDDRISE_SHIFT   5
 
#define _EMU_IFS_VMONIO0FALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONIO0FALL_MASK   0x40UL
 
#define _EMU_IFS_VMONIO0FALL_SHIFT   6
 
#define _EMU_IFS_VMONIO0RISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONIO0RISE_MASK   0x80UL
 
#define _EMU_IFS_VMONIO0RISE_SHIFT   7
 
#define _EMU_IFS_VMONIO1FALL_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONIO1FALL_MASK   0x100UL
 
#define _EMU_IFS_VMONIO1FALL_SHIFT   8
 
#define _EMU_IFS_VMONIO1RISE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VMONIO1RISE_MASK   0x200UL
 
#define _EMU_IFS_VMONIO1RISE_SHIFT   9
 
#define _EMU_IFS_VSCALEDONE_DEFAULT   0x00000000UL
 
#define _EMU_IFS_VSCALEDONE_MASK   0x2000000UL
 
#define _EMU_IFS_VSCALEDONE_SHIFT   25
 
#define _EMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL
 
#define _EMU_LOCK_LOCKKEY_LOCK   0x00000000UL
 
#define _EMU_LOCK_LOCKKEY_LOCKED   0x00000001UL
 
#define _EMU_LOCK_LOCKKEY_MASK   0xFFFFUL
 
#define _EMU_LOCK_LOCKKEY_SHIFT   0
 
#define _EMU_LOCK_LOCKKEY_UNLOCK   0x0000ADE8UL
 
#define _EMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL
 
#define _EMU_LOCK_MASK   0x0000FFFFUL
 
#define _EMU_LOCK_RESETVALUE   0x00000000UL
 
#define _EMU_PWRCTRL_ANASW_AVDD   0x00000000UL
 
#define _EMU_PWRCTRL_ANASW_DEFAULT   0x00000000UL
 
#define _EMU_PWRCTRL_ANASW_DVDD   0x00000001UL
 
#define _EMU_PWRCTRL_ANASW_MASK   0x20UL
 
#define _EMU_PWRCTRL_ANASW_SHIFT   5
 
#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT   0x00000000UL
 
#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK   0x2000UL
 
#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT   13
 
#define _EMU_PWRCTRL_MASK   0x00002420UL
 
#define _EMU_PWRCTRL_REGPWRSEL_AVDD   0x00000000UL
 
#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT   0x00000000UL
 
#define _EMU_PWRCTRL_REGPWRSEL_DVDD   0x00000001UL
 
#define _EMU_PWRCTRL_REGPWRSEL_MASK   0x400UL
 
#define _EMU_PWRCTRL_REGPWRSEL_SHIFT   10
 
#define _EMU_PWRCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_PWRLOCK_LOCKKEY_DEFAULT   0x00000000UL
 
#define _EMU_PWRLOCK_LOCKKEY_LOCK   0x00000000UL
 
#define _EMU_PWRLOCK_LOCKKEY_LOCKED   0x00000001UL
 
#define _EMU_PWRLOCK_LOCKKEY_MASK   0xFFFFUL
 
#define _EMU_PWRLOCK_LOCKKEY_SHIFT   0
 
#define _EMU_PWRLOCK_LOCKKEY_UNLOCK   0x0000ADE8UL
 
#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED   0x00000000UL
 
#define _EMU_PWRLOCK_MASK   0x0000FFFFUL
 
#define _EMU_PWRLOCK_RESETVALUE   0x00000000UL
 
#define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT   0x00000000UL
 
#define _EMU_R5VADCCTRL_AMUXSEL_MASK   0xF000UL
 
#define _EMU_R5VADCCTRL_AMUXSEL_SHIFT   12
 
#define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10   0x00000000UL
 
#define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON   0x00000004UL
 
#define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10   0x00000001UL
 
#define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON   0x00000003UL
 
#define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6   0x00000002UL
 
#define _EMU_R5VADCCTRL_ENAMUX_DEFAULT   0x00000000UL
 
#define _EMU_R5VADCCTRL_ENAMUX_MASK   0x1UL
 
#define _EMU_R5VADCCTRL_ENAMUX_SHIFT   0
 
#define _EMU_R5VADCCTRL_MASK   0x0000F001UL
 
#define _EMU_R5VADCCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_R5VCTRL_BYPASS_DEFAULT   0x00000000UL
 
#define _EMU_R5VCTRL_BYPASS_MASK   0x1UL
 
#define _EMU_R5VCTRL_BYPASS_SHIFT   0
 
#define _EMU_R5VCTRL_EM4WUEN_DEFAULT   0x00000000UL
 
#define _EMU_R5VCTRL_EM4WUEN_MASK   0x2UL
 
#define _EMU_R5VCTRL_EM4WUEN_SHIFT   1
 
#define _EMU_R5VCTRL_IMONEN_DEFAULT   0x00000000UL
 
#define _EMU_R5VCTRL_IMONEN_MASK   0x4UL
 
#define _EMU_R5VCTRL_IMONEN_SHIFT   2
 
#define _EMU_R5VCTRL_INPUTMODE_AUTO   0x00000000UL
 
#define _EMU_R5VCTRL_INPUTMODE_DEFAULT   0x00000000UL
 
#define _EMU_R5VCTRL_INPUTMODE_MASK   0x300UL
 
#define _EMU_R5VCTRL_INPUTMODE_SHIFT   8
 
#define _EMU_R5VCTRL_INPUTMODE_VBUS   0x00000001UL
 
#define _EMU_R5VCTRL_INPUTMODE_VREGI   0x00000002UL
 
#define _EMU_R5VCTRL_MASK   0x00000307UL
 
#define _EMU_R5VCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_R5VDETCTRL_MASK   0x00000007UL
 
#define _EMU_R5VDETCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT   0x00000000UL
 
#define _EMU_R5VDETCTRL_VBUSDETDIS_MASK   0x2UL
 
#define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT   1
 
#define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT   0x00000000UL
 
#define _EMU_R5VDETCTRL_VREGIDETDIS_MASK   0x1UL
 
#define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT   0
 
#define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT   0x00000000UL
 
#define _EMU_R5VDETCTRL_VREGODETDIS_MASK   0x4UL
 
#define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT   2
 
#define _EMU_R5VOUTLEVEL_MASK   0x0000000FUL
 
#define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT   0x00000001UL
 
#define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK   0xFUL
 
#define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT   0
 
#define _EMU_R5VOUTLEVEL_RESETVALUE   0x00000001UL
 
#define _EMU_R5VSTATUS_COLDSTART_DEFAULT   0x00000001UL
 
#define _EMU_R5VSTATUS_COLDSTART_MASK   0x20UL
 
#define _EMU_R5VSTATUS_COLDSTART_SHIFT   5
 
#define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT   0x00000000UL
 
#define _EMU_R5VSTATUS_LDODROPOUTDET_MASK   0x10UL
 
#define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT   4
 
#define _EMU_R5VSTATUS_MASK   0x0000003FUL
 
#define _EMU_R5VSTATUS_RESETVALUE   0x00000020UL
 
#define _EMU_R5VSTATUS_VBUSDET_DEFAULT   0x00000000UL
 
#define _EMU_R5VSTATUS_VBUSDET_MASK   0x2UL
 
#define _EMU_R5VSTATUS_VBUSDET_SHIFT   1
 
#define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT   0x00000000UL
 
#define _EMU_R5VSTATUS_VBUSGTVREGI_MASK   0x8UL
 
#define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT   3
 
#define _EMU_R5VSTATUS_VREGIDET_DEFAULT   0x00000000UL
 
#define _EMU_R5VSTATUS_VREGIDET_MASK   0x1UL
 
#define _EMU_R5VSTATUS_VREGIDET_SHIFT   0
 
#define _EMU_R5VSTATUS_VREGODET_DEFAULT   0x00000000UL
 
#define _EMU_R5VSTATUS_VREGODET_MASK   0x4UL
 
#define _EMU_R5VSTATUS_VREGODET_SHIFT   2
 
#define _EMU_R5VSYNC_MASK   0x00000001UL
 
#define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT   0x00000000UL
 
#define _EMU_R5VSYNC_OUTLEVELBUSY_MASK   0x1UL
 
#define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT   0
 
#define _EMU_R5VSYNC_RESETVALUE   0x00000000UL
 
#define _EMU_RAM0CTRL_MASK   0x00000007UL
 
#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3   0x00000007UL
 
#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3   0x00000006UL
 
#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3   0x00000004UL
 
#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT   0x00000000UL
 
#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK   0x7UL
 
#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE   0x00000000UL
 
#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT   0
 
#define _EMU_RAM0CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_RAM1CTRL_MASK   0x0000000FUL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3   0x0000000FUL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3   0x0000000EUL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3   0x0000000CUL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3   0x00000008UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT   0x00000000UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK   0xFUL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE   0x00000000UL
 
#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT   0
 
#define _EMU_RAM1CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_RAM2CTRL_MASK   0x0000000FUL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3   0x0000000FUL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3   0x0000000EUL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3   0x0000000CUL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3   0x00000008UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT   0x00000000UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK   0xFUL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE   0x00000000UL
 
#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT   0
 
#define _EMU_RAM2CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_STATUS_BURDY_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_BURDY_MASK   0x1000UL
 
#define _EMU_STATUS_BURDY_SHIFT   12
 
#define _EMU_STATUS_EM4IORET_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_EM4IORET_DISABLED   0x00000000UL
 
#define _EMU_STATUS_EM4IORET_ENABLED   0x00000001UL
 
#define _EMU_STATUS_EM4IORET_MASK   0x100000UL
 
#define _EMU_STATUS_EM4IORET_SHIFT   20
 
#define _EMU_STATUS_MASK   0x041710BFUL
 
#define _EMU_STATUS_RESETVALUE   0x00000000UL
 
#define _EMU_STATUS_TEMPACTIVE_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_TEMPACTIVE_MASK   0x4000000UL
 
#define _EMU_STATUS_TEMPACTIVE_SHIFT   26
 
#define _EMU_STATUS_VMONALTAVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONALTAVDD_MASK   0x4UL
 
#define _EMU_STATUS_VMONALTAVDD_SHIFT   2
 
#define _EMU_STATUS_VMONAVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONAVDD_MASK   0x2UL
 
#define _EMU_STATUS_VMONAVDD_SHIFT   1
 
#define _EMU_STATUS_VMONBUVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONBUVDD_MASK   0x80UL
 
#define _EMU_STATUS_VMONBUVDD_SHIFT   7
 
#define _EMU_STATUS_VMONDVDD_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONDVDD_MASK   0x8UL
 
#define _EMU_STATUS_VMONDVDD_SHIFT   3
 
#define _EMU_STATUS_VMONIO0_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONIO0_MASK   0x10UL
 
#define _EMU_STATUS_VMONIO0_SHIFT   4
 
#define _EMU_STATUS_VMONIO1_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONIO1_MASK   0x20UL
 
#define _EMU_STATUS_VMONIO1_SHIFT   5
 
#define _EMU_STATUS_VMONRDY_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VMONRDY_MASK   0x1UL
 
#define _EMU_STATUS_VMONRDY_SHIFT   0
 
#define _EMU_STATUS_VSCALE_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VSCALE_MASK   0x30000UL
 
#define _EMU_STATUS_VSCALE_RESV   0x00000003UL
 
#define _EMU_STATUS_VSCALE_SHIFT   16
 
#define _EMU_STATUS_VSCALE_VSCALE0   0x00000002UL
 
#define _EMU_STATUS_VSCALE_VSCALE2   0x00000000UL
 
#define _EMU_STATUS_VSCALEBUSY_DEFAULT   0x00000000UL
 
#define _EMU_STATUS_VSCALEBUSY_MASK   0x40000UL
 
#define _EMU_STATUS_VSCALEBUSY_SHIFT   18
 
#define _EMU_TEMP_MASK   0x000000FFUL
 
#define _EMU_TEMP_RESETVALUE   0x00000000UL
 
#define _EMU_TEMP_TEMP_DEFAULT   0x00000000UL
 
#define _EMU_TEMP_TEMP_MASK   0xFFUL
 
#define _EMU_TEMP_TEMP_SHIFT   0
 
#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT   0x00000000UL
 
#define _EMU_TEMPLIMITS_EM4WUEN_MASK   0x10000UL
 
#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT   16
 
#define _EMU_TEMPLIMITS_MASK   0x0001FFFFUL
 
#define _EMU_TEMPLIMITS_RESETVALUE   0x0000FF00UL
 
#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT   0x000000FFUL
 
#define _EMU_TEMPLIMITS_TEMPHIGH_MASK   0xFF00UL
 
#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT   8
 
#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT   0x00000000UL
 
#define _EMU_TEMPLIMITS_TEMPLOW_MASK   0xFFUL
 
#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT   0
 
#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_EN_MASK   0x1UL
 
#define _EMU_VMONALTAVDDCTRL_EN_SHIFT   0
 
#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONALTAVDDCTRL_MASK   0x0000FF0DUL
 
#define _EMU_VMONALTAVDDCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT   8
 
#define _EMU_VMONAVDDCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_EN_MASK   0x1UL
 
#define _EMU_VMONAVDDCTRL_EN_SHIFT   0
 
#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT   12
 
#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK   0xF00UL
 
#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT   8
 
#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONAVDDCTRL_MASK   0x00FFFF0DUL
 
#define _EMU_VMONAVDDCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK   0xF00000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT   20
 
#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK   0xF0000UL
 
#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT   16
 
#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONAVDDCTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONBUVDDCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONBUVDDCTRL_EN_MASK   0x1UL
 
#define _EMU_VMONBUVDDCTRL_EN_SHIFT   0
 
#define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONBUVDDCTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONBUVDDCTRL_MASK   0x0000FF0DUL
 
#define _EMU_VMONBUVDDCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONBUVDDCTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONBUVDDCTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT   8
 
#define _EMU_VMONDVDDCTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_EN_MASK   0x1UL
 
#define _EMU_VMONDVDDCTRL_EN_SHIFT   0
 
#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONDVDDCTRL_MASK   0x0000FF0DUL
 
#define _EMU_VMONDVDDCTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONDVDDCTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT   8
 
#define _EMU_VMONIO0CTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_EN_MASK   0x1UL
 
#define _EMU_VMONIO0CTRL_EN_SHIFT   0
 
#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONIO0CTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONIO0CTRL_MASK   0x0000FF1DUL
 
#define _EMU_VMONIO0CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_RETDIS_MASK   0x10UL
 
#define _EMU_VMONIO0CTRL_RETDIS_SHIFT   4
 
#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONIO0CTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO0CTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT   8
 
#define _EMU_VMONIO1CTRL_EN_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO1CTRL_EN_MASK   0x1UL
 
#define _EMU_VMONIO1CTRL_EN_SHIFT   0
 
#define _EMU_VMONIO1CTRL_FALLWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO1CTRL_FALLWU_MASK   0x8UL
 
#define _EMU_VMONIO1CTRL_FALLWU_SHIFT   3
 
#define _EMU_VMONIO1CTRL_MASK   0x0000FF1DUL
 
#define _EMU_VMONIO1CTRL_RESETVALUE   0x00000000UL
 
#define _EMU_VMONIO1CTRL_RETDIS_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO1CTRL_RETDIS_MASK   0x10UL
 
#define _EMU_VMONIO1CTRL_RETDIS_SHIFT   4
 
#define _EMU_VMONIO1CTRL_RISEWU_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO1CTRL_RISEWU_MASK   0x4UL
 
#define _EMU_VMONIO1CTRL_RISEWU_SHIFT   2
 
#define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO1CTRL_THRESCOARSE_MASK   0xF000UL
 
#define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT   12
 
#define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT   0x00000000UL
 
#define _EMU_VMONIO1CTRL_THRESFINE_MASK   0xF00UL
 
#define _EMU_VMONIO1CTRL_THRESFINE_SHIFT   8
 
#define EMU_BUCTRL_BUACTPWRCON_BUMAIN   (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16)
 
#define EMU_BUCTRL_BUACTPWRCON_DEFAULT   (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16)
 
#define EMU_BUCTRL_BUACTPWRCON_MAINBU   (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16)
 
#define EMU_BUCTRL_BUACTPWRCON_NODIODE   (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16)
 
#define EMU_BUCTRL_BUACTPWRCON_NONE   (_EMU_BUCTRL_BUACTPWRCON_NONE << 16)
 
#define EMU_BUCTRL_BUINACTPWRCON_BUMAIN   (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20)
 
#define EMU_BUCTRL_BUINACTPWRCON_DEFAULT   (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20)
 
#define EMU_BUCTRL_BUINACTPWRCON_MAINBU   (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20)
 
#define EMU_BUCTRL_BUINACTPWRCON_NODIODE   (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20)
 
#define EMU_BUCTRL_BUINACTPWRCON_NONE   (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20)
 
#define EMU_BUCTRL_BUVINPROBEEN   (0x1UL << 2)
 
#define EMU_BUCTRL_BUVINPROBEEN_DEFAULT   (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2)
 
#define EMU_BUCTRL_DISMAXCOMP   (0x1UL << 31)
 
#define EMU_BUCTRL_DISMAXCOMP_DEFAULT   (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31)
 
#define EMU_BUCTRL_EN   (0x1UL << 0)
 
#define EMU_BUCTRL_EN_DEFAULT   (_EMU_BUCTRL_EN_DEFAULT << 0)
 
#define EMU_BUCTRL_PWRRES_DEFAULT   (_EMU_BUCTRL_PWRRES_DEFAULT << 12)
 
#define EMU_BUCTRL_PWRRES_RES0   (_EMU_BUCTRL_PWRRES_RES0 << 12)
 
#define EMU_BUCTRL_PWRRES_RES1   (_EMU_BUCTRL_PWRRES_RES1 << 12)
 
#define EMU_BUCTRL_PWRRES_RES2   (_EMU_BUCTRL_PWRRES_RES2 << 12)
 
#define EMU_BUCTRL_PWRRES_RES3   (_EMU_BUCTRL_PWRRES_RES3 << 12)
 
#define EMU_BUCTRL_STATEN   (0x1UL << 1)
 
#define EMU_BUCTRL_STATEN_DEFAULT   (_EMU_BUCTRL_STATEN_DEFAULT << 1)
 
#define EMU_BUCTRL_VOUTRES_DEFAULT   (_EMU_BUCTRL_VOUTRES_DEFAULT << 8)
 
#define EMU_BUCTRL_VOUTRES_DIS   (_EMU_BUCTRL_VOUTRES_DIS << 8)
 
#define EMU_BUCTRL_VOUTRES_MED   (_EMU_BUCTRL_VOUTRES_MED << 8)
 
#define EMU_BUCTRL_VOUTRES_STRONG   (_EMU_BUCTRL_VOUTRES_STRONG << 8)
 
#define EMU_BUCTRL_VOUTRES_WEAK   (_EMU_BUCTRL_VOUTRES_WEAK << 8)
 
#define EMU_CMD_EM01VSCALE0   (0x1UL << 4)
 
#define EMU_CMD_EM01VSCALE0_DEFAULT   (_EMU_CMD_EM01VSCALE0_DEFAULT << 4)
 
#define EMU_CMD_EM01VSCALE2   (0x1UL << 6)
 
#define EMU_CMD_EM01VSCALE2_DEFAULT   (_EMU_CMD_EM01VSCALE2_DEFAULT << 6)
 
#define EMU_CMD_EM4UNLATCH   (0x1UL << 0)
 
#define EMU_CMD_EM4UNLATCH_DEFAULT   (_EMU_CMD_EM4UNLATCH_DEFAULT << 0)
 
#define EMU_CTRL_EM01LD   (0x1UL << 3)
 
#define EMU_CTRL_EM01LD_DEFAULT   (_EMU_CTRL_EM01LD_DEFAULT << 3)
 
#define EMU_CTRL_EM23VSCALE_DEFAULT   (_EMU_CTRL_EM23VSCALE_DEFAULT << 8)
 
#define EMU_CTRL_EM23VSCALE_RESV   (_EMU_CTRL_EM23VSCALE_RESV << 8)
 
#define EMU_CTRL_EM23VSCALE_VSCALE0   (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8)
 
#define EMU_CTRL_EM23VSCALE_VSCALE2   (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8)
 
#define EMU_CTRL_EM23VSCALEAUTOWSEN   (0x1UL << 4)
 
#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT   (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4)
 
#define EMU_CTRL_EM2BLOCK   (0x1UL << 1)
 
#define EMU_CTRL_EM2BLOCK_DEFAULT   (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
 
#define EMU_CTRL_EM2BODDIS   (0x1UL << 2)
 
#define EMU_CTRL_EM2BODDIS_DEFAULT   (_EMU_CTRL_EM2BODDIS_DEFAULT << 2)
 
#define EMU_CTRL_EM4HVSCALE_DEFAULT   (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16)
 
#define EMU_CTRL_EM4HVSCALE_RESV   (_EMU_CTRL_EM4HVSCALE_RESV << 16)
 
#define EMU_CTRL_EM4HVSCALE_VSCALE0   (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16)
 
#define EMU_CTRL_EM4HVSCALE_VSCALE2   (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16)
 
#define EMU_DCDCCLIMCTRL_BYPLIMEN   (0x1UL << 13)
 
#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT   (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)
 
#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT   (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8)
 
#define EMU_DCDCCTRL_DCDCMODE_BYPASS   (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_DEFAULT   (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE   (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER   (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)
 
#define EMU_DCDCCTRL_DCDCMODE_OFF   (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)
 
#define EMU_DCDCCTRL_DCDCMODEEM23   (0x1UL << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT   (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER   (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW   (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)
 
#define EMU_DCDCCTRL_DCDCMODEEM4   (0x1UL << 5)
 
#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT   (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)
 
#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER   (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)
 
#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW   (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)
 
#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20)
 
#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24)
 
#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28)
 
#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)
 
#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)
 
#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT   (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12)
 
#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT   (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)
 
#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT   (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24)
 
#define EMU_DCDCLNVCTRL_LNATT   (0x1UL << 1)
 
#define EMU_DCDCLNVCTRL_LNATT_DEFAULT   (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)
 
#define EMU_DCDCLNVCTRL_LNATT_DIV3   (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)
 
#define EMU_DCDCLNVCTRL_LNATT_DIV6   (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)
 
#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT   (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8)
 
#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT   (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)
 
#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT   (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12)
 
#define EMU_DCDCLPCTRL_LPVREFDUTYEN   (0x1UL << 24)
 
#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT   (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT   (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8)
 
#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT   (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12)
 
#define EMU_DCDCLPVCTRL_LPATT   (0x1UL << 0)
 
#define EMU_DCDCLPVCTRL_LPATT_DEFAULT   (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)
 
#define EMU_DCDCLPVCTRL_LPATT_DIV4   (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)
 
#define EMU_DCDCLPVCTRL_LPATT_DIV8   (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)
 
#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT   (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1)
 
#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)
 
#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)
 
#define EMU_DCDCMISCCTRL_LNFORCECCM   (0x1UL << 0)
 
#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT   (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)
 
#define EMU_DCDCMISCCTRL_LNFORCECCMIMM   (0x1UL << 5)
 
#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT   (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5)
 
#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT   (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS   (0x1UL << 1)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSHI   (0x1UL << 2)
 
#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT   (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2)
 
#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT   (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)
 
#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT   (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)
 
#define EMU_DCDCSYNC_DCDCCTRLBUSY   (0x1UL << 0)
 
#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT   (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0)
 
#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT   (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8)
 
#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT   (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)
 
#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK   (0x1UL << 0)
 
#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0)
 
#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK   (0x1UL << 1)
 
#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1)
 
#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK   (0x1UL << 21)
 
#define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21)
 
#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK   (0x1UL << 9)
 
#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9)
 
#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK   (0x1UL << 20)
 
#define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20)
 
#define EMU_EM23PERNORETAINCMD_CSENUNLOCK   (0x1UL << 14)
 
#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14)
 
#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK   (0x1UL << 7)
 
#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7)
 
#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK   (0x1UL << 5)
 
#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5)
 
#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK   (0x1UL << 6)
 
#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6)
 
#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK   (0x1UL << 8)
 
#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8)
 
#define EMU_EM23PERNORETAINCMD_LCDUNLOCK   (0x1UL << 17)
 
#define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17)
 
#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK   (0x1UL << 13)
 
#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13)
 
#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK   (0x1UL << 10)
 
#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10)
 
#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK   (0x1UL << 18)
 
#define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18)
 
#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK   (0x1UL << 15)
 
#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15)
 
#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK   (0x1UL << 16)
 
#define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16)
 
#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK   (0x1UL << 2)
 
#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2)
 
#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK   (0x1UL << 3)
 
#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3)
 
#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK   (0x1UL << 4)
 
#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4)
 
#define EMU_EM23PERNORETAINCMD_RTCUNLOCK   (0x1UL << 23)
 
#define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23)
 
#define EMU_EM23PERNORETAINCMD_USBUNLOCK   (0x1UL << 24)
 
#define EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT << 24)
 
#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK   (0x1UL << 11)
 
#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11)
 
#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK   (0x1UL << 12)
 
#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT   (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12)
 
#define EMU_EM23PERNORETAINCTRL_ACMP0DIS   (0x1UL << 0)
 
#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0)
 
#define EMU_EM23PERNORETAINCTRL_ACMP1DIS   (0x1UL << 1)
 
#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1)
 
#define EMU_EM23PERNORETAINCTRL_ACMP2DIS   (0x1UL << 21)
 
#define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21)
 
#define EMU_EM23PERNORETAINCTRL_ADC0DIS   (0x1UL << 9)
 
#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9)
 
#define EMU_EM23PERNORETAINCTRL_ADC1DIS   (0x1UL << 20)
 
#define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20)
 
#define EMU_EM23PERNORETAINCTRL_CSENDIS   (0x1UL << 14)
 
#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14)
 
#define EMU_EM23PERNORETAINCTRL_I2C0DIS   (0x1UL << 5)
 
#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5)
 
#define EMU_EM23PERNORETAINCTRL_I2C1DIS   (0x1UL << 6)
 
#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6)
 
#define EMU_EM23PERNORETAINCTRL_IDAC0DIS   (0x1UL << 8)
 
#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8)
 
#define EMU_EM23PERNORETAINCTRL_LCDDIS   (0x1UL << 17)
 
#define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17)
 
#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS   (0x1UL << 13)
 
#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13)
 
#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS   (0x1UL << 10)
 
#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10)
 
#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS   (0x1UL << 18)
 
#define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18)
 
#define EMU_EM23PERNORETAINCTRL_LEUART0DIS   (0x1UL << 15)
 
#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15)
 
#define EMU_EM23PERNORETAINCTRL_LEUART1DIS   (0x1UL << 16)
 
#define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16)
 
#define EMU_EM23PERNORETAINCTRL_PCNT0DIS   (0x1UL << 2)
 
#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2)
 
#define EMU_EM23PERNORETAINCTRL_PCNT1DIS   (0x1UL << 3)
 
#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3)
 
#define EMU_EM23PERNORETAINCTRL_PCNT2DIS   (0x1UL << 4)
 
#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4)
 
#define EMU_EM23PERNORETAINCTRL_RTCDIS   (0x1UL << 23)
 
#define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23)
 
#define EMU_EM23PERNORETAINCTRL_USBDIS   (0x1UL << 24)
 
#define EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT << 24)
 
#define EMU_EM23PERNORETAINCTRL_VDAC0DIS   (0x1UL << 7)
 
#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7)
 
#define EMU_EM23PERNORETAINCTRL_WDOG0DIS   (0x1UL << 11)
 
#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11)
 
#define EMU_EM23PERNORETAINCTRL_WDOG1DIS   (0x1UL << 12)
 
#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT   (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED   (0x1UL << 0)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED   (0x1UL << 1)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED   (0x1UL << 21)
 
#define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21)
 
#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED   (0x1UL << 9)
 
#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9)
 
#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED   (0x1UL << 20)
 
#define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20)
 
#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED   (0x1UL << 14)
 
#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14)
 
#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED   (0x1UL << 7)
 
#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7)
 
#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED   (0x1UL << 5)
 
#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5)
 
#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED   (0x1UL << 6)
 
#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6)
 
#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED   (0x1UL << 8)
 
#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8)
 
#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED   (0x1UL << 17)
 
#define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17)
 
#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED   (0x1UL << 13)
 
#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13)
 
#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED   (0x1UL << 10)
 
#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10)
 
#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED   (0x1UL << 18)
 
#define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18)
 
#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED   (0x1UL << 15)
 
#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15)
 
#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED   (0x1UL << 16)
 
#define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED   (0x1UL << 2)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED   (0x1UL << 3)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED   (0x1UL << 4)
 
#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4)
 
#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED   (0x1UL << 23)
 
#define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23)
 
#define EMU_EM23PERNORETAINSTATUS_USBLOCKED   (0x1UL << 24)
 
#define EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT << 24)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED   (0x1UL << 11)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED   (0x1UL << 12)
 
#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT   (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12)
 
#define EMU_EM4CTRL_EM4ENTRY_DEFAULT   (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)
 
#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT   (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)
 
#define EMU_EM4CTRL_EM4IORETMODE_DISABLE   (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)
 
#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT   (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)
 
#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH   (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)
 
#define EMU_EM4CTRL_EM4STATE   (0x1UL << 0)
 
#define EMU_EM4CTRL_EM4STATE_DEFAULT   (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)
 
#define EMU_EM4CTRL_EM4STATE_EM4H   (_EMU_EM4CTRL_EM4STATE_EM4H << 0)
 
#define EMU_EM4CTRL_EM4STATE_EM4S   (_EMU_EM4CTRL_EM4STATE_EM4S << 0)
 
#define EMU_EM4CTRL_RETAINLFRCO   (0x1UL << 1)
 
#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT   (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)
 
#define EMU_EM4CTRL_RETAINLFXO   (0x1UL << 2)
 
#define EMU_EM4CTRL_RETAINLFXO_DEFAULT   (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)
 
#define EMU_EM4CTRL_RETAINULFRCO   (0x1UL << 3)
 
#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT   (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)
 
#define EMU_IEN_BURDY   (0x1UL << 22)
 
#define EMU_IEN_BURDY_DEFAULT   (_EMU_IEN_BURDY_DEFAULT << 22)
 
#define EMU_IEN_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IEN_DCDCINBYPASS_DEFAULT   (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IEN_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IEN_DCDCLNRUNNING_DEFAULT   (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IEN_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IEN_DCDCLPRUNNING_DEFAULT   (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IEN_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IEN_EM23WAKEUP_DEFAULT   (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IEN_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IEN_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IEN_R5VREADY   (0x1UL << 10)
 
#define EMU_IEN_R5VREADY_DEFAULT   (_EMU_IEN_R5VREADY_DEFAULT << 10)
 
#define EMU_IEN_R5VVSINT   (0x1UL << 23)
 
#define EMU_IEN_R5VVSINT_DEFAULT   (_EMU_IEN_R5VVSINT_DEFAULT << 23)
 
#define EMU_IEN_TEMP   (0x1UL << 29)
 
#define EMU_IEN_TEMP_DEFAULT   (_EMU_IEN_TEMP_DEFAULT << 29)
 
#define EMU_IEN_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IEN_TEMPHIGH_DEFAULT   (_EMU_IEN_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IEN_TEMPLOW   (0x1UL << 30)
 
#define EMU_IEN_TEMPLOW_DEFAULT   (_EMU_IEN_TEMPLOW_DEFAULT << 30)
 
#define EMU_IEN_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IEN_VMONALTAVDDFALL_DEFAULT   (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IEN_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IEN_VMONALTAVDDRISE_DEFAULT   (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IEN_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IEN_VMONAVDDFALL_DEFAULT   (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IEN_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IEN_VMONAVDDRISE_DEFAULT   (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IEN_VMONBUVDDFALL   (0x1UL << 12)
 
#define EMU_IEN_VMONBUVDDFALL_DEFAULT   (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12)
 
#define EMU_IEN_VMONBUVDDRISE   (0x1UL << 13)
 
#define EMU_IEN_VMONBUVDDRISE_DEFAULT   (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13)
 
#define EMU_IEN_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IEN_VMONDVDDFALL_DEFAULT   (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IEN_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IEN_VMONDVDDRISE_DEFAULT   (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IEN_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IEN_VMONIO0FALL_DEFAULT   (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IEN_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IEN_VMONIO0RISE_DEFAULT   (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IEN_VMONIO1FALL   (0x1UL << 8)
 
#define EMU_IEN_VMONIO1FALL_DEFAULT   (_EMU_IEN_VMONIO1FALL_DEFAULT << 8)
 
#define EMU_IEN_VMONIO1RISE   (0x1UL << 9)
 
#define EMU_IEN_VMONIO1RISE_DEFAULT   (_EMU_IEN_VMONIO1RISE_DEFAULT << 9)
 
#define EMU_IEN_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IEN_VSCALEDONE_DEFAULT   (_EMU_IEN_VSCALEDONE_DEFAULT << 25)
 
#define EMU_IF_BURDY   (0x1UL << 22)
 
#define EMU_IF_BURDY_DEFAULT   (_EMU_IF_BURDY_DEFAULT << 22)
 
#define EMU_IF_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IF_DCDCINBYPASS_DEFAULT   (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IF_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IF_DCDCLNRUNNING_DEFAULT   (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IF_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IF_DCDCLPRUNNING_DEFAULT   (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IF_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IF_EM23WAKEUP_DEFAULT   (_EMU_IF_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IF_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IF_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IF_R5VREADY   (0x1UL << 10)
 
#define EMU_IF_R5VREADY_DEFAULT   (_EMU_IF_R5VREADY_DEFAULT << 10)
 
#define EMU_IF_R5VVSINT   (0x1UL << 23)
 
#define EMU_IF_R5VVSINT_DEFAULT   (_EMU_IF_R5VVSINT_DEFAULT << 23)
 
#define EMU_IF_TEMP   (0x1UL << 29)
 
#define EMU_IF_TEMP_DEFAULT   (_EMU_IF_TEMP_DEFAULT << 29)
 
#define EMU_IF_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IF_TEMPHIGH_DEFAULT   (_EMU_IF_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IF_TEMPLOW   (0x1UL << 30)
 
#define EMU_IF_TEMPLOW_DEFAULT   (_EMU_IF_TEMPLOW_DEFAULT << 30)
 
#define EMU_IF_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IF_VMONALTAVDDFALL_DEFAULT   (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IF_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IF_VMONALTAVDDRISE_DEFAULT   (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IF_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IF_VMONAVDDFALL_DEFAULT   (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IF_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IF_VMONAVDDRISE_DEFAULT   (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IF_VMONBUVDDFALL   (0x1UL << 12)
 
#define EMU_IF_VMONBUVDDFALL_DEFAULT   (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12)
 
#define EMU_IF_VMONBUVDDRISE   (0x1UL << 13)
 
#define EMU_IF_VMONBUVDDRISE_DEFAULT   (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13)
 
#define EMU_IF_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IF_VMONDVDDFALL_DEFAULT   (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IF_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IF_VMONDVDDRISE_DEFAULT   (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IF_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IF_VMONIO0FALL_DEFAULT   (_EMU_IF_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IF_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IF_VMONIO0RISE_DEFAULT   (_EMU_IF_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IF_VMONIO1FALL   (0x1UL << 8)
 
#define EMU_IF_VMONIO1FALL_DEFAULT   (_EMU_IF_VMONIO1FALL_DEFAULT << 8)
 
#define EMU_IF_VMONIO1RISE   (0x1UL << 9)
 
#define EMU_IF_VMONIO1RISE_DEFAULT   (_EMU_IF_VMONIO1RISE_DEFAULT << 9)
 
#define EMU_IF_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IF_VSCALEDONE_DEFAULT   (_EMU_IF_VSCALEDONE_DEFAULT << 25)
 
#define EMU_IFC_BURDY   (0x1UL << 22)
 
#define EMU_IFC_BURDY_DEFAULT   (_EMU_IFC_BURDY_DEFAULT << 22)
 
#define EMU_IFC_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IFC_DCDCINBYPASS_DEFAULT   (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IFC_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IFC_DCDCLNRUNNING_DEFAULT   (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IFC_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IFC_DCDCLPRUNNING_DEFAULT   (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IFC_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IFC_EM23WAKEUP_DEFAULT   (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IFC_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IFC_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IFC_R5VREADY   (0x1UL << 10)
 
#define EMU_IFC_R5VREADY_DEFAULT   (_EMU_IFC_R5VREADY_DEFAULT << 10)
 
#define EMU_IFC_R5VVSINT   (0x1UL << 23)
 
#define EMU_IFC_R5VVSINT_DEFAULT   (_EMU_IFC_R5VVSINT_DEFAULT << 23)
 
#define EMU_IFC_TEMP   (0x1UL << 29)
 
#define EMU_IFC_TEMP_DEFAULT   (_EMU_IFC_TEMP_DEFAULT << 29)
 
#define EMU_IFC_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IFC_TEMPHIGH_DEFAULT   (_EMU_IFC_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IFC_TEMPLOW   (0x1UL << 30)
 
#define EMU_IFC_TEMPLOW_DEFAULT   (_EMU_IFC_TEMPLOW_DEFAULT << 30)
 
#define EMU_IFC_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IFC_VMONALTAVDDFALL_DEFAULT   (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IFC_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IFC_VMONALTAVDDRISE_DEFAULT   (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IFC_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IFC_VMONAVDDFALL_DEFAULT   (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IFC_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IFC_VMONAVDDRISE_DEFAULT   (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IFC_VMONBUVDDFALL   (0x1UL << 12)
 
#define EMU_IFC_VMONBUVDDFALL_DEFAULT   (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12)
 
#define EMU_IFC_VMONBUVDDRISE   (0x1UL << 13)
 
#define EMU_IFC_VMONBUVDDRISE_DEFAULT   (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13)
 
#define EMU_IFC_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IFC_VMONDVDDFALL_DEFAULT   (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IFC_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IFC_VMONDVDDRISE_DEFAULT   (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IFC_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IFC_VMONIO0FALL_DEFAULT   (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IFC_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IFC_VMONIO0RISE_DEFAULT   (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IFC_VMONIO1FALL   (0x1UL << 8)
 
#define EMU_IFC_VMONIO1FALL_DEFAULT   (_EMU_IFC_VMONIO1FALL_DEFAULT << 8)
 
#define EMU_IFC_VMONIO1RISE   (0x1UL << 9)
 
#define EMU_IFC_VMONIO1RISE_DEFAULT   (_EMU_IFC_VMONIO1RISE_DEFAULT << 9)
 
#define EMU_IFC_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IFC_VSCALEDONE_DEFAULT   (_EMU_IFC_VSCALEDONE_DEFAULT << 25)
 
#define EMU_IFS_BURDY   (0x1UL << 22)
 
#define EMU_IFS_BURDY_DEFAULT   (_EMU_IFS_BURDY_DEFAULT << 22)
 
#define EMU_IFS_DCDCINBYPASS   (0x1UL << 20)
 
#define EMU_IFS_DCDCINBYPASS_DEFAULT   (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)
 
#define EMU_IFS_DCDCLNRUNNING   (0x1UL << 19)
 
#define EMU_IFS_DCDCLNRUNNING_DEFAULT   (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)
 
#define EMU_IFS_DCDCLPRUNNING   (0x1UL << 18)
 
#define EMU_IFS_DCDCLPRUNNING_DEFAULT   (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)
 
#define EMU_IFS_EM23WAKEUP   (0x1UL << 24)
 
#define EMU_IFS_EM23WAKEUP_DEFAULT   (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)
 
#define EMU_IFS_NFETOVERCURRENTLIMIT   (0x1UL << 17)
 
#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17)
 
#define EMU_IFS_PFETOVERCURRENTLIMIT   (0x1UL << 16)
 
#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT   (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16)
 
#define EMU_IFS_R5VREADY   (0x1UL << 10)
 
#define EMU_IFS_R5VREADY_DEFAULT   (_EMU_IFS_R5VREADY_DEFAULT << 10)
 
#define EMU_IFS_R5VVSINT   (0x1UL << 23)
 
#define EMU_IFS_R5VVSINT_DEFAULT   (_EMU_IFS_R5VVSINT_DEFAULT << 23)
 
#define EMU_IFS_TEMP   (0x1UL << 29)
 
#define EMU_IFS_TEMP_DEFAULT   (_EMU_IFS_TEMP_DEFAULT << 29)
 
#define EMU_IFS_TEMPHIGH   (0x1UL << 31)
 
#define EMU_IFS_TEMPHIGH_DEFAULT   (_EMU_IFS_TEMPHIGH_DEFAULT << 31)
 
#define EMU_IFS_TEMPLOW   (0x1UL << 30)
 
#define EMU_IFS_TEMPLOW_DEFAULT   (_EMU_IFS_TEMPLOW_DEFAULT << 30)
 
#define EMU_IFS_VMONALTAVDDFALL   (0x1UL << 2)
 
#define EMU_IFS_VMONALTAVDDFALL_DEFAULT   (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)
 
#define EMU_IFS_VMONALTAVDDRISE   (0x1UL << 3)
 
#define EMU_IFS_VMONALTAVDDRISE_DEFAULT   (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)
 
#define EMU_IFS_VMONAVDDFALL   (0x1UL << 0)
 
#define EMU_IFS_VMONAVDDFALL_DEFAULT   (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0)
 
#define EMU_IFS_VMONAVDDRISE   (0x1UL << 1)
 
#define EMU_IFS_VMONAVDDRISE_DEFAULT   (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1)
 
#define EMU_IFS_VMONBUVDDFALL   (0x1UL << 12)
 
#define EMU_IFS_VMONBUVDDFALL_DEFAULT   (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12)
 
#define EMU_IFS_VMONBUVDDRISE   (0x1UL << 13)
 
#define EMU_IFS_VMONBUVDDRISE_DEFAULT   (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13)
 
#define EMU_IFS_VMONDVDDFALL   (0x1UL << 4)
 
#define EMU_IFS_VMONDVDDFALL_DEFAULT   (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4)
 
#define EMU_IFS_VMONDVDDRISE   (0x1UL << 5)
 
#define EMU_IFS_VMONDVDDRISE_DEFAULT   (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5)
 
#define EMU_IFS_VMONIO0FALL   (0x1UL << 6)
 
#define EMU_IFS_VMONIO0FALL_DEFAULT   (_EMU_IFS_VMONIO0FALL_DEFAULT << 6)
 
#define EMU_IFS_VMONIO0RISE   (0x1UL << 7)
 
#define EMU_IFS_VMONIO0RISE_DEFAULT   (_EMU_IFS_VMONIO0RISE_DEFAULT << 7)
 
#define EMU_IFS_VMONIO1FALL   (0x1UL << 8)
 
#define EMU_IFS_VMONIO1FALL_DEFAULT   (_EMU_IFS_VMONIO1FALL_DEFAULT << 8)
 
#define EMU_IFS_VMONIO1RISE   (0x1UL << 9)
 
#define EMU_IFS_VMONIO1RISE_DEFAULT   (_EMU_IFS_VMONIO1RISE_DEFAULT << 9)
 
#define EMU_IFS_VSCALEDONE   (0x1UL << 25)
 
#define EMU_IFS_VSCALEDONE_DEFAULT   (_EMU_IFS_VSCALEDONE_DEFAULT << 25)
 
#define EMU_LOCK_LOCKKEY_DEFAULT   (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
 
#define EMU_LOCK_LOCKKEY_LOCK   (_EMU_LOCK_LOCKKEY_LOCK << 0)
 
#define EMU_LOCK_LOCKKEY_LOCKED   (_EMU_LOCK_LOCKKEY_LOCKED << 0)
 
#define EMU_LOCK_LOCKKEY_UNLOCK   (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
 
#define EMU_LOCK_LOCKKEY_UNLOCKED   (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
 
#define EMU_PWRCTRL_ANASW   (0x1UL << 5)
 
#define EMU_PWRCTRL_ANASW_AVDD   (_EMU_PWRCTRL_ANASW_AVDD << 5)
 
#define EMU_PWRCTRL_ANASW_DEFAULT   (_EMU_PWRCTRL_ANASW_DEFAULT << 5)
 
#define EMU_PWRCTRL_ANASW_DVDD   (_EMU_PWRCTRL_ANASW_DVDD << 5)
 
#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH   (0x1UL << 13)
 
#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT   (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13)
 
#define EMU_PWRCTRL_REGPWRSEL   (0x1UL << 10)
 
#define EMU_PWRCTRL_REGPWRSEL_AVDD   (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10)
 
#define EMU_PWRCTRL_REGPWRSEL_DEFAULT   (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10)
 
#define EMU_PWRCTRL_REGPWRSEL_DVDD   (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10)
 
#define EMU_PWRLOCK_LOCKKEY_DEFAULT   (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)
 
#define EMU_PWRLOCK_LOCKKEY_LOCK   (_EMU_PWRLOCK_LOCKKEY_LOCK << 0)
 
#define EMU_PWRLOCK_LOCKKEY_LOCKED   (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0)
 
#define EMU_PWRLOCK_LOCKKEY_UNLOCK   (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)
 
#define EMU_PWRLOCK_LOCKKEY_UNLOCKED   (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0)
 
#define EMU_R5VADCCTRL_AMUXSEL_DEFAULT   (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12)
 
#define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10   (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12)
 
#define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON   (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12)
 
#define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10   (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12)
 
#define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON   (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12)
 
#define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6   (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12)
 
#define EMU_R5VADCCTRL_ENAMUX   (0x1UL << 0)
 
#define EMU_R5VADCCTRL_ENAMUX_DEFAULT   (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0)
 
#define EMU_R5VCTRL_BYPASS   (0x1UL << 0)
 
#define EMU_R5VCTRL_BYPASS_DEFAULT   (_EMU_R5VCTRL_BYPASS_DEFAULT << 0)
 
#define EMU_R5VCTRL_EM4WUEN   (0x1UL << 1)
 
#define EMU_R5VCTRL_EM4WUEN_DEFAULT   (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1)
 
#define EMU_R5VCTRL_IMONEN   (0x1UL << 2)
 
#define EMU_R5VCTRL_IMONEN_DEFAULT   (_EMU_R5VCTRL_IMONEN_DEFAULT << 2)
 
#define EMU_R5VCTRL_INPUTMODE_AUTO   (_EMU_R5VCTRL_INPUTMODE_AUTO << 8)
 
#define EMU_R5VCTRL_INPUTMODE_DEFAULT   (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8)
 
#define EMU_R5VCTRL_INPUTMODE_VBUS   (_EMU_R5VCTRL_INPUTMODE_VBUS << 8)
 
#define EMU_R5VCTRL_INPUTMODE_VREGI   (_EMU_R5VCTRL_INPUTMODE_VREGI << 8)
 
#define EMU_R5VDETCTRL_VBUSDETDIS   (0x1UL << 1)
 
#define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT   (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1)
 
#define EMU_R5VDETCTRL_VREGIDETDIS   (0x1UL << 0)
 
#define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT   (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0)
 
#define EMU_R5VDETCTRL_VREGODETDIS   (0x1UL << 2)
 
#define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT   (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2)
 
#define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT   (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0)
 
#define EMU_R5VSTATUS_COLDSTART   (0x1UL << 5)
 
#define EMU_R5VSTATUS_COLDSTART_DEFAULT   (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5)
 
#define EMU_R5VSTATUS_LDODROPOUTDET   (0x1UL << 4)
 
#define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT   (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4)
 
#define EMU_R5VSTATUS_VBUSDET   (0x1UL << 1)
 
#define EMU_R5VSTATUS_VBUSDET_DEFAULT   (_EMU_R5VSTATUS_VBUSDET_DEFAULT << 1)
 
#define EMU_R5VSTATUS_VBUSGTVREGI   (0x1UL << 3)
 
#define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT   (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3)
 
#define EMU_R5VSTATUS_VREGIDET   (0x1UL << 0)
 
#define EMU_R5VSTATUS_VREGIDET_DEFAULT   (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0)
 
#define EMU_R5VSTATUS_VREGODET   (0x1UL << 2)
 
#define EMU_R5VSTATUS_VREGODET_DEFAULT   (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2)
 
#define EMU_R5VSYNC_OUTLEVELBUSY   (0x1UL << 0)
 
#define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT   (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0)
 
#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3   (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3 << 0)
 
#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3   (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3 << 0)
 
#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3   (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3 << 0)
 
#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT   (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0)
 
#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE   (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3   (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3 << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3   (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3 << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3   (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3 << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3   (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3 << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT   (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0)
 
#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE   (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3   (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3   (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3   (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3   (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT   (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0)
 
#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE   (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0)
 
#define EMU_STATUS_BURDY   (0x1UL << 12)
 
#define EMU_STATUS_BURDY_DEFAULT   (_EMU_STATUS_BURDY_DEFAULT << 12)
 
#define EMU_STATUS_EM4IORET   (0x1UL << 20)
 
#define EMU_STATUS_EM4IORET_DEFAULT   (_EMU_STATUS_EM4IORET_DEFAULT << 20)
 
#define EMU_STATUS_EM4IORET_DISABLED   (_EMU_STATUS_EM4IORET_DISABLED << 20)
 
#define EMU_STATUS_EM4IORET_ENABLED   (_EMU_STATUS_EM4IORET_ENABLED << 20)
 
#define EMU_STATUS_TEMPACTIVE   (0x1UL << 26)
 
#define EMU_STATUS_TEMPACTIVE_DEFAULT   (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26)
 
#define EMU_STATUS_VMONALTAVDD   (0x1UL << 2)
 
#define EMU_STATUS_VMONALTAVDD_DEFAULT   (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2)
 
#define EMU_STATUS_VMONAVDD   (0x1UL << 1)
 
#define EMU_STATUS_VMONAVDD_DEFAULT   (_EMU_STATUS_VMONAVDD_DEFAULT << 1)
 
#define EMU_STATUS_VMONBUVDD   (0x1UL << 7)
 
#define EMU_STATUS_VMONBUVDD_DEFAULT   (_EMU_STATUS_VMONBUVDD_DEFAULT << 7)
 
#define EMU_STATUS_VMONDVDD   (0x1UL << 3)
 
#define EMU_STATUS_VMONDVDD_DEFAULT   (_EMU_STATUS_VMONDVDD_DEFAULT << 3)
 
#define EMU_STATUS_VMONIO0   (0x1UL << 4)
 
#define EMU_STATUS_VMONIO0_DEFAULT   (_EMU_STATUS_VMONIO0_DEFAULT << 4)
 
#define EMU_STATUS_VMONIO1   (0x1UL << 5)
 
#define EMU_STATUS_VMONIO1_DEFAULT   (_EMU_STATUS_VMONIO1_DEFAULT << 5)
 
#define EMU_STATUS_VMONRDY   (0x1UL << 0)
 
#define EMU_STATUS_VMONRDY_DEFAULT   (_EMU_STATUS_VMONRDY_DEFAULT << 0)
 
#define EMU_STATUS_VSCALE_DEFAULT   (_EMU_STATUS_VSCALE_DEFAULT << 16)
 
#define EMU_STATUS_VSCALE_RESV   (_EMU_STATUS_VSCALE_RESV << 16)
 
#define EMU_STATUS_VSCALE_VSCALE0   (_EMU_STATUS_VSCALE_VSCALE0 << 16)
 
#define EMU_STATUS_VSCALE_VSCALE2   (_EMU_STATUS_VSCALE_VSCALE2 << 16)
 
#define EMU_STATUS_VSCALEBUSY   (0x1UL << 18)
 
#define EMU_STATUS_VSCALEBUSY_DEFAULT   (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18)
 
#define EMU_TEMP_TEMP_DEFAULT   (_EMU_TEMP_TEMP_DEFAULT << 0)
 
#define EMU_TEMPLIMITS_EM4WUEN   (0x1UL << 16)
 
#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT   (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16)
 
#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT   (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8)
 
#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT   (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)
 
#define EMU_VMONALTAVDDCTRL_EN   (0x1UL << 0)
 
#define EMU_VMONALTAVDDCTRL_EN_DEFAULT   (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)
 
#define EMU_VMONALTAVDDCTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT   (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONALTAVDDCTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT   (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT   (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT   (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)
 
#define EMU_VMONAVDDCTRL_EN   (0x1UL << 0)
 
#define EMU_VMONAVDDCTRL_EN_DEFAULT   (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0)
 
#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT   (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT   (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)
 
#define EMU_VMONAVDDCTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT   (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT   (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20)
 
#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT   (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)
 
#define EMU_VMONAVDDCTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT   (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONBUVDDCTRL_EN   (0x1UL << 0)
 
#define EMU_VMONBUVDDCTRL_EN_DEFAULT   (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0)
 
#define EMU_VMONBUVDDCTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT   (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONBUVDDCTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT   (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT   (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT   (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8)
 
#define EMU_VMONDVDDCTRL_EN   (0x1UL << 0)
 
#define EMU_VMONDVDDCTRL_EN_DEFAULT   (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0)
 
#define EMU_VMONDVDDCTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT   (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONDVDDCTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT   (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT   (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT   (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)
 
#define EMU_VMONIO0CTRL_EN   (0x1UL << 0)
 
#define EMU_VMONIO0CTRL_EN_DEFAULT   (_EMU_VMONIO0CTRL_EN_DEFAULT << 0)
 
#define EMU_VMONIO0CTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONIO0CTRL_FALLWU_DEFAULT   (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONIO0CTRL_RETDIS   (0x1UL << 4)
 
#define EMU_VMONIO0CTRL_RETDIS_DEFAULT   (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)
 
#define EMU_VMONIO0CTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONIO0CTRL_RISEWU_DEFAULT   (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT   (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT   (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)
 
#define EMU_VMONIO1CTRL_EN   (0x1UL << 0)
 
#define EMU_VMONIO1CTRL_EN_DEFAULT   (_EMU_VMONIO1CTRL_EN_DEFAULT << 0)
 
#define EMU_VMONIO1CTRL_FALLWU   (0x1UL << 3)
 
#define EMU_VMONIO1CTRL_FALLWU_DEFAULT   (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3)
 
#define EMU_VMONIO1CTRL_RETDIS   (0x1UL << 4)
 
#define EMU_VMONIO1CTRL_RETDIS_DEFAULT   (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4)
 
#define EMU_VMONIO1CTRL_RISEWU   (0x1UL << 2)
 
#define EMU_VMONIO1CTRL_RISEWU_DEFAULT   (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2)
 
#define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT   (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12)
 
#define EMU_VMONIO1CTRL_THRESFINE_DEFAULT   (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8)
 

Macro Definition Documentation

#define _EMU_BUCTRL_BUACTPWRCON_BUMAIN   0x00000002UL

Mode BUMAIN for EMU_BUCTRL

Definition at line 1398 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUACTPWRCON_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1395 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUACTPWRCON_MAINBU   0x00000001UL

Mode MAINBU for EMU_BUCTRL

Definition at line 1397 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUACTPWRCON_MASK   0x30000UL

Bit mask for EMU_BUACTPWRCON

Definition at line 1394 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUACTPWRCON_NODIODE   0x00000003UL

Mode NODIODE for EMU_BUCTRL

Definition at line 1399 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUACTPWRCON_NONE   0x00000000UL

Mode NONE for EMU_BUCTRL

Definition at line 1396 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUACTPWRCON_SHIFT   16

Shift value for EMU_BUACTPWRCON

Definition at line 1393 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN   0x00000002UL

Mode BUMAIN for EMU_BUCTRL

Definition at line 1410 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1407 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUINACTPWRCON_MAINBU   0x00000001UL

Mode MAINBU for EMU_BUCTRL

Definition at line 1409 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUINACTPWRCON_MASK   0x300000UL

Bit mask for EMU_BUINACTPWRCON

Definition at line 1406 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUINACTPWRCON_NODIODE   0x00000003UL

Mode NODIODE for EMU_BUCTRL

Definition at line 1411 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUINACTPWRCON_NONE   0x00000000UL

Mode NONE for EMU_BUCTRL

Definition at line 1408 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUINACTPWRCON_SHIFT   20

Shift value for EMU_BUINACTPWRCON

Definition at line 1405 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1367 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUVINPROBEEN_MASK   0x4UL

Bit mask for EMU_BUVINPROBEEN

Definition at line 1366 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_BUVINPROBEEN_SHIFT   2

Shift value for EMU_BUVINPROBEEN

Definition at line 1365 of file efm32gg12b_emu.h.

Referenced by EMU_BUInit().

#define _EMU_BUCTRL_DISMAXCOMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1420 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_DISMAXCOMP_MASK   0x80000000UL

Bit mask for EMU_DISMAXCOMP

Definition at line 1419 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_DISMAXCOMP_SHIFT   31

Shift value for EMU_DISMAXCOMP

Definition at line 1418 of file efm32gg12b_emu.h.

Referenced by EMU_BUInit().

#define _EMU_BUCTRL_EN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1357 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_EN_MASK   0x1UL

Bit mask for EMU_EN

Definition at line 1356 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_EN_SHIFT   0

Shift value for EMU_EN

Definition at line 1355 of file efm32gg12b_emu.h.

Referenced by EMU_BUInit().

#define _EMU_BUCTRL_MASK   0x80333307UL

Mask for EMU_BUCTRL

Definition at line 1353 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_PWRRES_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1383 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_PWRRES_MASK   0x3000UL

Bit mask for EMU_PWRRES

Definition at line 1382 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_PWRRES_RES0   0x00000000UL

Mode RES0 for EMU_BUCTRL

Definition at line 1384 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_PWRRES_RES1   0x00000001UL

Mode RES1 for EMU_BUCTRL

Definition at line 1385 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_PWRRES_RES2   0x00000002UL

Mode RES2 for EMU_BUCTRL

Definition at line 1386 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_PWRRES_RES3   0x00000003UL

Mode RES3 for EMU_BUCTRL

Definition at line 1387 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_PWRRES_SHIFT   12

Shift value for EMU_PWRRES

Definition at line 1381 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_RESETVALUE   0x00000000UL

Default value for EMU_BUCTRL

Definition at line 1352 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_STATEN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1362 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_STATEN_MASK   0x2UL

Bit mask for EMU_STATEN

Definition at line 1361 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_STATEN_SHIFT   1

Shift value for EMU_STATEN

Definition at line 1360 of file efm32gg12b_emu.h.

Referenced by EMU_BUInit().

#define _EMU_BUCTRL_VOUTRES_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_BUCTRL

Definition at line 1371 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_VOUTRES_DIS   0x00000000UL

Mode DIS for EMU_BUCTRL

Definition at line 1372 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_VOUTRES_MASK   0x300UL

Bit mask for EMU_VOUTRES

Definition at line 1370 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_VOUTRES_MED   0x00000002UL

Mode MED for EMU_BUCTRL

Definition at line 1374 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_VOUTRES_SHIFT   8

Shift value for EMU_VOUTRES

Definition at line 1369 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_VOUTRES_STRONG   0x00000003UL

Mode STRONG for EMU_BUCTRL

Definition at line 1375 of file efm32gg12b_emu.h.

#define _EMU_BUCTRL_VOUTRES_WEAK   0x00000001UL

Mode WEAK for EMU_BUCTRL

Definition at line 1373 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM01VSCALE0_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 286 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM01VSCALE0_MASK   0x10UL

Bit mask for EMU_EM01VSCALE0

Definition at line 285 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM01VSCALE0_SHIFT   4

Shift value for EMU_EM01VSCALE0

Definition at line 284 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM01VSCALE2_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 291 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM01VSCALE2_MASK   0x40UL

Bit mask for EMU_EM01VSCALE2

Definition at line 290 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM01VSCALE2_SHIFT   6

Shift value for EMU_EM01VSCALE2

Definition at line 289 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM4UNLATCH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 281 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM4UNLATCH_MASK   0x1UL

Bit mask for EMU_EM4UNLATCH

Definition at line 280 of file efm32gg12b_emu.h.

#define _EMU_CMD_EM4UNLATCH_SHIFT   0

Shift value for EMU_EM4UNLATCH

Definition at line 279 of file efm32gg12b_emu.h.

#define _EMU_CMD_MASK   0x00000051UL

Mask for EMU_CMD

Definition at line 277 of file efm32gg12b_emu.h.

#define _EMU_CMD_RESETVALUE   0x00000000UL

Default value for EMU_CMD

Definition at line 276 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM01LD_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 142 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM01LD_MASK   0x8UL

Bit mask for EMU_EM01LD

Definition at line 141 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM01LD_SHIFT   3

Shift value for EMU_EM01LD

Definition at line 140 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM23VSCALE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 151 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM23VSCALE_MASK   0x300UL

Bit mask for EMU_EM23VSCALE

Definition at line 150 of file efm32gg12b_emu.h.

Referenced by CMU_HFXOAutostartEnable(), and EMU_EM23Init().

#define _EMU_CTRL_EM23VSCALE_RESV   0x00000003UL

Mode RESV for EMU_CTRL

Definition at line 154 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM23VSCALE_SHIFT   8

Shift value for EMU_EM23VSCALE

Definition at line 149 of file efm32gg12b_emu.h.

Referenced by EMU_EM23Init().

#define _EMU_CTRL_EM23VSCALE_VSCALE0   0x00000002UL

Mode VSCALE0 for EMU_CTRL

Definition at line 153 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM23VSCALE_VSCALE2   0x00000000UL

Mode VSCALE2 for EMU_CTRL

Definition at line 152 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 147 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK   0x10UL

Bit mask for EMU_EM23VSCALEAUTOWSEN

Definition at line 146 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT   4

Shift value for EMU_EM23VSCALEAUTOWSEN

Definition at line 145 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM2BLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 132 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM2BLOCK_MASK   0x2UL

Bit mask for EMU_EM2BLOCK

Definition at line 131 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM2BLOCK_SHIFT   1

Shift value for EMU_EM2BLOCK

Definition at line 130 of file efm32gg12b_emu.h.

Referenced by EMU_EM2Block(), and EMU_EM2UnBlock().

#define _EMU_CTRL_EM2BODDIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 137 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM2BODDIS_MASK   0x4UL

Bit mask for EMU_EM2BODDIS

Definition at line 136 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM2BODDIS_SHIFT   2

Shift value for EMU_EM2BODDIS

Definition at line 135 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM4HVSCALE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 161 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM4HVSCALE_MASK   0x30000UL

Bit mask for EMU_EM4HVSCALE

Definition at line 160 of file efm32gg12b_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_CTRL_EM4HVSCALE_RESV   0x00000003UL

Mode RESV for EMU_CTRL

Definition at line 164 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM4HVSCALE_SHIFT   16

Shift value for EMU_EM4HVSCALE

Definition at line 159 of file efm32gg12b_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_CTRL_EM4HVSCALE_VSCALE0   0x00000002UL

Mode VSCALE0 for EMU_CTRL

Definition at line 163 of file efm32gg12b_emu.h.

#define _EMU_CTRL_EM4HVSCALE_VSCALE2   0x00000000UL

Mode VSCALE2 for EMU_CTRL

Definition at line 162 of file efm32gg12b_emu.h.

#define _EMU_CTRL_MASK   0x0003031EUL

Mask for EMU_CTRL

Definition at line 128 of file efm32gg12b_emu.h.

#define _EMU_CTRL_RESETVALUE   0x00000000UL

Default value for EMU_CTRL

Definition at line 127 of file efm32gg12b_emu.h.

#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCCLIMCTRL

Definition at line 1032 of file efm32gg12b_emu.h.

#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK   0x2000UL

Bit mask for EMU_BYPLIMEN

Definition at line 1031 of file efm32gg12b_emu.h.

#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT   13

Shift value for EMU_BYPLIMEN

Definition at line 1030 of file efm32gg12b_emu.h.

Referenced by CHIP_Init().

#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCCLIMCTRL

Definition at line 1027 of file efm32gg12b_emu.h.

#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK   0x300UL

Bit mask for EMU_CLIMBLANKDLY

Definition at line 1026 of file efm32gg12b_emu.h.

#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT   8

Shift value for EMU_CLIMBLANKDLY

Definition at line 1025 of file efm32gg12b_emu.h.

#define _EMU_DCDCCLIMCTRL_MASK   0x00002300UL

Mask for EMU_DCDCCLIMCTRL

Definition at line 1024 of file efm32gg12b_emu.h.

#define _EMU_DCDCCLIMCTRL_RESETVALUE   0x00000100UL

Default value for EMU_DCDCCLIMCTRL

Definition at line 1023 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_BYPASS   0x00000000UL

Mode BYPASS for EMU_DCDCCTRL

Definition at line 925 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT   0x00000003UL

Mode DEFAULT for EMU_DCDCCTRL

Definition at line 928 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE   0x00000001UL

Mode LOWNOISE for EMU_DCDCCTRL

Definition at line 926 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER   0x00000002UL

Mode LOWPOWER for EMU_DCDCCTRL

Definition at line 927 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_MASK   0x3UL

Bit mask for EMU_DCDCMODE

Definition at line 924 of file efm32gg12b_emu.h.

Referenced by EMU_EnterEM4().

#define _EMU_DCDCCTRL_DCDCMODE_OFF   0x00000003UL

Mode OFF for EMU_DCDCCTRL

Definition at line 929 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODE_SHIFT   0

Shift value for EMU_DCDCMODE

Definition at line 923 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCCTRL

Definition at line 939 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER   0x00000001UL

Mode EM23LOWPOWER for EMU_DCDCCTRL

Definition at line 940 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW   0x00000000UL

Mode EM23SW for EMU_DCDCCTRL

Definition at line 938 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK   0x10UL

Bit mask for EMU_DCDCMODEEM23

Definition at line 937 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT   4

Shift value for EMU_DCDCMODEEM23

Definition at line 936 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCCTRL

Definition at line 948 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER   0x00000001UL

Mode EM4LOWPOWER for EMU_DCDCCTRL

Definition at line 949 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW   0x00000000UL

Mode EM4SW for EMU_DCDCCTRL

Definition at line 947 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK   0x20UL

Bit mask for EMU_DCDCMODEEM4

Definition at line 946 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT   5

Shift value for EMU_DCDCMODEEM4

Definition at line 945 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_MASK   0x00000033UL

Mask for EMU_DCDCCTRL

Definition at line 922 of file efm32gg12b_emu.h.

#define _EMU_DCDCCTRL_RESETVALUE   0x00000033UL

Default value for EMU_DCDCCTRL

Definition at line 921 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT   0x00000002UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 1052 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK   0x300000UL

Bit mask for EMU_COMPENC1

Definition at line 1051 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT   20

Shift value for EMU_COMPENC1

Definition at line 1050 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 1056 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK   0x7000000UL

Bit mask for EMU_COMPENC2

Definition at line 1055 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT   24

Shift value for EMU_COMPENC2

Definition at line 1054 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT   0x00000005UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 1060 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK   0xF0000000UL

Bit mask for EMU_COMPENC3

Definition at line 1059 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT   28

Shift value for EMU_COMPENC3

Definition at line 1058 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 1040 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK   0x7UL

Bit mask for EMU_COMPENR1

Definition at line 1039 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT   0

Shift value for EMU_COMPENR1

Definition at line 1038 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 1044 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK   0x1F0UL

Bit mask for EMU_COMPENR2

Definition at line 1043 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT   4

Shift value for EMU_COMPENR2

Definition at line 1042 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT   0x00000004UL

Mode DEFAULT for EMU_DCDCLNCOMPCTRL

Definition at line 1048 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK   0xF000UL

Bit mask for EMU_COMPENR3

Definition at line 1047 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT   12

Shift value for EMU_COMPENR3

Definition at line 1046 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_MASK   0xF730F1F7UL

Mask for EMU_DCDCLNCOMPCTRL

Definition at line 1037 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNCOMPCTRL_RESETVALUE   0x57204077UL

Default value for EMU_DCDCLNCOMPCTRL

Definition at line 1036 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_MASK   0x1F000007UL

Mask for EMU_DCDCLNFREQCTRL

Definition at line 1116 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLNFREQCTRL

Definition at line 1119 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK   0x7UL

Bit mask for EMU_RCOBAND

Definition at line 1118 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT   0

Shift value for EMU_RCOBAND

Definition at line 1117 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT   0x00000010UL

Mode DEFAULT for EMU_DCDCLNFREQCTRL

Definition at line 1123 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK   0x1F000000UL

Bit mask for EMU_RCOTRIM

Definition at line 1122 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT   24

Shift value for EMU_RCOTRIM

Definition at line 1121 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNFREQCTRL_RESETVALUE   0x10000000UL

Default value for EMU_DCDCLNFREQCTRL

Definition at line 1115 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLNVCTRL

Definition at line 1069 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_DIV3   0x00000000UL

Mode DIV3 for EMU_DCDCLNVCTRL

Definition at line 1070 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_DIV6   0x00000001UL

Mode DIV6 for EMU_DCDCLNVCTRL

Definition at line 1071 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_MASK   0x2UL

Bit mask for EMU_LNATT

Definition at line 1068 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNATT_SHIFT   1

Shift value for EMU_LNATT

Definition at line 1067 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT   0x00000071UL

Mode DEFAULT for EMU_DCDCLNVCTRL

Definition at line 1077 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNVREF_MASK   0x7F00UL

Bit mask for EMU_LNVREF

Definition at line 1076 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT   8

Shift value for EMU_LNVREF

Definition at line 1075 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_MASK   0x00007F02UL

Mask for EMU_DCDCLNVCTRL

Definition at line 1065 of file efm32gg12b_emu.h.

#define _EMU_DCDCLNVCTRL_RESETVALUE   0x00007100UL

Default value for EMU_DCDCLNVCTRL

Definition at line 1064 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 1111 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPBLANK_MASK   0x6000000UL

Bit mask for EMU_LPBLANK

Definition at line 1110 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT   25

Shift value for EMU_LPBLANK

Definition at line 1109 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 1102 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK   0xF000UL

Bit mask for EMU_LPCMPHYSSELEM234H

Definition at line 1101 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT   12

Shift value for EMU_LPCMPHYSSELEM234H

Definition at line 1100 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCLPCTRL

Definition at line 1107 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK   0x1000000UL

Bit mask for EMU_LPVREFDUTYEN

Definition at line 1106 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT   24

Shift value for EMU_LPVREFDUTYEN

Definition at line 1105 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_MASK   0x0700F000UL

Mask for EMU_DCDCLPCTRL

Definition at line 1099 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPCTRL_RESETVALUE   0x03000000UL

Default value for EMU_DCDCLPCTRL

Definition at line 1098 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0   0x00000000UL

Mode BIAS0 for EMU_DCDCLPEM01CFG

Definition at line 1507 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1   0x00000001UL

Mode BIAS1 for EMU_DCDCLPEM01CFG

Definition at line 1508 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2   0x00000002UL

Mode BIAS2 for EMU_DCDCLPEM01CFG

Definition at line 1509 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3   0x00000003UL

Mode BIAS3 for EMU_DCDCLPEM01CFG

Definition at line 1511 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT   0x00000003UL

Mode DEFAULT for EMU_DCDCLPEM01CFG

Definition at line 1510 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK   0x300UL

Bit mask for EMU_LPCMPBIASEM01

Definition at line 1506 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT   8

Shift value for EMU_LPCMPBIASEM01

Definition at line 1505 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLPEM01CFG

Definition at line 1519 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK   0xF000UL

Bit mask for EMU_LPCMPHYSSELEM01

Definition at line 1518 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT   12

Shift value for EMU_LPCMPHYSSELEM01

Definition at line 1517 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_MASK   0x0000F300UL

Mask for EMU_DCDCLPEM01CFG

Definition at line 1504 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPEM01CFG_RESETVALUE   0x00000300UL

Default value for EMU_DCDCLPEM01CFG

Definition at line 1503 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCLPVCTRL

Definition at line 1086 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_DIV4   0x00000000UL

Mode DIV4 for EMU_DCDCLPVCTRL

Definition at line 1087 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_DIV8   0x00000001UL

Mode DIV8 for EMU_DCDCLPVCTRL

Definition at line 1088 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_MASK   0x1UL

Bit mask for EMU_LPATT

Definition at line 1085 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPATT_SHIFT   0

Shift value for EMU_LPATT

Definition at line 1084 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT   0x000000B4UL

Mode DEFAULT for EMU_DCDCLPVCTRL

Definition at line 1094 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPVREF_MASK   0x1FEUL

Bit mask for EMU_LPVREF

Definition at line 1093 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT   1

Shift value for EMU_LPVREF

Definition at line 1092 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_MASK   0x000001FFUL

Mask for EMU_DCDCLPVCTRL

Definition at line 1082 of file efm32gg12b_emu.h.

#define _EMU_DCDCLPVCTRL_RESETVALUE   0x00000168UL

Default value for EMU_DCDCLPVCTRL

Definition at line 1081 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 987 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK   0xF0000UL

Bit mask for EMU_BYPLIMSEL

Definition at line 986 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT   16

Shift value for EMU_BYPLIMSEL

Definition at line 985 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT   0x00000003UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 995 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK   0x7000000UL

Bit mask for EMU_LNCLIMILIMSEL

Definition at line 994 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT   24

Shift value for EMU_LNCLIMILIMSEL

Definition at line 993 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 960 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK   0x1UL

Bit mask for EMU_LNFORCECCM

Definition at line 959 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT   0

Shift value for EMU_LNFORCECCM

Definition at line 958 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 975 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK   0x20UL

Bit mask for EMU_LNFORCECCMIMM

Definition at line 974 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT   5

Shift value for EMU_LNFORCECCMIMM

Definition at line 973 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 991 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK   0x700000UL

Bit mask for EMU_LPCLIMILIMSEL

Definition at line 990 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT   20

Shift value for EMU_LPCLIMILIMSEL

Definition at line 989 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0   0x00000000UL

Mode BIAS0 for EMU_DCDCMISCCTRL

Definition at line 1000 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1   0x00000001UL

Mode BIAS1 for EMU_DCDCMISCCTRL

Definition at line 1001 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2   0x00000002UL

Mode BIAS2 for EMU_DCDCMISCCTRL

Definition at line 1002 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3   0x00000003UL

Mode BIAS3 for EMU_DCDCMISCCTRL

Definition at line 1003 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 999 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK   0x30000000UL

Bit mask for EMU_LPCMPBIASEM234H

Definition at line 998 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT   28

Shift value for EMU_LPCMPBIASEM234H

Definition at line 997 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 965 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK   0x2UL

Bit mask for EMU_LPCMPHYSDIS

Definition at line 964 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT   1

Shift value for EMU_LPCMPHYSDIS

Definition at line 963 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 970 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK   0x4UL

Bit mask for EMU_LPCMPHYSHI

Definition at line 969 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT   2

Shift value for EMU_LPCMPHYSHI

Definition at line 968 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_MASK   0x377FFF27UL

Mask for EMU_DCDCMISCCTRL

Definition at line 956 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 983 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_NFETCNT_MASK   0xF000UL

Bit mask for EMU_NFETCNT

Definition at line 982 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT   12

Shift value for EMU_NFETCNT

Definition at line 981 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT   0x00000007UL

Mode DEFAULT for EMU_DCDCMISCCTRL

Definition at line 979 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_PFETCNT_MASK   0xF00UL

Bit mask for EMU_PFETCNT

Definition at line 978 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT   8

Shift value for EMU_PFETCNT

Definition at line 977 of file efm32gg12b_emu.h.

#define _EMU_DCDCMISCCTRL_RESETVALUE   0x03107706UL

Default value for EMU_DCDCMISCCTRL

Definition at line 955 of file efm32gg12b_emu.h.

#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_DCDCSYNC

Definition at line 1132 of file efm32gg12b_emu.h.

#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK   0x1UL

Bit mask for EMU_DCDCCTRLBUSY

Definition at line 1131 of file efm32gg12b_emu.h.

#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT   0

Shift value for EMU_DCDCCTRLBUSY

Definition at line 1130 of file efm32gg12b_emu.h.

#define _EMU_DCDCSYNC_MASK   0x00000001UL

Mask for EMU_DCDCSYNC

Definition at line 1128 of file efm32gg12b_emu.h.

#define _EMU_DCDCSYNC_RESETVALUE   0x00000000UL

Default value for EMU_DCDCSYNC

Definition at line 1127 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_MASK   0x00000370UL

Mask for EMU_DCDCZDETCTRL

Definition at line 1012 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_RESETVALUE   0x00000150UL

Default value for EMU_DCDCZDETCTRL

Definition at line 1011 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT   0x00000001UL

Mode DEFAULT for EMU_DCDCZDETCTRL

Definition at line 1019 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK   0x300UL

Bit mask for EMU_ZDETBLANKDLY

Definition at line 1018 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT   8

Shift value for EMU_ZDETBLANKDLY

Definition at line 1017 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT   0x00000005UL

Mode DEFAULT for EMU_DCDCZDETCTRL

Definition at line 1015 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK   0x70UL

Bit mask for EMU_ZDETILIMSEL

Definition at line 1014 of file efm32gg12b_emu.h.

#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT   4

Shift value for EMU_ZDETILIMSEL

Definition at line 1013 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1571 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK   0x1UL

Bit mask for EMU_ACMP0UNLOCK

Definition at line 1570 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT   0

Shift value for EMU_ACMP0UNLOCK

Definition at line 1569 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1576 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK   0x2UL

Bit mask for EMU_ACMP1UNLOCK

Definition at line 1575 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT   1

Shift value for EMU_ACMP1UNLOCK

Definition at line 1574 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1671 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK   0x200000UL

Bit mask for EMU_ACMP2UNLOCK

Definition at line 1670 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT   21

Shift value for EMU_ACMP2UNLOCK

Definition at line 1669 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1616 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK   0x200UL

Bit mask for EMU_ADC0UNLOCK

Definition at line 1615 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT   9

Shift value for EMU_ADC0UNLOCK

Definition at line 1614 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1666 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK   0x100000UL

Bit mask for EMU_ADC1UNLOCK

Definition at line 1665 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT   20

Shift value for EMU_ADC1UNLOCK

Definition at line 1664 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1641 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK   0x4000UL

Bit mask for EMU_CSENUNLOCK

Definition at line 1640 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT   14

Shift value for EMU_CSENUNLOCK

Definition at line 1639 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1606 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK   0x80UL

Bit mask for EMU_DAC0UNLOCK

Definition at line 1605 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT   7

Shift value for EMU_DAC0UNLOCK

Definition at line 1604 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1596 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK   0x20UL

Bit mask for EMU_I2C0UNLOCK

Definition at line 1595 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT   5

Shift value for EMU_I2C0UNLOCK

Definition at line 1594 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1601 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK   0x40UL

Bit mask for EMU_I2C1UNLOCK

Definition at line 1600 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT   6

Shift value for EMU_I2C1UNLOCK

Definition at line 1599 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1611 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK   0x100UL

Bit mask for EMU_IDAC0UNLOCK

Definition at line 1610 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT   8

Shift value for EMU_IDAC0UNLOCK

Definition at line 1609 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1656 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK   0x20000UL

Bit mask for EMU_LCDUNLOCK

Definition at line 1655 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT   17

Shift value for EMU_LCDUNLOCK

Definition at line 1654 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1636 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK   0x2000UL

Bit mask for EMU_LESENSE0UNLOCK

Definition at line 1635 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT   13

Shift value for EMU_LESENSE0UNLOCK

Definition at line 1634 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1621 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK   0x400UL

Bit mask for EMU_LETIMER0UNLOCK

Definition at line 1620 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT   10

Shift value for EMU_LETIMER0UNLOCK

Definition at line 1619 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1661 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK   0x40000UL

Bit mask for EMU_LETIMER1UNLOCK

Definition at line 1660 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT   18

Shift value for EMU_LETIMER1UNLOCK

Definition at line 1659 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1646 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK   0x8000UL

Bit mask for EMU_LEUART0UNLOCK

Definition at line 1645 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT   15

Shift value for EMU_LEUART0UNLOCK

Definition at line 1644 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1651 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK   0x10000UL

Bit mask for EMU_LEUART1UNLOCK

Definition at line 1650 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT   16

Shift value for EMU_LEUART1UNLOCK

Definition at line 1649 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_MASK   0x01B7FFFFUL

Mask for EMU_EM23PERNORETAINCMD

Definition at line 1567 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1581 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK   0x4UL

Bit mask for EMU_PCNT0UNLOCK

Definition at line 1580 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT   2

Shift value for EMU_PCNT0UNLOCK

Definition at line 1579 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1586 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK   0x8UL

Bit mask for EMU_PCNT1UNLOCK

Definition at line 1585 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT   3

Shift value for EMU_PCNT1UNLOCK

Definition at line 1584 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1591 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK   0x10UL

Bit mask for EMU_PCNT2UNLOCK

Definition at line 1590 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT   4

Shift value for EMU_PCNT2UNLOCK

Definition at line 1589 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_RESETVALUE   0x00000000UL

Default value for EMU_EM23PERNORETAINCMD

Definition at line 1566 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1676 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK   0x800000UL

Bit mask for EMU_RTCUNLOCK

Definition at line 1675 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT   23

Shift value for EMU_RTCUNLOCK

Definition at line 1674 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1681 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_MASK   0x1000000UL

Bit mask for EMU_USBUNLOCK

Definition at line 1680 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_USBUNLOCK_SHIFT   24

Shift value for EMU_USBUNLOCK

Definition at line 1679 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1626 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK   0x800UL

Bit mask for EMU_WDOG0UNLOCK

Definition at line 1625 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT   11

Shift value for EMU_WDOG0UNLOCK

Definition at line 1624 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCMD

Definition at line 1631 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK   0x1000UL

Bit mask for EMU_WDOG1UNLOCK

Definition at line 1630 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT   12

Shift value for EMU_WDOG1UNLOCK

Definition at line 1629 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1809 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK   0x1UL

Bit mask for EMU_ACMP0DIS

Definition at line 1808 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT   0

Shift value for EMU_ACMP0DIS

Definition at line 1807 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1814 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK   0x2UL

Bit mask for EMU_ACMP1DIS

Definition at line 1813 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT   1

Shift value for EMU_ACMP1DIS

Definition at line 1812 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1909 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK   0x200000UL

Bit mask for EMU_ACMP2DIS

Definition at line 1908 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT   21

Shift value for EMU_ACMP2DIS

Definition at line 1907 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1854 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK   0x200UL

Bit mask for EMU_ADC0DIS

Definition at line 1853 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT   9

Shift value for EMU_ADC0DIS

Definition at line 1852 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1904 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK   0x100000UL

Bit mask for EMU_ADC1DIS

Definition at line 1903 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT   20

Shift value for EMU_ADC1DIS

Definition at line 1902 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1879 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK   0x4000UL

Bit mask for EMU_CSENDIS

Definition at line 1878 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT   14

Shift value for EMU_CSENDIS

Definition at line 1877 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1834 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK   0x20UL

Bit mask for EMU_I2C0DIS

Definition at line 1833 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT   5

Shift value for EMU_I2C0DIS

Definition at line 1832 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1839 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK   0x40UL

Bit mask for EMU_I2C1DIS

Definition at line 1838 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT   6

Shift value for EMU_I2C1DIS

Definition at line 1837 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1849 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK   0x100UL

Bit mask for EMU_IDAC0DIS

Definition at line 1848 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT   8

Shift value for EMU_IDAC0DIS

Definition at line 1847 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1894 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK   0x20000UL

Bit mask for EMU_LCDDIS

Definition at line 1893 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT   17

Shift value for EMU_LCDDIS

Definition at line 1892 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1874 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK   0x2000UL

Bit mask for EMU_LESENSE0DIS

Definition at line 1873 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT   13

Shift value for EMU_LESENSE0DIS

Definition at line 1872 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1859 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK   0x400UL

Bit mask for EMU_LETIMER0DIS

Definition at line 1858 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT   10

Shift value for EMU_LETIMER0DIS

Definition at line 1857 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1899 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK   0x40000UL

Bit mask for EMU_LETIMER1DIS

Definition at line 1898 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT   18

Shift value for EMU_LETIMER1DIS

Definition at line 1897 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1884 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK   0x8000UL

Bit mask for EMU_LEUART0DIS

Definition at line 1883 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT   15

Shift value for EMU_LEUART0DIS

Definition at line 1882 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1889 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK   0x10000UL

Bit mask for EMU_LEUART1DIS

Definition at line 1888 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT   16

Shift value for EMU_LEUART1DIS

Definition at line 1887 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_MASK   0x01B7FFFFUL

Mask for EMU_EM23PERNORETAINCTRL

Definition at line 1805 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1819 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK   0x4UL

Bit mask for EMU_PCNT0DIS

Definition at line 1818 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT   2

Shift value for EMU_PCNT0DIS

Definition at line 1817 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1824 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK   0x8UL

Bit mask for EMU_PCNT1DIS

Definition at line 1823 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT   3

Shift value for EMU_PCNT1DIS

Definition at line 1822 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1829 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK   0x10UL

Bit mask for EMU_PCNT2DIS

Definition at line 1828 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT   4

Shift value for EMU_PCNT2DIS

Definition at line 1827 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_RESETVALUE   0x00000000UL

Default value for EMU_EM23PERNORETAINCTRL

Definition at line 1804 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1914 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK   0x800000UL

Bit mask for EMU_RTCDIS

Definition at line 1913 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT   23

Shift value for EMU_RTCDIS

Definition at line 1912 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1919 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_USBDIS_MASK   0x1000000UL

Bit mask for EMU_USBDIS

Definition at line 1918 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_USBDIS_SHIFT   24

Shift value for EMU_USBDIS

Definition at line 1917 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1844 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK   0x80UL

Bit mask for EMU_VDAC0DIS

Definition at line 1843 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT   7

Shift value for EMU_VDAC0DIS

Definition at line 1842 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1864 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK   0x800UL

Bit mask for EMU_WDOG0DIS

Definition at line 1863 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT   11

Shift value for EMU_WDOG0DIS

Definition at line 1862 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINCTRL

Definition at line 1869 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK   0x1000UL

Bit mask for EMU_WDOG1DIS

Definition at line 1868 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT   12

Shift value for EMU_WDOG1DIS

Definition at line 1867 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1690 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK   0x1UL

Bit mask for EMU_ACMP0LOCKED

Definition at line 1689 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT   0

Shift value for EMU_ACMP0LOCKED

Definition at line 1688 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1695 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK   0x2UL

Bit mask for EMU_ACMP1LOCKED

Definition at line 1694 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT   1

Shift value for EMU_ACMP1LOCKED

Definition at line 1693 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1790 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK   0x200000UL

Bit mask for EMU_ACMP2LOCKED

Definition at line 1789 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT   21

Shift value for EMU_ACMP2LOCKED

Definition at line 1788 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1735 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK   0x200UL

Bit mask for EMU_ADC0LOCKED

Definition at line 1734 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT   9

Shift value for EMU_ADC0LOCKED

Definition at line 1733 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1785 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK   0x100000UL

Bit mask for EMU_ADC1LOCKED

Definition at line 1784 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT   20

Shift value for EMU_ADC1LOCKED

Definition at line 1783 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1760 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK   0x4000UL

Bit mask for EMU_CSENLOCKED

Definition at line 1759 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT   14

Shift value for EMU_CSENLOCKED

Definition at line 1758 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1725 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK   0x80UL

Bit mask for EMU_DAC0LOCKED

Definition at line 1724 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT   7

Shift value for EMU_DAC0LOCKED

Definition at line 1723 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1715 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK   0x20UL

Bit mask for EMU_I2C0LOCKED

Definition at line 1714 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT   5

Shift value for EMU_I2C0LOCKED

Definition at line 1713 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1720 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK   0x40UL

Bit mask for EMU_I2C1LOCKED

Definition at line 1719 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT   6

Shift value for EMU_I2C1LOCKED

Definition at line 1718 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1730 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK   0x100UL

Bit mask for EMU_IDAC0LOCKED

Definition at line 1729 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT   8

Shift value for EMU_IDAC0LOCKED

Definition at line 1728 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1775 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK   0x20000UL

Bit mask for EMU_LCDLOCKED

Definition at line 1774 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT   17

Shift value for EMU_LCDLOCKED

Definition at line 1773 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1755 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK   0x2000UL

Bit mask for EMU_LESENSE0LOCKED

Definition at line 1754 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT   13

Shift value for EMU_LESENSE0LOCKED

Definition at line 1753 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1740 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK   0x400UL

Bit mask for EMU_LETIMER0LOCKED

Definition at line 1739 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT   10

Shift value for EMU_LETIMER0LOCKED

Definition at line 1738 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1780 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK   0x40000UL

Bit mask for EMU_LETIMER1LOCKED

Definition at line 1779 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT   18

Shift value for EMU_LETIMER1LOCKED

Definition at line 1778 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1765 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK   0x8000UL

Bit mask for EMU_LEUART0LOCKED

Definition at line 1764 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT   15

Shift value for EMU_LEUART0LOCKED

Definition at line 1763 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1770 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK   0x10000UL

Bit mask for EMU_LEUART1LOCKED

Definition at line 1769 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT   16

Shift value for EMU_LEUART1LOCKED

Definition at line 1768 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_MASK   0x01B7FFFFUL

Mask for EMU_EM23PERNORETAINSTATUS

Definition at line 1686 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1700 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK   0x4UL

Bit mask for EMU_PCNT0LOCKED

Definition at line 1699 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT   2

Shift value for EMU_PCNT0LOCKED

Definition at line 1698 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1705 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK   0x8UL

Bit mask for EMU_PCNT1LOCKED

Definition at line 1704 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT   3

Shift value for EMU_PCNT1LOCKED

Definition at line 1703 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1710 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK   0x10UL

Bit mask for EMU_PCNT2LOCKED

Definition at line 1709 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT   4

Shift value for EMU_PCNT2LOCKED

Definition at line 1708 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE   0x00000000UL

Default value for EMU_EM23PERNORETAINSTATUS

Definition at line 1685 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1795 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK   0x800000UL

Bit mask for EMU_RTCLOCKED

Definition at line 1794 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT   23

Shift value for EMU_RTCLOCKED

Definition at line 1793 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1800 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_MASK   0x1000000UL

Bit mask for EMU_USBLOCKED

Definition at line 1799 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_SHIFT   24

Shift value for EMU_USBLOCKED

Definition at line 1798 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1745 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK   0x800UL

Bit mask for EMU_WDOG0LOCKED

Definition at line 1744 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT   11

Shift value for EMU_WDOG0LOCKED

Definition at line 1743 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM23PERNORETAINSTATUS

Definition at line 1750 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK   0x1000UL

Bit mask for EMU_WDOG1LOCKED

Definition at line 1749 of file efm32gg12b_emu.h.

#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT   12

Shift value for EMU_WDOG1LOCKED

Definition at line 1748 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 333 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4ENTRY_MASK   0x30000UL

Bit mask for EMU_EM4ENTRY

Definition at line 332 of file efm32gg12b_emu.h.

Referenced by EMU_EnterEM4().

#define _EMU_EM4CTRL_EM4ENTRY_SHIFT   16

Shift value for EMU_EM4ENTRY

Definition at line 331 of file efm32gg12b_emu.h.

Referenced by EMU_EnterEM4().

#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 323 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE   0x00000000UL

Mode DISABLE for EMU_EM4CTRL

Definition at line 324 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT   0x00000001UL

Mode EM4EXIT for EMU_EM4CTRL

Definition at line 325 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_MASK   0x30UL

Bit mask for EMU_EM4IORETMODE

Definition at line 322 of file efm32gg12b_emu.h.

Referenced by EMU_EM4Init(), and GPIO_EM4SetPinRetention().

#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT   4

Shift value for EMU_EM4IORETMODE

Definition at line 321 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH   0x00000002UL

Mode SWUNLATCH for EMU_EM4CTRL

Definition at line 326 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4STATE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 300 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4STATE_EM4H   0x00000001UL

Mode EM4H for EMU_EM4CTRL

Definition at line 302 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4STATE_EM4S   0x00000000UL

Mode EM4S for EMU_EM4CTRL

Definition at line 301 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_EM4STATE_MASK   0x1UL

Bit mask for EMU_EM4STATE

Definition at line 299 of file efm32gg12b_emu.h.

Referenced by EMU_EM4Init(), and EMU_EnterEM4().

#define _EMU_EM4CTRL_EM4STATE_SHIFT   0

Shift value for EMU_EM4STATE

Definition at line 298 of file efm32gg12b_emu.h.

Referenced by EMU_EnterEM4H(), and EMU_EnterEM4S().

#define _EMU_EM4CTRL_MASK   0x0003003FUL

Mask for EMU_EM4CTRL

Definition at line 296 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_RESETVALUE   0x00000000UL

Default value for EMU_EM4CTRL

Definition at line 295 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 309 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_RETAINLFRCO_MASK   0x2UL

Bit mask for EMU_RETAINLFRCO

Definition at line 308 of file efm32gg12b_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT   1

Shift value for EMU_RETAINLFRCO

Definition at line 307 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 314 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_RETAINLFXO_MASK   0x4UL

Bit mask for EMU_RETAINLFXO

Definition at line 313 of file efm32gg12b_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_EM4CTRL_RETAINLFXO_SHIFT   2

Shift value for EMU_RETAINLFXO

Definition at line 312 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 319 of file efm32gg12b_emu.h.

#define _EMU_EM4CTRL_RETAINULFRCO_MASK   0x8UL

Bit mask for EMU_RETAINULFRCO

Definition at line 318 of file efm32gg12b_emu.h.

Referenced by EMU_EM4Init().

#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT   3

Shift value for EMU_RETAINULFRCO

Definition at line 317 of file efm32gg12b_emu.h.

#define _EMU_IEN_BURDY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 844 of file efm32gg12b_emu.h.

#define _EMU_IEN_BURDY_MASK   0x400000UL

Bit mask for EMU_BURDY

Definition at line 843 of file efm32gg12b_emu.h.

#define _EMU_IEN_BURDY_SHIFT   22

Shift value for EMU_BURDY

Definition at line 842 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCINBYPASS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 839 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCINBYPASS_MASK   0x100000UL

Bit mask for EMU_DCDCINBYPASS

Definition at line 838 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCINBYPASS_SHIFT   20

Shift value for EMU_DCDCINBYPASS

Definition at line 837 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCLNRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 834 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCLNRUNNING_MASK   0x80000UL

Bit mask for EMU_DCDCLNRUNNING

Definition at line 833 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCLNRUNNING_SHIFT   19

Shift value for EMU_DCDCLNRUNNING

Definition at line 832 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCLPRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 829 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCLPRUNNING_MASK   0x40000UL

Bit mask for EMU_DCDCLPRUNNING

Definition at line 828 of file efm32gg12b_emu.h.

#define _EMU_IEN_DCDCLPRUNNING_SHIFT   18

Shift value for EMU_DCDCLPRUNNING

Definition at line 827 of file efm32gg12b_emu.h.

#define _EMU_IEN_EM23WAKEUP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 854 of file efm32gg12b_emu.h.

#define _EMU_IEN_EM23WAKEUP_MASK   0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 853 of file efm32gg12b_emu.h.

#define _EMU_IEN_EM23WAKEUP_SHIFT   24

Shift value for EMU_EM23WAKEUP

Definition at line 852 of file efm32gg12b_emu.h.

#define _EMU_IEN_MASK   0xE3DF37FFUL

Mask for EMU_IEN

Definition at line 750 of file efm32gg12b_emu.h.

#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 824 of file efm32gg12b_emu.h.

#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK   0x20000UL

Bit mask for EMU_NFETOVERCURRENTLIMIT

Definition at line 823 of file efm32gg12b_emu.h.

#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT   17

Shift value for EMU_NFETOVERCURRENTLIMIT

Definition at line 822 of file efm32gg12b_emu.h.

#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 819 of file efm32gg12b_emu.h.

#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK   0x10000UL

Bit mask for EMU_PFETOVERCURRENTLIMIT

Definition at line 818 of file efm32gg12b_emu.h.

#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT   16

Shift value for EMU_PFETOVERCURRENTLIMIT

Definition at line 817 of file efm32gg12b_emu.h.

#define _EMU_IEN_R5VREADY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 804 of file efm32gg12b_emu.h.

#define _EMU_IEN_R5VREADY_MASK   0x400UL

Bit mask for EMU_R5VREADY

Definition at line 803 of file efm32gg12b_emu.h.

#define _EMU_IEN_R5VREADY_SHIFT   10

Shift value for EMU_R5VREADY

Definition at line 802 of file efm32gg12b_emu.h.

#define _EMU_IEN_R5VVSINT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 849 of file efm32gg12b_emu.h.

#define _EMU_IEN_R5VVSINT_MASK   0x800000UL

Bit mask for EMU_R5VVSINT

Definition at line 848 of file efm32gg12b_emu.h.

#define _EMU_IEN_R5VVSINT_SHIFT   23

Shift value for EMU_R5VVSINT

Definition at line 847 of file efm32gg12b_emu.h.

#define _EMU_IEN_RESETVALUE   0x00000000UL

Default value for EMU_IEN

Definition at line 749 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 864 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMP_MASK   0x20000000UL

Bit mask for EMU_TEMP

Definition at line 863 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMP_SHIFT   29

Shift value for EMU_TEMP

Definition at line 862 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMPHIGH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 874 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMPHIGH_MASK   0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 873 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMPHIGH_SHIFT   31

Shift value for EMU_TEMPHIGH

Definition at line 872 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMPLOW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 869 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMPLOW_MASK   0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 868 of file efm32gg12b_emu.h.

#define _EMU_IEN_TEMPLOW_SHIFT   30

Shift value for EMU_TEMPLOW

Definition at line 867 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 764 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONALTAVDDFALL_MASK   0x4UL

Bit mask for EMU_VMONALTAVDDFALL

Definition at line 763 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONALTAVDDFALL_SHIFT   2

Shift value for EMU_VMONALTAVDDFALL

Definition at line 762 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 769 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONALTAVDDRISE_MASK   0x8UL

Bit mask for EMU_VMONALTAVDDRISE

Definition at line 768 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONALTAVDDRISE_SHIFT   3

Shift value for EMU_VMONALTAVDDRISE

Definition at line 767 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 754 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONAVDDFALL_MASK   0x1UL

Bit mask for EMU_VMONAVDDFALL

Definition at line 753 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONAVDDFALL_SHIFT   0

Shift value for EMU_VMONAVDDFALL

Definition at line 752 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 759 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONAVDDRISE_MASK   0x2UL

Bit mask for EMU_VMONAVDDRISE

Definition at line 758 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONAVDDRISE_SHIFT   1

Shift value for EMU_VMONAVDDRISE

Definition at line 757 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONBUVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 809 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONBUVDDFALL_MASK   0x1000UL

Bit mask for EMU_VMONBUVDDFALL

Definition at line 808 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONBUVDDFALL_SHIFT   12

Shift value for EMU_VMONBUVDDFALL

Definition at line 807 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONBUVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 814 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONBUVDDRISE_MASK   0x2000UL

Bit mask for EMU_VMONBUVDDRISE

Definition at line 813 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONBUVDDRISE_SHIFT   13

Shift value for EMU_VMONBUVDDRISE

Definition at line 812 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONDVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 774 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONDVDDFALL_MASK   0x10UL

Bit mask for EMU_VMONDVDDFALL

Definition at line 773 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONDVDDFALL_SHIFT   4

Shift value for EMU_VMONDVDDFALL

Definition at line 772 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONDVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 779 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONDVDDRISE_MASK   0x20UL

Bit mask for EMU_VMONDVDDRISE

Definition at line 778 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONDVDDRISE_SHIFT   5

Shift value for EMU_VMONDVDDRISE

Definition at line 777 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO0FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 784 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO0FALL_MASK   0x40UL

Bit mask for EMU_VMONIO0FALL

Definition at line 783 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO0FALL_SHIFT   6

Shift value for EMU_VMONIO0FALL

Definition at line 782 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO0RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 789 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO0RISE_MASK   0x80UL

Bit mask for EMU_VMONIO0RISE

Definition at line 788 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO0RISE_SHIFT   7

Shift value for EMU_VMONIO0RISE

Definition at line 787 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO1FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 794 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO1FALL_MASK   0x100UL

Bit mask for EMU_VMONIO1FALL

Definition at line 793 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO1FALL_SHIFT   8

Shift value for EMU_VMONIO1FALL

Definition at line 792 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO1RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 799 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO1RISE_MASK   0x200UL

Bit mask for EMU_VMONIO1RISE

Definition at line 798 of file efm32gg12b_emu.h.

#define _EMU_IEN_VMONIO1RISE_SHIFT   9

Shift value for EMU_VMONIO1RISE

Definition at line 797 of file efm32gg12b_emu.h.

#define _EMU_IEN_VSCALEDONE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 859 of file efm32gg12b_emu.h.

#define _EMU_IEN_VSCALEDONE_MASK   0x2000000UL

Bit mask for EMU_VSCALEDONE

Definition at line 858 of file efm32gg12b_emu.h.

#define _EMU_IEN_VSCALEDONE_SHIFT   25

Shift value for EMU_VSCALEDONE

Definition at line 857 of file efm32gg12b_emu.h.

#define _EMU_IF_BURDY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 457 of file efm32gg12b_emu.h.

#define _EMU_IF_BURDY_MASK   0x400000UL

Bit mask for EMU_BURDY

Definition at line 456 of file efm32gg12b_emu.h.

#define _EMU_IF_BURDY_SHIFT   22

Shift value for EMU_BURDY

Definition at line 455 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCINBYPASS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 452 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCINBYPASS_MASK   0x100000UL

Bit mask for EMU_DCDCINBYPASS

Definition at line 451 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCINBYPASS_SHIFT   20

Shift value for EMU_DCDCINBYPASS

Definition at line 450 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCLNRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 447 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCLNRUNNING_MASK   0x80000UL

Bit mask for EMU_DCDCLNRUNNING

Definition at line 446 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCLNRUNNING_SHIFT   19

Shift value for EMU_DCDCLNRUNNING

Definition at line 445 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCLPRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 442 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCLPRUNNING_MASK   0x40000UL

Bit mask for EMU_DCDCLPRUNNING

Definition at line 441 of file efm32gg12b_emu.h.

#define _EMU_IF_DCDCLPRUNNING_SHIFT   18

Shift value for EMU_DCDCLPRUNNING

Definition at line 440 of file efm32gg12b_emu.h.

#define _EMU_IF_EM23WAKEUP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 467 of file efm32gg12b_emu.h.

#define _EMU_IF_EM23WAKEUP_MASK   0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 466 of file efm32gg12b_emu.h.

#define _EMU_IF_EM23WAKEUP_SHIFT   24

Shift value for EMU_EM23WAKEUP

Definition at line 465 of file efm32gg12b_emu.h.

#define _EMU_IF_MASK   0xE3DF37FFUL

Mask for EMU_IF

Definition at line 363 of file efm32gg12b_emu.h.

#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 437 of file efm32gg12b_emu.h.

#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK   0x20000UL

Bit mask for EMU_NFETOVERCURRENTLIMIT

Definition at line 436 of file efm32gg12b_emu.h.

#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT   17

Shift value for EMU_NFETOVERCURRENTLIMIT

Definition at line 435 of file efm32gg12b_emu.h.

#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 432 of file efm32gg12b_emu.h.

#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK   0x10000UL

Bit mask for EMU_PFETOVERCURRENTLIMIT

Definition at line 431 of file efm32gg12b_emu.h.

#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT   16

Shift value for EMU_PFETOVERCURRENTLIMIT

Definition at line 430 of file efm32gg12b_emu.h.

#define _EMU_IF_R5VREADY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 417 of file efm32gg12b_emu.h.

#define _EMU_IF_R5VREADY_MASK   0x400UL

Bit mask for EMU_R5VREADY

Definition at line 416 of file efm32gg12b_emu.h.

#define _EMU_IF_R5VREADY_SHIFT   10

Shift value for EMU_R5VREADY

Definition at line 415 of file efm32gg12b_emu.h.

#define _EMU_IF_R5VVSINT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 462 of file efm32gg12b_emu.h.

#define _EMU_IF_R5VVSINT_MASK   0x800000UL

Bit mask for EMU_R5VVSINT

Definition at line 461 of file efm32gg12b_emu.h.

#define _EMU_IF_R5VVSINT_SHIFT   23

Shift value for EMU_R5VVSINT

Definition at line 460 of file efm32gg12b_emu.h.

#define _EMU_IF_RESETVALUE   0x00000000UL

Default value for EMU_IF

Definition at line 362 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 477 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMP_MASK   0x20000000UL

Bit mask for EMU_TEMP

Definition at line 476 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMP_SHIFT   29

Shift value for EMU_TEMP

Definition at line 475 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMPHIGH_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 487 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMPHIGH_MASK   0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 486 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMPHIGH_SHIFT   31

Shift value for EMU_TEMPHIGH

Definition at line 485 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMPLOW_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 482 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMPLOW_MASK   0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 481 of file efm32gg12b_emu.h.

#define _EMU_IF_TEMPLOW_SHIFT   30

Shift value for EMU_TEMPLOW

Definition at line 480 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONALTAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 377 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONALTAVDDFALL_MASK   0x4UL

Bit mask for EMU_VMONALTAVDDFALL

Definition at line 376 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONALTAVDDFALL_SHIFT   2

Shift value for EMU_VMONALTAVDDFALL

Definition at line 375 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONALTAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 382 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONALTAVDDRISE_MASK   0x8UL

Bit mask for EMU_VMONALTAVDDRISE

Definition at line 381 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONALTAVDDRISE_SHIFT   3

Shift value for EMU_VMONALTAVDDRISE

Definition at line 380 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONAVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 367 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONAVDDFALL_MASK   0x1UL

Bit mask for EMU_VMONAVDDFALL

Definition at line 366 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONAVDDFALL_SHIFT   0

Shift value for EMU_VMONAVDDFALL

Definition at line 365 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONAVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 372 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONAVDDRISE_MASK   0x2UL

Bit mask for EMU_VMONAVDDRISE

Definition at line 371 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONAVDDRISE_SHIFT   1

Shift value for EMU_VMONAVDDRISE

Definition at line 370 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONBUVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 422 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONBUVDDFALL_MASK   0x1000UL

Bit mask for EMU_VMONBUVDDFALL

Definition at line 421 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONBUVDDFALL_SHIFT   12

Shift value for EMU_VMONBUVDDFALL

Definition at line 420 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONBUVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 427 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONBUVDDRISE_MASK   0x2000UL

Bit mask for EMU_VMONBUVDDRISE

Definition at line 426 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONBUVDDRISE_SHIFT   13

Shift value for EMU_VMONBUVDDRISE

Definition at line 425 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONDVDDFALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 387 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONDVDDFALL_MASK   0x10UL

Bit mask for EMU_VMONDVDDFALL

Definition at line 386 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONDVDDFALL_SHIFT   4

Shift value for EMU_VMONDVDDFALL

Definition at line 385 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONDVDDRISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 392 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONDVDDRISE_MASK   0x20UL

Bit mask for EMU_VMONDVDDRISE

Definition at line 391 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONDVDDRISE_SHIFT   5

Shift value for EMU_VMONDVDDRISE

Definition at line 390 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO0FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 397 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO0FALL_MASK   0x40UL

Bit mask for EMU_VMONIO0FALL

Definition at line 396 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO0FALL_SHIFT   6

Shift value for EMU_VMONIO0FALL

Definition at line 395 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO0RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 402 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO0RISE_MASK   0x80UL

Bit mask for EMU_VMONIO0RISE

Definition at line 401 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO0RISE_SHIFT   7

Shift value for EMU_VMONIO0RISE

Definition at line 400 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO1FALL_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 407 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO1FALL_MASK   0x100UL

Bit mask for EMU_VMONIO1FALL

Definition at line 406 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO1FALL_SHIFT   8

Shift value for EMU_VMONIO1FALL

Definition at line 405 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO1RISE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 412 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO1RISE_MASK   0x200UL

Bit mask for EMU_VMONIO1RISE

Definition at line 411 of file efm32gg12b_emu.h.

#define _EMU_IF_VMONIO1RISE_SHIFT   9

Shift value for EMU_VMONIO1RISE

Definition at line 410 of file efm32gg12b_emu.h.

#define _EMU_IF_VSCALEDONE_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 472 of file efm32gg12b_emu.h.

#define _EMU_IF_VSCALEDONE_MASK   0x2000000UL

Bit mask for EMU_VSCALEDONE

Definition at line 471 of file efm32gg12b_emu.h.

#define _EMU_IF_VSCALEDONE_SHIFT   25

Shift value for EMU_VSCALEDONE

Definition at line 470 of file efm32gg12b_emu.h.

#define _EMU_IFC_BURDY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 715 of file efm32gg12b_emu.h.

#define _EMU_IFC_BURDY_MASK   0x400000UL

Bit mask for EMU_BURDY

Definition at line 714 of file efm32gg12b_emu.h.

#define _EMU_IFC_BURDY_SHIFT   22

Shift value for EMU_BURDY

Definition at line 713 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCINBYPASS_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 710 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCINBYPASS_MASK   0x100000UL

Bit mask for EMU_DCDCINBYPASS

Definition at line 709 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCINBYPASS_SHIFT   20

Shift value for EMU_DCDCINBYPASS

Definition at line 708 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCLNRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 705 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCLNRUNNING_MASK   0x80000UL

Bit mask for EMU_DCDCLNRUNNING

Definition at line 704 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCLNRUNNING_SHIFT   19

Shift value for EMU_DCDCLNRUNNING

Definition at line 703 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCLPRUNNING_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 700 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCLPRUNNING_MASK   0x40000UL

Bit mask for EMU_DCDCLPRUNNING

Definition at line 699 of file efm32gg12b_emu.h.

#define _EMU_IFC_DCDCLPRUNNING_SHIFT   18

Shift value for EMU_DCDCLPRUNNING

Definition at line 698 of file efm32gg12b_emu.h.

#define _EMU_IFC_EM23WAKEUP_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 725 of file efm32gg12b_emu.h.

#define _EMU_IFC_EM23WAKEUP_MASK   0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 724 of file efm32gg12b_emu.h.

#define _EMU_IFC_EM23WAKEUP_SHIFT   24

Shift value for EMU_EM23WAKEUP

Definition at line 723 of file efm32gg12b_emu.h.

#define _EMU_IFC_MASK   0xE3DF37FFUL

Mask for EMU_IFC

Definition at line 621 of file efm32gg12b_emu.h.

#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 695 of file efm32gg12b_emu.h.

#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK   0x20000UL

Bit mask for EMU_NFETOVERCURRENTLIMIT

Definition at line 694 of file efm32gg12b_emu.h.

#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT   17

Shift value for EMU_NFETOVERCURRENTLIMIT

Definition at line 693 of file efm32gg12b_emu.h.

#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 690 of file efm32gg12b_emu.h.

#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK   0x10000UL

Bit mask for EMU_PFETOVERCURRENTLIMIT

Definition at line 689 of file efm32gg12b_emu.h.

#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT   16

Shift value for EMU_PFETOVERCURRENTLIMIT

Definition at line 688 of file efm32gg12b_emu.h.

#define _EMU_IFC_R5VREADY_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 675 of file efm32gg12b_emu.h.

#define _EMU_IFC_R5VREADY_MASK   0x400UL

Bit mask for EMU_R5VREADY

Definition at line 674 of file efm32gg12b_emu.h.

#define _EMU_IFC_R5VREADY_SHIFT   10

Shift value for EMU_R5VREADY

Definition at line 673 of file efm32gg12b_emu.h.

#define _EMU_IFC_R5VVSINT_DEFAULT   0x00000000UL

Mode DEFAULT for EMU_IFC

Definition at line 720 of file efm32gg12b_emu.h.