Detailed Description

Security Management Unit (SMU) Peripheral API.

SMU forms the control and status/reporting component of bus-level security in EFM32/EFR32 devices.

Peripheral-level protection is provided via the peripheral protection unit (PPU). PPU provides hardware access barrier to any peripheral that is configured to be protected. When an attempt is made to access a peripheral without the required privilege/security level, PPU detects the fault and intercepts the access. No write or read of the peripheral register space occurs, and an all-zero value is returned if the access is a read.

       
        // SMU is always clocked, so no call to CMU_ClockEnable() is necessary
       
        // Initialize SMU to prevent access to CMU, EMU, SMU and GPIO
       
        SMU_Init_TypeDef
       
       init =
       
        SMU_INIT_DEFAULT
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedCMU
       
       =
       
        true
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedEMU
       
       =
       
        true
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedSMU
       
       =
       
        true
       
       ;
      
       init.ppu.
       
        access
       
       .
       
        privilegedGPIO
       
       =
       
        true
       
       ;
      
        SMU_Init
       
       (&init);

Data Structures
struct	SMU_Init_TypeDef

struct	SMU_PrivilegedAccess_TypeDef

Macros
#define	SMU_INIT_DEFAULT

Enumerations
enum	SMU_Peripheral_TypeDef { smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, smuPeripheralEnd }

Functions
__STATIC_INLINE void	SMU_EnablePPU (bool enable)
	Enable or disable PPU of SMU.

__STATIC_INLINE SMU_Peripheral_TypeDef	SMU_GetFaultingPeripheral (void)
	Get ID of the peripheral that caused an access fault.

__STATIC_INLINE void	SMU_Init (const SMU_Init_TypeDef *init)
	Initialize PPU of SMU.

__STATIC_INLINE void	SMU_IntClear (uint32_t flags)
	Clear one or more pending SMU interrupts.

__STATIC_INLINE void	SMU_IntDisable (uint32_t flags)
	Disable one or more SMU interrupts.

__STATIC_INLINE void	SMU_IntEnable (uint32_t flags)
	Enable one or more SMU interrupts.

__STATIC_INLINE uint32_t	SMU_IntGet (void)
	Get pending SMU interrupts.

__STATIC_INLINE uint32_t	SMU_IntGetEnabled (void)
	Get enabled and pending SMU interrupt flags. Useful for handling more interrupt sources in the same interrupt handler.

__STATIC_INLINE void	SMU_IntSet (uint32_t flags)
	Set one or more pending SMU interrupts from SW.

__STATIC_INLINE void	SMU_SetPrivilegedAccess ( SMU_Peripheral_TypeDef peripheral, bool privileged)
	Change access settings for a peripheral.

Macro Definition Documentation

#define SMU_INIT_DEFAULT

Value:

         { \
        
         { { 0 } },
         
          /* No peripherals access protected. */
         
         \
        
         true
         
          /* Enable SMU.*/
         
         \
        
         }

Default SMU initialization structure settings.

Definition at line 823 of file em_smu.h .

Enumeration Type Documentation

enum SMU_Peripheral_TypeDef

SMU peripheral identifiers.

Enumerator
smuPeripheralACMP0	SMU peripheral identifier for ACMP0.
smuPeripheralACMP1	SMU peripheral identifier for ACMP1.
smuPeripheralACMP2	SMU peripheral identifier for ACMP2.
smuPeripheralADC0	SMU peripheral identifier for ADC0.
smuPeripheralADC1	SMU peripheral identifier for ADC1.
smuPeripheralCAN0	SMU peripheral identifier for CAN0.
smuPeripheralCAN1	SMU peripheral identifier for CAN1.
smuPeripheralCMU	SMU peripheral identifier for CMU.
smuPeripheralCRYOTIMER	SMU peripheral identifier for CRYOTIMER.
smuPeripheralCRYPTO0	SMU peripheral identifier for CRYPTO0.
smuPeripheralCSEN	SMU peripheral identifier for CSEN.
smuPeripheralVDAC0	SMU peripheral identifier for VDAC0.
smuPeripheralPRS	SMU peripheral identifier for PRS.
smuPeripheralEBI	SMU peripheral identifier for EBI.
smuPeripheralEMU	SMU peripheral identifier for EMU.
smuPeripheralFPUEH	SMU peripheral identifier for FPUEH.
smuPeripheralGPCRC	SMU peripheral identifier for GPCRC.
smuPeripheralGPIO	SMU peripheral identifier for GPIO.
smuPeripheralI2C0	SMU peripheral identifier for I2C0.
smuPeripheralI2C1	SMU peripheral identifier for I2C1.
smuPeripheralIDAC0	SMU peripheral identifier for IDAC0.
smuPeripheralMSC	SMU peripheral identifier for MAC.
smuPeripheralLCD	SMU peripheral identifier for LCD.
smuPeripheralLDMA	SMU peripheral identifier for LDMA.
smuPeripheralLESENSE	SMU peripheral identifier for LESENSE.
smuPeripheralLETIMER0	SMU peripheral identifier for LETIMER0.
smuPeripheralLETIMER1	SMU peripheral identifier for LETIMER1.
smuPeripheralLEUART0	SMU peripheral identifier for LEUART0.
smuPeripheralLEUART1	SMU peripheral identifier for LEUART1.
smuPeripheralPCNT0	SMU peripheral identifier for PCNT0.
smuPeripheralPCNT1	SMU peripheral identifier for PCNT1.
smuPeripheralPCNT2	SMU peripheral identifier for PCNT2.
smuPeripheralQSPI0	SMU peripheral identifier for QSPI0.
smuPeripheralRMU	SMU peripheral identifier for RMU.
smuPeripheralRTC	SMU peripheral identifier for RTC.
smuPeripheralRTCC	SMU peripheral identifier for RTCC.
smuPeripheralSDIO	SMU peripheral identifier for SDIO.
smuPeripheralSMU	SMU peripheral identifier for SMU.
smuPeripheralTIMER0	SMU peripheral identifier for TIMER0.
smuPeripheralTIMER1	SMU peripheral identifier for TIMER1.
smuPeripheralTIMER2	SMU peripheral identifier for TIMER2.
smuPeripheralTIMER3	SMU peripheral identifier for TIMER3.
smuPeripheralTRNG0	SMU peripheral identifier for TRNG0.
smuPeripheralUART0	SMU peripheral identifier for UART0.
smuPeripheralUART1	SMU peripheral identifier for UART1.
smuPeripheralUSART0	SMU peripheral identifier for USART0.
smuPeripheralUSART1	SMU peripheral identifier for USART1.
smuPeripheralUSART2	SMU peripheral identifier for USART2.
smuPeripheralUSART3	SMU peripheral identifier for USART3.
smuPeripheralUSART4	SMU peripheral identifier for USART4.
smuPeripheralUSB	SMU peripheral identifier for USB.
smuPeripheralWDOG0	SMU peripheral identifier for WDOG0.
smuPeripheralWDOG1	SMU peripheral identifier for WDOG1.
smuPeripheralWTIMER0	SMU peripheral identifier for WTIMER0.
smuPeripheralWTIMER1	SMU peripheral identifier for WTIMER1.

Definition at line 78 of file em_smu.h .

Function Documentation

__STATIC_INLINE void SMU_EnablePPU ( bool enable )

Enable or disable PPU of SMU.

Parameters

[in] enable Set to true to enable PPU; set to false otherwise.

Definition at line 839 of file em_smu.h .

References _SMU_PPUCTRL_ENABLE_SHIFT , BUS_RegBitWrite() , and SMU .

Referenced by SMU_Init() .

__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral ( void )

Get ID of the peripheral that caused an access fault.

Note: The return value is only valid if SMU_IF_PPUPRIV interrupt flag is set.

Returns: ID of the peripheral that caused an access fault.

Definition at line 901 of file em_smu.h .

References SMU .

__STATIC_INLINE void SMU_Init ( const SMU_Init_TypeDef * init )

Initialize PPU of SMU.

Parameters

[in] init Pointer to initialization structure that defines which peripherals should only be accessed from privileged mode, and if PPU should be enabled.

Definition at line 856 of file em_smu.h .

References SMU_Init_TypeDef::enable , SMU_Init_TypeDef::reg , SMU , and SMU_EnablePPU() .

__STATIC_INLINE void SMU_IntClear ( uint32_t flags )

Clear one or more pending SMU interrupts.

Parameters

[in] flags Bitwise logic OR of SMU interrupt sources to clear.

Definition at line 913 of file em_smu.h .

References SMU .

__STATIC_INLINE void SMU_IntDisable ( uint32_t flags )

Disable one or more SMU interrupts.

Parameters

[in] flags SMU interrupt sources to disable.

Definition at line 929 of file em_smu.h .

References SMU .

__STATIC_INLINE void SMU_IntEnable ( uint32_t flags )

Enable one or more SMU interrupts.

Note: Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. To ignore a pending interrupt, consider using SMU_IntClear() prior to enabling the interrupt.

Parameters

[in] flags SMU interrupt sources to enable.

Definition at line 950 of file em_smu.h .

References SMU .

__STATIC_INLINE uint32_t SMU_IntGet ( void )

Get pending SMU interrupts.

Returns: SMU interrupt sources pending.

Definition at line 966 of file em_smu.h .

References SMU .

__STATIC_INLINE uint32_t SMU_IntGetEnabled ( void )

Get enabled and pending SMU interrupt flags. Useful for handling more interrupt sources in the same interrupt handler.

Note: Interrupt flags are not cleared by this function.

Returns

Pending and enabled SMU interrupt sources. The return value is the bitwise AND combination of

the OR combination of enabled interrupt sources in SMU_IEN register and
the OR combination of valid interrupt flags in SMU_IF register.

Definition at line 986 of file em_smu.h .

References SMU .

__STATIC_INLINE void SMU_IntSet ( uint32_t flags )

Set one or more pending SMU interrupts from SW.

Parameters

[in] flags SMU interrupt sources to set to pending.

Definition at line 1005 of file em_smu.h .

References SMU .

__STATIC_INLINE void SMU_SetPrivilegedAccess	(	SMU_Peripheral_TypeDef	`peripheral,`
		bool	`privileged`
	)

Change access settings for a peripheral.

Set to limit access of a peripheral from privileged mode.

Parameters

[in]	`peripheral`	ID of the peripheral to change access settings for.
[in]	`privileged`	Set to true if the peripheral should only be accessed from privileged mode; set to false otherwise.

Definition at line 878 of file em_smu.h .

References BUS_RegBitWrite() , and SMU .

SMUEMLIB

Detailed Description

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation