Peripheral Memory MapDevices > EFM32GG12B830F512IL120
Macros | |
| #define | ACMP0_BASE (0x40080000UL) |
| #define | ACMP1_BASE (0x40080400UL) |
| #define | ACMP2_BASE (0x40080800UL) |
| #define | ADC0_BASE (0x40082000UL) |
| #define | ADC1_BASE (0x40082400UL) |
| #define | CAN0_BASE (0x40004000UL) |
| #define | CAN1_BASE (0x40004400UL) |
| #define | CMU_BASE (0x400E4000UL) |
| #define | CRYOTIMER_BASE (0x4008F000UL) |
| #define | CRYPTO0_BASE (0x400F0000UL) |
| #define | CSEN_BASE (0x4008E000UL) |
| #define | DEVINFO_BASE (0x0FE081B0UL) |
| #define | EBI_BASE (0x4000B000UL) |
| #define | EMU_BASE (0x400E3000UL) |
| #define | ETM_BASE (0xE0041000UL) |
| #define | FPUEH_BASE (0x40001000UL) |
| #define | GPCRC_BASE (0x4001C000UL) |
| #define | GPIO_BASE (0x40088000UL) |
| #define | I2C0_BASE (0x40089000UL) |
| #define | I2C1_BASE (0x40089400UL) |
| #define | IDAC0_BASE (0x40084000UL) |
| #define | LCD_BASE (0x40054000UL) |
| #define | LDMA_BASE (0x40002000UL) |
| #define | LESENSE_BASE (0x40055000UL) |
| #define | LETIMER0_BASE (0x40066000UL) |
| #define | LETIMER1_BASE (0x40066400UL) |
| #define | LEUART0_BASE (0x4006A000UL) |
| #define | LEUART1_BASE (0x4006A400UL) |
| #define | LOCKBITS_BASE (0x0FE04000UL) |
| #define | MSC_BASE (0x40000000UL) |
| #define | PCNT0_BASE (0x4006E000UL) |
| #define | PCNT1_BASE (0x4006E400UL) |
| #define | PCNT2_BASE (0x4006E800UL) |
| #define | PDM_BASE (0x40028000UL) |
| #define | PRS_BASE (0x400E6000UL) |
| #define | QSPI0_BASE (0x4001C400UL) |
| #define | RMU_BASE (0x400E5000UL) |
| #define | ROMTABLE_BASE (0xE00FFFD0UL) |
| #define | RTC_BASE (0x40060000UL) |
| #define | RTCC_BASE (0x40062000UL) |
| #define | SDIO_BASE (0x400F1000UL) |
| #define | SMU_BASE (0x40020000UL) |
| #define | TIMER0_BASE (0x40018000UL) |
| #define | TIMER1_BASE (0x40018400UL) |
| #define | TIMER2_BASE (0x40018800UL) |
| #define | TIMER3_BASE (0x40018C00UL) |
| #define | TRNG0_BASE (0x4001D000UL) |
| #define | UART0_BASE (0x40014000UL) |
| #define | UART1_BASE (0x40014400UL) |
| #define | USART0_BASE (0x40010000UL) |
| #define | USART1_BASE (0x40010400UL) |
| #define | USART2_BASE (0x40010800UL) |
| #define | USART3_BASE (0x40010C00UL) |
| #define | USART4_BASE (0x40011000UL) |
| #define | USB_BASE (0x40022000UL) |
| #define | USERDATA_BASE (0x0FE00000UL) |
| #define | VDAC0_BASE (0x40086000UL) |
| #define | WDOG0_BASE (0x40052000UL) |
| #define | WDOG1_BASE (0x40052400UL) |
| #define | WTIMER0_BASE (0x4001A000UL) |
| #define | WTIMER1_BASE (0x4001A400UL) |
Macro Definition Documentation
| #define ACMP0_BASE (0x40080000UL) |
ACMP0 base address
Definition at line 497 of file efm32gg12b830f512il120.h.
| #define ACMP1_BASE (0x40080400UL) |
ACMP1 base address
Definition at line 498 of file efm32gg12b830f512il120.h.
| #define ACMP2_BASE (0x40080800UL) |
ACMP2 base address
Definition at line 499 of file efm32gg12b830f512il120.h.
| #define ADC0_BASE (0x40082000UL) |
ADC0 base address
Definition at line 495 of file efm32gg12b830f512il120.h.
| #define ADC1_BASE (0x40082400UL) |
ADC1 base address
Definition at line 496 of file efm32gg12b830f512il120.h.
| #define CAN0_BASE (0x40004000UL) |
CAN0 base address
Definition at line 469 of file efm32gg12b830f512il120.h.
| #define CAN1_BASE (0x40004400UL) |
CAN1 base address
Definition at line 470 of file efm32gg12b830f512il120.h.
| #define CMU_BASE (0x400E4000UL) |
CMU base address
Definition at line 458 of file efm32gg12b830f512il120.h.
| #define CRYOTIMER_BASE (0x4008F000UL) |
CRYOTIMER base address
Definition at line 489 of file efm32gg12b830f512il120.h.
| #define CRYPTO0_BASE (0x400F0000UL) |
CRYPTO0 base address
Definition at line 459 of file efm32gg12b830f512il120.h.
| #define CSEN_BASE (0x4008E000UL) |
CSEN base address
Definition at line 503 of file efm32gg12b830f512il120.h.
| #define DEVINFO_BASE (0x0FE081B0UL) |
DEVINFO base address
Definition at line 512 of file efm32gg12b830f512il120.h.
Referenced by SYSTEM_GetCalibrationValue().
| #define EBI_BASE (0x4000B000UL) |
EBI base address
Definition at line 461 of file efm32gg12b830f512il120.h.
| #define EMU_BASE (0x400E3000UL) |
EMU base address
Definition at line 456 of file efm32gg12b830f512il120.h.
Referenced by CHIP_Init(), EMU_EnterEM4(), and RMU_ResetCauseGet().
| #define ETM_BASE (0xE0041000UL) |
ETM base address
Definition at line 509 of file efm32gg12b830f512il120.h.
| #define FPUEH_BASE (0x40001000UL) |
FPUEH base address
Definition at line 467 of file efm32gg12b830f512il120.h.
| #define GPCRC_BASE (0x4001C000UL) |
GPCRC base address
Definition at line 468 of file efm32gg12b830f512il120.h.
| #define GPIO_BASE (0x40088000UL) |
GPIO base address
Definition at line 464 of file efm32gg12b830f512il120.h.
| #define I2C0_BASE (0x40089000UL) |
I2C0 base address
Definition at line 493 of file efm32gg12b830f512il120.h.
| #define I2C1_BASE (0x40089400UL) |
I2C1 base address
Definition at line 494 of file efm32gg12b830f512il120.h.
| #define IDAC0_BASE (0x40084000UL) |
IDAC0 base address
Definition at line 502 of file efm32gg12b830f512il120.h.
| #define LCD_BASE (0x40054000UL) |
LCD base address
Definition at line 504 of file efm32gg12b830f512il120.h.
Referenced by CHIP_Init().
| #define LDMA_BASE (0x40002000UL) |
LDMA base address
Definition at line 466 of file efm32gg12b830f512il120.h.
| #define LESENSE_BASE (0x40055000UL) |
LESENSE base address
Definition at line 460 of file efm32gg12b830f512il120.h.
| #define LETIMER0_BASE (0x40066000UL) |
LETIMER0 base address
Definition at line 487 of file efm32gg12b830f512il120.h.
| #define LETIMER1_BASE (0x40066400UL) |
LETIMER1 base address
Definition at line 488 of file efm32gg12b830f512il120.h.
| #define LEUART0_BASE (0x4006A000UL) |
LEUART0 base address
Definition at line 485 of file efm32gg12b830f512il120.h.
| #define LEUART1_BASE (0x4006A400UL) |
LEUART1 base address
Definition at line 486 of file efm32gg12b830f512il120.h.
| #define LOCKBITS_BASE (0x0FE04000UL) |
Lock-bits page base address
Definition at line 514 of file efm32gg12b830f512il120.h.
Referenced by DBG_DisableDebugAccess().
| #define MSC_BASE (0x40000000UL) |
MSC base address
Definition at line 455 of file efm32gg12b830f512il120.h.
| #define PCNT0_BASE (0x4006E000UL) |
PCNT0 base address
Definition at line 490 of file efm32gg12b830f512il120.h.
| #define PCNT1_BASE (0x4006E400UL) |
PCNT1 base address
Definition at line 491 of file efm32gg12b830f512il120.h.
| #define PCNT2_BASE (0x4006E800UL) |
PCNT2 base address
Definition at line 492 of file efm32gg12b830f512il120.h.
| #define PDM_BASE (0x40028000UL) |
PDM base address
Definition at line 463 of file efm32gg12b830f512il120.h.
| #define PRS_BASE (0x400E6000UL) |
PRS base address
Definition at line 465 of file efm32gg12b830f512il120.h.
| #define QSPI0_BASE (0x4001C400UL) |
QSPI0 base address
Definition at line 484 of file efm32gg12b830f512il120.h.
| #define RMU_BASE (0x400E5000UL) |
RMU base address
Definition at line 457 of file efm32gg12b830f512il120.h.
| #define ROMTABLE_BASE (0xE00FFFD0UL) |
ROMTABLE base address
Definition at line 513 of file efm32gg12b830f512il120.h.
| #define RTC_BASE (0x40060000UL) |
RTC base address
Definition at line 505 of file efm32gg12b830f512il120.h.
| #define RTCC_BASE (0x40062000UL) |
RTCC base address
Definition at line 506 of file efm32gg12b830f512il120.h.
| #define SDIO_BASE (0x400F1000UL) |
SDIO base address
Definition at line 462 of file efm32gg12b830f512il120.h.
| #define SMU_BASE (0x40020000UL) |
SMU base address
Definition at line 510 of file efm32gg12b830f512il120.h.
| #define TIMER0_BASE (0x40018000UL) |
TIMER0 base address
Definition at line 471 of file efm32gg12b830f512il120.h.
| #define TIMER1_BASE (0x40018400UL) |
TIMER1 base address
Definition at line 472 of file efm32gg12b830f512il120.h.
| #define TIMER2_BASE (0x40018800UL) |
TIMER2 base address
Definition at line 473 of file efm32gg12b830f512il120.h.
| #define TIMER3_BASE (0x40018C00UL) |
TIMER3 base address
Definition at line 474 of file efm32gg12b830f512il120.h.
| #define TRNG0_BASE (0x4001D000UL) |
TRNG0 base address
Definition at line 511 of file efm32gg12b830f512il120.h.
| #define UART0_BASE (0x40014000UL) |
UART0 base address
Definition at line 482 of file efm32gg12b830f512il120.h.
| #define UART1_BASE (0x40014400UL) |
UART1 base address
Definition at line 483 of file efm32gg12b830f512il120.h.
| #define USART0_BASE (0x40010000UL) |
USART0 base address
Definition at line 477 of file efm32gg12b830f512il120.h.
| #define USART1_BASE (0x40010400UL) |
USART1 base address
Definition at line 478 of file efm32gg12b830f512il120.h.
| #define USART2_BASE (0x40010800UL) |
USART2 base address
Definition at line 479 of file efm32gg12b830f512il120.h.
| #define USART3_BASE (0x40010C00UL) |
USART3 base address
Definition at line 480 of file efm32gg12b830f512il120.h.
| #define USART4_BASE (0x40011000UL) |
USART4 base address
Definition at line 481 of file efm32gg12b830f512il120.h.
| #define USB_BASE (0x40022000UL) |
USB base address
Definition at line 501 of file efm32gg12b830f512il120.h.
| #define USERDATA_BASE (0x0FE00000UL) |
User data page base address
Definition at line 515 of file efm32gg12b830f512il120.h.
| #define VDAC0_BASE (0x40086000UL) |
VDAC0 base address
Definition at line 500 of file efm32gg12b830f512il120.h.
| #define WDOG0_BASE (0x40052000UL) |
WDOG0 base address
Definition at line 507 of file efm32gg12b830f512il120.h.
| #define WDOG1_BASE (0x40052400UL) |
WDOG1 base address
Definition at line 508 of file efm32gg12b830f512il120.h.
| #define WTIMER0_BASE (0x4001A000UL) |
WTIMER0 base address
Definition at line 475 of file efm32gg12b830f512il120.h.
| #define WTIMER1_BASE (0x4001A400UL) |
WTIMER1 base address
Definition at line 476 of file efm32gg12b830f512il120.h.