QSPI_TypeDef Struct ReferenceDevices > QSPI
QSPI Register Declaration
Definition at line
48
of file
efm32gg12b_qspi.h
.
#include <
efm32gg12b_qspi.h
>
Data Fields |
|
__IOM uint32_t | CONFIG |
__IOM uint32_t | DEVDELAY |
__IOM uint32_t | DEVINSTRRDCONFIG |
__IOM uint32_t | DEVINSTRWRCONFIG |
__IOM uint32_t | DEVSIZECONFIG |
__IOM uint32_t | FLASHCMDADDR |
__IOM uint32_t | FLASHCMDCTRL |
__IOM uint32_t | FLASHCOMMANDCTRLMEM |
__IM uint32_t | FLASHRDDATALOWER |
__IM uint32_t | FLASHRDDATAUPPER |
__IOM uint32_t | FLASHWRDATALOWER |
__IOM uint32_t | FLASHWRDATAUPPER |
__IOM uint32_t | INDAHBADDRTRIGGER |
__IOM uint32_t | INDIRECTREADXFERCTRL |
__IOM uint32_t | INDIRECTREADXFERNUMBYTES |
__IOM uint32_t | INDIRECTREADXFERSTART |
__IOM uint32_t | INDIRECTREADXFERWATERMARK |
__IOM uint32_t | INDIRECTTRIGGERADDRRANGE |
__IOM uint32_t | INDIRECTWRITEXFERCTRL |
__IOM uint32_t | INDIRECTWRITEXFERNUMBYTES |
__IOM uint32_t | INDIRECTWRITEXFERSTART |
__IOM uint32_t | INDIRECTWRITEXFERWATERMARK |
__IOM uint32_t | IRQMASK |
__IOM uint32_t | IRQSTATUS |
__IOM uint32_t | LOWERWRPROT |
__IOM uint32_t | MODEBITCONFIG |
__IM uint32_t | MODULEID |
__IOM uint32_t | NOOFPOLLSBEFEXP |
__IOM uint32_t | OPCODEEXTLOWER |
__IOM uint32_t | OPCODEEXTUPPER |
__IOM uint32_t | PHYCONFIGURATION |
__IOM uint32_t | POLLINGFLASHSTATUS |
__IOM uint32_t | RDDATACAPTURE |
__IOM uint32_t | REMAPADDR |
uint32_t | RESERVED0 [1U] |
uint32_t | RESERVED1 [2U] |
uint32_t | RESERVED2 [1U] |
uint32_t | RESERVED3 [2U] |
uint32_t | RESERVED4 [2U] |
uint32_t | RESERVED5 [10U] |
uint32_t | RESERVED6 [5U] |
uint32_t | RESERVED7 [1U] |
__IOM uint32_t | ROUTELOC0 |
__IOM uint32_t | ROUTEPEN |
__IOM uint32_t | RXTHRESH |
__IM uint32_t | SRAMFILL |
__IOM uint32_t | SRAMPARTITIONCFG |
__IOM uint32_t | TXTHRESH |
__IOM uint32_t | UPPERWRPROT |
__IOM uint32_t | WRITECOMPLETIONCTRL |
__IOM uint32_t | WRPROTCTRL |
Field Documentation
__IOM uint32_t QSPI_TypeDef::CONFIG |
Octal-SPI Configuration Register
Definition at line
49
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_Enable() , QSPI_Init() , and QSPI_WaitForIdle() .
__IOM uint32_t QSPI_TypeDef::DEVDELAY |
Device Delay Register
Definition at line
52
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::DEVINSTRRDCONFIG |
Device Read Instruction Configuration Register
Definition at line
50
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_ReadConfig() .
__IOM uint32_t QSPI_TypeDef::DEVINSTRWRCONFIG |
Device Write Instruction Configuration Register
Definition at line
51
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_WriteConfig() .
__IOM uint32_t QSPI_TypeDef::DEVSIZECONFIG |
Device Size Configuration Register
Definition at line
54
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::FLASHCMDADDR |
Flash Command Address Register (STIG)
Definition at line
84
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_ExecStigCmd() .
__IOM uint32_t QSPI_TypeDef::FLASHCMDCTRL |
Flash Command Control Register (STIG)
Definition at line
83
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_ExecStigCmd() .
__IOM uint32_t QSPI_TypeDef::FLASHCOMMANDCTRLMEM |
Flash Command Control Memory Register (STIG)
Definition at line
82
of file
efm32gg12b_qspi.h
.
__IM uint32_t QSPI_TypeDef::FLASHRDDATALOWER |
Flash Command Read Data Register (Lower) (STIG)
Definition at line
86
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_ExecStigCmd() .
__IM uint32_t QSPI_TypeDef::FLASHRDDATAUPPER |
Flash Command Read Data Register (Upper) (STIG)
Definition at line
87
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_ExecStigCmd() .
__IOM uint32_t QSPI_TypeDef::FLASHWRDATALOWER |
Flash Command Write Data Register (Lower) (STIG)
Definition at line
88
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_ExecStigCmd() .
__IOM uint32_t QSPI_TypeDef::FLASHWRDATAUPPER |
Flash Command Write Data Register (Upper) (STIG)
Definition at line
89
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_ExecStigCmd() .
__IOM uint32_t QSPI_TypeDef::INDAHBADDRTRIGGER |
Indirect Address Trigger Register
Definition at line
56
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTREADXFERCTRL |
Indirect Read Transfer Control Register
Definition at line
72
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTREADXFERNUMBYTES |
Indirect Read Transfer Number Bytes Register
Definition at line
75
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTREADXFERSTART |
Indirect Read Transfer Start Address Register
Definition at line
74
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTREADXFERWATERMARK |
Indirect Read Transfer Watermark Register
Definition at line
73
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTTRIGGERADDRRANGE |
Indirect Trigger Address Range Register
Definition at line
80
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTWRITEXFERCTRL |
Indirect Write Transfer Control Register
Definition at line
76
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTWRITEXFERNUMBYTES |
Indirect Write Transfer Number Bytes Register
Definition at line
79
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTWRITEXFERSTART |
Indirect Write Transfer Start Address Register
Definition at line
78
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::INDIRECTWRITEXFERWATERMARK |
Indirect Write Transfer Watermark Register
Definition at line
77
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::IRQMASK |
Interrupt Mask
Definition at line
66
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_IntDisable() , and QSPI_IntEnable() .
__IOM uint32_t QSPI_TypeDef::IRQSTATUS |
Interrupt Status Register
Definition at line
65
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_IntClear() , and QSPI_IntGet() .
__IOM uint32_t QSPI_TypeDef::LOWERWRPROT |
Lower Write Protection Register
Definition at line
68
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::MODEBITCONFIG |
Mode Bit Configuration Register
Definition at line
59
of file
efm32gg12b_qspi.h
.
__IM uint32_t QSPI_TypeDef::MODULEID |
Module ID Register
Definition at line
97
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::NOOFPOLLSBEFEXP |
Polling Expiration Register
Definition at line
64
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::OPCODEEXTLOWER |
Opcode Extension Register (Lower)
Definition at line
94
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::OPCODEEXTUPPER |
Opcode Extension Register (Upper)
Definition at line
95
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::PHYCONFIGURATION |
PHY Configuration Register
Definition at line
91
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::POLLINGFLASHSTATUS |
Polling Flash Status Register
Definition at line
90
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::RDDATACAPTURE |
Read Data Capture Register
Definition at line
53
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::REMAPADDR |
Remap Address Register
Definition at line
58
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED0[1U] |
Reserved for future use
Definition at line
57
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED1[2U] |
Reserved for future use
Definition at line
67
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED2[1U] |
Reserved for future use
Definition at line
71
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED3[2U] |
Reserved for future use
Definition at line
81
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED4[2U] |
Reserved for future use
Definition at line
85
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED5[10U] |
Reserved for future use
Definition at line
93
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED6[5U] |
Reserved for future use
Definition at line
96
of file
efm32gg12b_qspi.h
.
uint32_t QSPI_TypeDef::RESERVED7[1U] |
Reserved for future use
Definition at line
99
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::ROUTELOC0 |
I/O Route Location Register 0
Definition at line
101
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::ROUTEPEN |
I/O Routing Pin Enable Register
Definition at line
100
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::RXTHRESH |
RX Threshold Register
Definition at line
62
of file
efm32gg12b_qspi.h
.
__IM uint32_t QSPI_TypeDef::SRAMFILL |
SRAM Fill Register
Definition at line
60
of file
efm32gg12b_qspi.h
.
Referenced by QSPI_GetReadLevel() , and QSPI_GetWriteLevel() .
__IOM uint32_t QSPI_TypeDef::SRAMPARTITIONCFG |
SRAM Partition Configuration Register
Definition at line
55
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::TXTHRESH |
TX Threshold Register
Definition at line
61
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::UPPERWRPROT |
Upper Write Protection Register
Definition at line
69
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::WRITECOMPLETIONCTRL |
Write Completion Control Register
Definition at line
63
of file
efm32gg12b_qspi.h
.
__IOM uint32_t QSPI_TypeDef::WRPROTCTRL |
Write Protection Control Register
Definition at line
70
of file
efm32gg12b_qspi.h
.
The documentation for this struct was generated from the following file:
-
C:/repos/super_h1/platform/Device/SiliconLabs/EFM32GG12B/Include/
efm32gg12b_qspi.h