Si7210 Details
Description
Register interface and implementation details.
Functions |
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sl_status_t | sl_si7210_read_otp_register (sl_i2cspm_t *i2cspm, uint8_t otpAddr, uint8_t *otpData) |
Read register from the OTP area of the Si7021 device.
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sl_status_t | sl_si7210_read_register (sl_i2cspm_t *i2cspm, uint8_t addr, uint8_t *data) |
Read register from the Hall sensor device.
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sl_status_t | sl_si7210_write_register (sl_i2cspm_t *i2cspm, uint8_t addr, uint8_t data) |
Write a register in the Hall sensor device.
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sl_status_t | sl_si7210_set_register_bits (sl_i2cspm_t *i2cspm, uint8_t addr, uint8_t mask) |
Set the given bit(s) in a register in the Hall sensor device.
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sl_status_t | sl_si7210_clear_register_bits (sl_i2cspm_t *i2cspm, uint8_t addr, uint8_t mask) |
Clear the given bit(s) in a register in the Hall sensor device.
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uint8_t | sl_si7210_calculate_sw_op (float threshold) |
Calculate the sw_op value from the threshold by finding the inverse of the formula: threshold = (16 + sw_op[3:0]) * 2^sw_op[6:4].
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uint8_t | sl_si7210_calculate_sw_hyst (float hysteresis, bool scale200mT) |
Calculate the sw_hyst value from the hysteresis by finding the inverse of the formula: hysteresis = (8 + sw_hyst[2:0]) * 2^sw_hyst[5:3].
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uint8_t | sl_si7210_calculate_sw_tamper (float tamper, bool scale200mT) |
Calculate the sw_tamper value from the tamper threshold by finding the inverse of the formula: tamper = (16 + sw_tamper[3:0]) * 2^(sw_tamper[5:4] + 5)
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uint8_t | sl_si7210_calculate_sltime (uint32_t samplePeriod, uint8_t *slFast) |
Calculate the slTime value from the sleep time by finding the inverse of the formula: tsleep = (32 + slTime[4:0]) * 2^(8 + slTime[7:5]) / 12 MHz.
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Registers |
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#define | SI7210_REG_ADDR_HREVID 0xC0 |
Hardware revision ID register
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#define | SI7210_REG_ADDR_DSPSIGM 0xC1 |
The most significant byte of the last conversion result
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#define | SI7210_REG_ADDR_DSPSIGL 0xC2 |
The least significant byte of the last conversion result
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#define | SI7210_REG_ADDR_DSPSIGSEL 0xC3 |
Select the data after filtering
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#define | SI7210_REG_ADDR_POWER_CTRL 0xC4 |
Power control register
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#define | SI7210_REG_ADDR_ARAUTOINC 0xC5 |
Enables auto increment of the I2C register address pointer
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#define | SI7210_REG_ADDR_CTRL1 0xC6 |
Control register 1, output pin configuration
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#define | SI7210_REG_ADDR_CTRL2 0xC7 |
Control register 2, output pin configuration
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#define | SI7210_REG_ADDR_SLTIME 0xC8 |
Sleep time control register
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#define | SI7210_REG_ADDR_CTRL3 0xC9 |
Control register 3, output pin and sleep time configuration
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#define | SI7210_REG_ADDR_A0 0xCA |
Coefficient A0
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#define | SI7210_REG_ADDR_A1 0xCB |
Coefficient A1
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#define | SI7210_REG_ADDR_A2 0xCC |
Coefficient A2
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#define | SI7210_REG_ADDR_CTRL4 0xCD |
Control register 4, Digital filter configuration
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#define | SI7210_REG_ADDR_A3 0xCE |
Coefficient A3
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#define | SI7210_REG_ADDR_A4 0xCF |
Coefficient A4
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#define | SI7210_REG_ADDR_A5 0xD0 |
Coefficient A5
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#define | SI7210_REG_ADDR_OTP_ADDR 0xE1 |
OTP address of the data to read
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#define | SI7210_REG_ADDR_OTP_DATA 0xE2 |
Data read from OTP
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#define | SI7210_REG_ADDR_OTP_CTRL 0xE3 |
OTP read control register
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#define | SI7210_REG_ADDR_TM_FG 0xE4 |
On-chip test coil control
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#define | SI7210_REG_HREVID_REVID_MASK 0x0F |
Revision ID mask, Hardware revision ID register
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#define | SI7210_REG_HREVID_REVID_SHIFT 0 |
Revision ID shift value, Hardware revision ID register
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#define | SI7210_REG_HREVID_CHIPID_MASK 0xF0 |
Chip ID mask, Hardware revision ID register
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#define | SI7210_REG_HREVID_CHIPID_SHIFT 4 |
Revision ID shift value, Hardware revision ID register
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#define | SI7210_REG_DSPSIGM_FRESH_MASK 0x80 |
New data available mask, MSB of last conversion result register
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#define | SI7210_REG_DSPSIGM_FRESH_SHIFT 7 |
New data available shift value, MSB of last conversion result register
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#define | SI7210_REG_DSPSIGM_DSPSIGM_MASK 0x7F |
MSB bits of conversion mask, MSB of last conversion result register
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#define | SI7210_REG_DSPSIGM_DSPSIGM_SHIFT 0 |
MSB bits of conversion shift value, MSB of last conversion result register
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#define | SI7210_REG_POWER_CTRL_SLEEP_MASK 0x01 |
Sleep mode bit mask, Power control register
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#define | SI7210_REG_POWER_CTRL_SLEEP_SHIFT 0 |
Sleep mode bit shift value, Power control register
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#define | SI7210_REG_POWER_CTRL_STOP_MASK 0x02 |
Stop bit mask, Power control register
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#define | SI7210_REG_POWER_CTRL_STOP_SHIFT 1 |
Stop bit shift value, Power control register
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#define | SI7210_REG_POWER_CTRL_ONEBURST_MASK 0x04 |
One burst mesurement bit mask, Power control register
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#define | SI7210_REG_POWER_CTRL_ONEBURST_SHIFT 2 |
One burst mesurement bit shift value, Power control register
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#define | SI7210_REG_POWER_CTRL_USESTORE_MASK 0x08 |
Save the current state of OTP regs bit mask, Power control register
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#define | SI7210_REG_POWER_CTRL_USESTORE_SHIFT 3 |
Save the current state of OTP regs bit shift value, Power control register
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#define | SI7210_REG_POWER_CTRL_MEAS_MASK 0x80 |
Measurement in progress bit mask, Power control register
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#define | SI7210_REG_POWER_CTRL_MEAS_SHIFT 7 |
Measurement in progress bit shift value, Power control register
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#define | SI7210_REG_CTRL1_SW_OP_MASK 0x7F |
Switching point mask, Control register 1
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#define | SI7210_REG_CTRL1_SW_OP_SHIFT 0 |
Switching point shift value, Control register 1
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#define | SI7210_REG_CTRL1_SW_LOW4FIELD_MASK 0x80 |
Output polarity setting bit mask, Control register 1
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#define | SI7210_REG_CTRL1_SW_LOW4FIELD_SHIFT 7 |
Output polarity setting bit shift value, Control register 1
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#define | SI7210_REG_CTRL2_SW_HYST_MASK 0x3F |
Switch hysteresis mask, Control register 2
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#define | SI7210_REG_CTRL2_SW_HYST_SHIFT 0 |
Switch hyteresis shift value, Control register 2
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#define | SI7210_REG_CTRL2_SW_FIELDPOLSEL_MASK 0xC0 |
Switch polarity mask, Control register 2
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#define | SI7210_REG_CTRL2_SW_FIELDPOLSEL_SHIFT 6 |
Switchi polarity shift value, Control register 2
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#define | SI7210_REG_CTRL3_SLTIMEENA_MASK 0x01 |
Sleep timer enable bit mask, Control register 3
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#define | SI7210_REG_CTRL3_SLTIMEENA_SHIFT 0 |
Sleep timer enable bit shift value, Control register 3
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#define | SI7210_REG_CTRL3_SLFAST_MASK 0x02 |
Sleep time reduction enable bit mask, Control register 3
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#define | SI7210_REG_CTRL3_SLFAST_SHIFT 1 |
Sleep time reduction bit shift value, Control register 3
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#define | SI7210_REG_CTRL3_SW_TAMPER_MASK 0xFC |
Tamper switch threshold mask, Control register 3
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#define | SI7210_REG_CTRL3_SW_TAMPER_SHIFT 2 |
Tamper switch threshold shift value, Control register 3
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#define | SI7210_REG_CTRL4_IIR_MASK 0x01 |
IIR filter enable bit mask, Control register 4
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#define | SI7210_REG_CTRL4_IIR_SHIFT 0 |
IIR filter enable bit shift value, Control register 4
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#define | SI7210_REG_CTRL4_DF_BW_MASK 0x1E |
Number of samples to average mask, Control register 4
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#define | SI7210_REG_CTRL4_DF_BW_SHIFT 1 |
Number of samples to average shift value, Control register 4
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#define | SI7210_REG_CTRL4_DF_BURSTSIZE_MASK 0x0E |
Measurement burst size mask, Control register 4
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#define | SI7210_REG_CTRL4_DF_BURSTSIZE_SHIFT 5 |
Measurement burst size shift value, Control register 4
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#define | SI7210_REG_OTP_CTRL_BUSY_MASK 0x01 |
OTP busy indicator bit mask, OTP read control register
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#define | SI7210_REG_OTP_CTRL_BUSY_SHIFT 0 |
OTP busy indicator bit shift value, OTP read control register
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#define | SI7210_REG_OTP_CTRL_READ_EN_MASK 0x02 |
OTP read enable bit mask, OTP read control register
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#define | SI7210_REG_OTP_CTRL_READ_EN_SHIFT 1 |
OTP read enable bit shift value, OTP read control register
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#define | SI7210_OTP_ADDR_CTRL1 0x04 |
OTP Control register 1, output pin configuration
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#define | SI7210_OTP_ADDR_CTRL2 0x05 |
OTP Control register 2, output pin configuration
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#define | SI7210_OTP_ADDR_SLTIME 0x06 |
OTP Sleep time control register
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#define | SI7210_OTP_ADDR_CTRL3 0x08 |
OTP Control register 3, output pin and sleep time configuration
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#define | SI7210_OTP_ADDR_POWER_UP_A0 0x09 |
OTP Coefficient A0
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#define | SI7210_OTP_ADDR_POWER_UP_A1 0x0A |
OTP Coefficient A1
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#define | SI7210_OTP_ADDR_POWER_UP_A2 0x0B |
OTP Coefficient A2
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#define | SI7210_OTP_ADDR_CTRL4 0x0C |
OTP Control register 4, Digital filter configuration
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#define | SI7210_OTP_ADDR_POWER_UP_A3 0x0D |
OTP Coefficient A3
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#define | SI7210_OTP_ADDR_POWER_UP_A4 0x0E |
OTP Coefficient A4
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#define | SI7210_OTP_ADDR_POWER_UP_A5 0x0F |
OTP Coefficient A5
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#define | SI7210_OTP_ADDR_BASE_PART_NUMBER 0x14 |
OTP Base part number
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#define | SI7210_OTP_ADDR_VARIANT 0x15 |
OTP Variant number
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#define | SI7210_OTP_ADDR_SERIAL_NUMBER 0x18 |
OTP Serial number
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#define | SI7210_OTP_ADDR_BPERVCAL 0x20 |
OTP On-chip field generator calibration value
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#define | SI7210_OTP_ADDR_COEFFS_20MT 0x21 |
OTP 20mT scale no magnet temperature compensation value
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#define | SI7210_OTP_ADDR_COEFFS_200MT 0x27 |
OTP 200mT scale no magnet temperature compensation value
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#define | SI7210_OTP_ADDR_COEFFS_20MT_NEODYMIUM 0x2D |
OTP 20mT scale neodymium magnet temperature compensation value
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#define | SI7210_OTP_ADDR_COEFFS_200MT_NEODYMIUM 0x33 |
OTP 200mT scale neodymium temperature compensation value
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#define | SI7210_OTP_ADDR_COEFFS_20MT_CERAMIC 0x39 |
OTP 20mT scale ceramic magnet temperature compensation value
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#define | SI7210_OTP_ADDR_COEFFS_200MT_CERAMIC 0x3F |
OTP 200mT scale ceramic magnet temperature compensation value
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Function Documentation
◆ sl_si7210_read_otp_register()
sl_status_t sl_si7210_read_otp_register | ( | sl_i2cspm_t * |
i2cspm,
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uint8_t |
otpAddr,
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uint8_t * |
otpData
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Read register from the OTP area of the Si7021 device.
- Parameters
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[in] i2cspm
The I2CSPM instance to use. [in] otpAddr
The register address to read from in the sensor [out] otpData
The data read from the device
- Return values
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SL_STATUS_OK
Success SL_STATUS_TRANSMIT
I2C transmission error
◆ sl_si7210_read_register()
sl_status_t sl_si7210_read_register | ( | sl_i2cspm_t * |
i2cspm,
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uint8_t |
addr,
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uint8_t * |
data
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Read register from the Hall sensor device.
- Parameters
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[in] i2cspm
The I2CSPM instance to use. [in] addr
The register address to read from in the sensor [out] data
The data read from the device
- Return values
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SL_STATUS_OK
Success SL_STATUS_TRANSMIT
I2C transmission error
◆ sl_si7210_write_register()
sl_status_t sl_si7210_write_register | ( | sl_i2cspm_t * |
i2cspm,
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uint8_t |
addr,
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uint8_t |
data
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Write a register in the Hall sensor device.
- Parameters
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[in] i2cspm
The I2CSPM instance to use. [in] addr
The register address to write [in] data
The data to write to the register
- Return values
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SL_STATUS_OK
Success SL_STATUS_TRANSMIT
I2C transmission error
◆ sl_si7210_set_register_bits()
sl_status_t sl_si7210_set_register_bits | ( | sl_i2cspm_t * |
i2cspm,
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uint8_t |
addr,
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uint8_t |
mask
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Set the given bit(s) in a register in the Hall sensor device.
- Parameters
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[in] i2cspm
The I2CSPM instance to use. [in] addr
The address of the register [in] mask
The mask specifies which bits should be set. If a given bit of the mask is 1, that register bit will be set to 1. All the other register bits will be untouched.
- Return values
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SL_STATUS_OK
Success SL_STATUS_TRANSMIT
I2C transmission error
◆ sl_si7210_clear_register_bits()
sl_status_t sl_si7210_clear_register_bits | ( | sl_i2cspm_t * |
i2cspm,
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uint8_t |
addr,
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uint8_t |
mask
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Clear the given bit(s) in a register in the Hall sensor device.
- Parameters
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[in] i2cspm
The I2CSPM instance to use. [in] addr
The address of the register [in] mask
The mask specifies which bits should be clear. If a given bit of the mask is 1 that register bit will be cleared to 0. All the other register bits will be untouched.
- Return values
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SL_STATUS_OK
Success SL_STATUS_TRANSMIT
I2C transmission error
◆ sl_si7210_calculate_sw_op()
uint8_t sl_si7210_calculate_sw_op | ( | float |
threshold
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Calculate the sw_op value from the threshold by finding the inverse of the formula: threshold = (16 + sw_op[3:0]) * 2^sw_op[6:4].
- Parameters
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[in] threshold
Threshold value
- Returns
- The value of the sw_op bitfield
◆ sl_si7210_calculate_sw_hyst()
uint8_t sl_si7210_calculate_sw_hyst | ( | float |
hysteresis,
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bool |
scale200mT
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Calculate the sw_hyst value from the hysteresis by finding the inverse of the formula: hysteresis = (8 + sw_hyst[2:0]) * 2^sw_hyst[5:3].
- Parameters
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[in] hysteresis
Hysteresis value [in] scale200mT
scale200mT=false : full-scale equals 20mT scale200mT=true : full-scale equals 200mT
- Returns
- The value of the sw_hyst bitfield
◆ sl_si7210_calculate_sw_tamper()
uint8_t sl_si7210_calculate_sw_tamper | ( | float |
tamper,
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bool |
scale200mT
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Calculate the sw_tamper value from the tamper threshold by finding the inverse of the formula: tamper = (16 + sw_tamper[3:0]) * 2^(sw_tamper[5:4] + 5)
- Parameters
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[in] tamper
Tamper value
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- Parameters
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[in] scale200mT
scale200mT=false : full-scale equals 20mT scale200mT=true : full-scale equals 200mT
- Returns
- The value of the sw_tamper bitfield
◆ sl_si7210_calculate_sltime()
uint8_t sl_si7210_calculate_sltime | ( | uint32_t |
samplePeriod,
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uint8_t * |
slFast
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Calculate the slTime value from the sleep time by finding the inverse of the formula: tsleep = (32 + slTime[4:0]) * 2^(8 + slTime[7:5]) / 12 MHz.
- Parameters
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[in] samplePeriod
The sleep time [out] slFast
The value of the slFast bit
- Returns
- The value of the slTime bitfield
Macro Definition Documentation
◆ SI7210_REG_ADDR_HREVID
#define SI7210_REG_ADDR_HREVID 0xC0 |
Hardware revision ID register
◆ SI7210_REG_ADDR_DSPSIGM
#define SI7210_REG_ADDR_DSPSIGM 0xC1 |
The most significant byte of the last conversion result
◆ SI7210_REG_ADDR_DSPSIGL
#define SI7210_REG_ADDR_DSPSIGL 0xC2 |
The least significant byte of the last conversion result
◆ SI7210_REG_ADDR_DSPSIGSEL
#define SI7210_REG_ADDR_DSPSIGSEL 0xC3 |
Select the data after filtering
◆ SI7210_REG_ADDR_POWER_CTRL
#define SI7210_REG_ADDR_POWER_CTRL 0xC4 |
Power control register
◆ SI7210_REG_ADDR_ARAUTOINC
#define SI7210_REG_ADDR_ARAUTOINC 0xC5 |
Enables auto increment of the I2C register address pointer
◆ SI7210_REG_ADDR_CTRL1
#define SI7210_REG_ADDR_CTRL1 0xC6 |
Control register 1, output pin configuration
◆ SI7210_REG_ADDR_CTRL2
#define SI7210_REG_ADDR_CTRL2 0xC7 |
Control register 2, output pin configuration
◆ SI7210_REG_ADDR_SLTIME
#define SI7210_REG_ADDR_SLTIME 0xC8 |
Sleep time control register
◆ SI7210_REG_ADDR_CTRL3
#define SI7210_REG_ADDR_CTRL3 0xC9 |
Control register 3, output pin and sleep time configuration
◆ SI7210_REG_ADDR_A0
#define SI7210_REG_ADDR_A0 0xCA |
Coefficient A0
◆ SI7210_REG_ADDR_A1
#define SI7210_REG_ADDR_A1 0xCB |
Coefficient A1
◆ SI7210_REG_ADDR_A2
#define SI7210_REG_ADDR_A2 0xCC |
Coefficient A2
◆ SI7210_REG_ADDR_CTRL4
#define SI7210_REG_ADDR_CTRL4 0xCD |
Control register 4, Digital filter configuration
◆ SI7210_REG_ADDR_A3
#define SI7210_REG_ADDR_A3 0xCE |
Coefficient A3
◆ SI7210_REG_ADDR_A4
#define SI7210_REG_ADDR_A4 0xCF |
Coefficient A4
◆ SI7210_REG_ADDR_A5
#define SI7210_REG_ADDR_A5 0xD0 |
Coefficient A5
◆ SI7210_REG_ADDR_OTP_ADDR
#define SI7210_REG_ADDR_OTP_ADDR 0xE1 |
OTP address of the data to read
◆ SI7210_REG_ADDR_OTP_DATA
#define SI7210_REG_ADDR_OTP_DATA 0xE2 |
Data read from OTP
◆ SI7210_REG_ADDR_OTP_CTRL
#define SI7210_REG_ADDR_OTP_CTRL 0xE3 |
OTP read control register
◆ SI7210_REG_ADDR_TM_FG
#define SI7210_REG_ADDR_TM_FG 0xE4 |
On-chip test coil control
◆ SI7210_REG_HREVID_REVID_MASK
#define SI7210_REG_HREVID_REVID_MASK 0x0F |
Revision ID mask, Hardware revision ID register
◆ SI7210_REG_HREVID_REVID_SHIFT
#define SI7210_REG_HREVID_REVID_SHIFT 0 |
Revision ID shift value, Hardware revision ID register
◆ SI7210_REG_HREVID_CHIPID_MASK
#define SI7210_REG_HREVID_CHIPID_MASK 0xF0 |
Chip ID mask, Hardware revision ID register
◆ SI7210_REG_HREVID_CHIPID_SHIFT
#define SI7210_REG_HREVID_CHIPID_SHIFT 4 |
Revision ID shift value, Hardware revision ID register
◆ SI7210_REG_DSPSIGM_FRESH_MASK
#define SI7210_REG_DSPSIGM_FRESH_MASK 0x80 |
New data available mask, MSB of last conversion result register
◆ SI7210_REG_DSPSIGM_FRESH_SHIFT
#define SI7210_REG_DSPSIGM_FRESH_SHIFT 7 |
New data available shift value, MSB of last conversion result register
◆ SI7210_REG_DSPSIGM_DSPSIGM_MASK
#define SI7210_REG_DSPSIGM_DSPSIGM_MASK 0x7F |
MSB bits of conversion mask, MSB of last conversion result register
◆ SI7210_REG_DSPSIGM_DSPSIGM_SHIFT
#define SI7210_REG_DSPSIGM_DSPSIGM_SHIFT 0 |
MSB bits of conversion shift value, MSB of last conversion result register
◆ SI7210_REG_POWER_CTRL_SLEEP_MASK
#define SI7210_REG_POWER_CTRL_SLEEP_MASK 0x01 |
Sleep mode bit mask, Power control register
◆ SI7210_REG_POWER_CTRL_SLEEP_SHIFT
#define SI7210_REG_POWER_CTRL_SLEEP_SHIFT 0 |
Sleep mode bit shift value, Power control register
◆ SI7210_REG_POWER_CTRL_STOP_MASK
#define SI7210_REG_POWER_CTRL_STOP_MASK 0x02 |
Stop bit mask, Power control register
◆ SI7210_REG_POWER_CTRL_STOP_SHIFT
#define SI7210_REG_POWER_CTRL_STOP_SHIFT 1 |
Stop bit shift value, Power control register
◆ SI7210_REG_POWER_CTRL_ONEBURST_MASK
#define SI7210_REG_POWER_CTRL_ONEBURST_MASK 0x04 |
One burst mesurement bit mask, Power control register
◆ SI7210_REG_POWER_CTRL_ONEBURST_SHIFT
#define SI7210_REG_POWER_CTRL_ONEBURST_SHIFT 2 |
One burst mesurement bit shift value, Power control register
◆ SI7210_REG_POWER_CTRL_USESTORE_MASK
#define SI7210_REG_POWER_CTRL_USESTORE_MASK 0x08 |
Save the current state of OTP regs bit mask, Power control register
◆ SI7210_REG_POWER_CTRL_USESTORE_SHIFT
#define SI7210_REG_POWER_CTRL_USESTORE_SHIFT 3 |
Save the current state of OTP regs bit shift value, Power control register
◆ SI7210_REG_POWER_CTRL_MEAS_MASK
#define SI7210_REG_POWER_CTRL_MEAS_MASK 0x80 |
Measurement in progress bit mask, Power control register
◆ SI7210_REG_POWER_CTRL_MEAS_SHIFT
#define SI7210_REG_POWER_CTRL_MEAS_SHIFT 7 |
Measurement in progress bit shift value, Power control register
◆ SI7210_REG_CTRL1_SW_OP_MASK
#define SI7210_REG_CTRL1_SW_OP_MASK 0x7F |
Switching point mask, Control register 1
◆ SI7210_REG_CTRL1_SW_OP_SHIFT
#define SI7210_REG_CTRL1_SW_OP_SHIFT 0 |
Switching point shift value, Control register 1
◆ SI7210_REG_CTRL1_SW_LOW4FIELD_MASK
#define SI7210_REG_CTRL1_SW_LOW4FIELD_MASK 0x80 |
Output polarity setting bit mask, Control register 1
◆ SI7210_REG_CTRL1_SW_LOW4FIELD_SHIFT
#define SI7210_REG_CTRL1_SW_LOW4FIELD_SHIFT 7 |
Output polarity setting bit shift value, Control register 1
◆ SI7210_REG_CTRL2_SW_HYST_MASK
#define SI7210_REG_CTRL2_SW_HYST_MASK 0x3F |
Switch hysteresis mask, Control register 2
◆ SI7210_REG_CTRL2_SW_HYST_SHIFT
#define SI7210_REG_CTRL2_SW_HYST_SHIFT 0 |
Switch hyteresis shift value, Control register 2
◆ SI7210_REG_CTRL2_SW_FIELDPOLSEL_MASK
#define SI7210_REG_CTRL2_SW_FIELDPOLSEL_MASK 0xC0 |
Switch polarity mask, Control register 2
◆ SI7210_REG_CTRL2_SW_FIELDPOLSEL_SHIFT
#define SI7210_REG_CTRL2_SW_FIELDPOLSEL_SHIFT 6 |
Switchi polarity shift value, Control register 2
◆ SI7210_REG_CTRL3_SLTIMEENA_MASK
#define SI7210_REG_CTRL3_SLTIMEENA_MASK 0x01 |
Sleep timer enable bit mask, Control register 3
◆ SI7210_REG_CTRL3_SLTIMEENA_SHIFT
#define SI7210_REG_CTRL3_SLTIMEENA_SHIFT 0 |
Sleep timer enable bit shift value, Control register 3
◆ SI7210_REG_CTRL3_SLFAST_MASK
#define SI7210_REG_CTRL3_SLFAST_MASK 0x02 |
Sleep time reduction enable bit mask, Control register 3
◆ SI7210_REG_CTRL3_SLFAST_SHIFT
#define SI7210_REG_CTRL3_SLFAST_SHIFT 1 |
Sleep time reduction bit shift value, Control register 3
◆ SI7210_REG_CTRL3_SW_TAMPER_MASK
#define SI7210_REG_CTRL3_SW_TAMPER_MASK 0xFC |
Tamper switch threshold mask, Control register 3
◆ SI7210_REG_CTRL3_SW_TAMPER_SHIFT
#define SI7210_REG_CTRL3_SW_TAMPER_SHIFT 2 |
Tamper switch threshold shift value, Control register 3
◆ SI7210_REG_CTRL4_IIR_MASK
#define SI7210_REG_CTRL4_IIR_MASK 0x01 |
IIR filter enable bit mask, Control register 4
◆ SI7210_REG_CTRL4_IIR_SHIFT
#define SI7210_REG_CTRL4_IIR_SHIFT 0 |
IIR filter enable bit shift value, Control register 4
◆ SI7210_REG_CTRL4_DF_BW_MASK
#define SI7210_REG_CTRL4_DF_BW_MASK 0x1E |
Number of samples to average mask, Control register 4
◆ SI7210_REG_CTRL4_DF_BW_SHIFT
#define SI7210_REG_CTRL4_DF_BW_SHIFT 1 |
Number of samples to average shift value, Control register 4
◆ SI7210_REG_CTRL4_DF_BURSTSIZE_MASK
#define SI7210_REG_CTRL4_DF_BURSTSIZE_MASK 0x0E |
Measurement burst size mask, Control register 4
◆ SI7210_REG_CTRL4_DF_BURSTSIZE_SHIFT
#define SI7210_REG_CTRL4_DF_BURSTSIZE_SHIFT 5 |
Measurement burst size shift value, Control register 4
◆ SI7210_REG_OTP_CTRL_BUSY_MASK
#define SI7210_REG_OTP_CTRL_BUSY_MASK 0x01 |
OTP busy indicator bit mask, OTP read control register
◆ SI7210_REG_OTP_CTRL_BUSY_SHIFT
#define SI7210_REG_OTP_CTRL_BUSY_SHIFT 0 |
OTP busy indicator bit shift value, OTP read control register
◆ SI7210_REG_OTP_CTRL_READ_EN_MASK
#define SI7210_REG_OTP_CTRL_READ_EN_MASK 0x02 |
OTP read enable bit mask, OTP read control register
◆ SI7210_REG_OTP_CTRL_READ_EN_SHIFT
#define SI7210_REG_OTP_CTRL_READ_EN_SHIFT 1 |
OTP read enable bit shift value, OTP read control register
◆ SI7210_OTP_ADDR_CTRL1
#define SI7210_OTP_ADDR_CTRL1 0x04 |
OTP Control register 1, output pin configuration
◆ SI7210_OTP_ADDR_CTRL2
#define SI7210_OTP_ADDR_CTRL2 0x05 |
OTP Control register 2, output pin configuration
◆ SI7210_OTP_ADDR_SLTIME
#define SI7210_OTP_ADDR_SLTIME 0x06 |
OTP Sleep time control register
◆ SI7210_OTP_ADDR_CTRL3
#define SI7210_OTP_ADDR_CTRL3 0x08 |
OTP Control register 3, output pin and sleep time configuration
◆ SI7210_OTP_ADDR_POWER_UP_A0
#define SI7210_OTP_ADDR_POWER_UP_A0 0x09 |
OTP Coefficient A0
◆ SI7210_OTP_ADDR_POWER_UP_A1
#define SI7210_OTP_ADDR_POWER_UP_A1 0x0A |
OTP Coefficient A1
◆ SI7210_OTP_ADDR_POWER_UP_A2
#define SI7210_OTP_ADDR_POWER_UP_A2 0x0B |
OTP Coefficient A2
◆ SI7210_OTP_ADDR_CTRL4
#define SI7210_OTP_ADDR_CTRL4 0x0C |
OTP Control register 4, Digital filter configuration
◆ SI7210_OTP_ADDR_POWER_UP_A3
#define SI7210_OTP_ADDR_POWER_UP_A3 0x0D |
OTP Coefficient A3
◆ SI7210_OTP_ADDR_POWER_UP_A4
#define SI7210_OTP_ADDR_POWER_UP_A4 0x0E |
OTP Coefficient A4
◆ SI7210_OTP_ADDR_POWER_UP_A5
#define SI7210_OTP_ADDR_POWER_UP_A5 0x0F |
OTP Coefficient A5
◆ SI7210_OTP_ADDR_BASE_PART_NUMBER
#define SI7210_OTP_ADDR_BASE_PART_NUMBER 0x14 |
OTP Base part number
◆ SI7210_OTP_ADDR_VARIANT
#define SI7210_OTP_ADDR_VARIANT 0x15 |
OTP Variant number
◆ SI7210_OTP_ADDR_SERIAL_NUMBER
#define SI7210_OTP_ADDR_SERIAL_NUMBER 0x18 |
OTP Serial number
◆ SI7210_OTP_ADDR_BPERVCAL
#define SI7210_OTP_ADDR_BPERVCAL 0x20 |
OTP On-chip field generator calibration value
◆ SI7210_OTP_ADDR_COEFFS_20MT
#define SI7210_OTP_ADDR_COEFFS_20MT 0x21 |
OTP 20mT scale no magnet temperature compensation value
◆ SI7210_OTP_ADDR_COEFFS_200MT
#define SI7210_OTP_ADDR_COEFFS_200MT 0x27 |
OTP 200mT scale no magnet temperature compensation value
◆ SI7210_OTP_ADDR_COEFFS_20MT_NEODYMIUM
#define SI7210_OTP_ADDR_COEFFS_20MT_NEODYMIUM 0x2D |
OTP 20mT scale neodymium magnet temperature compensation value
◆ SI7210_OTP_ADDR_COEFFS_200MT_NEODYMIUM
#define SI7210_OTP_ADDR_COEFFS_200MT_NEODYMIUM 0x33 |
OTP 200mT scale neodymium temperature compensation value
◆ SI7210_OTP_ADDR_COEFFS_20MT_CERAMIC
#define SI7210_OTP_ADDR_COEFFS_20MT_CERAMIC 0x39 |
OTP 20mT scale ceramic magnet temperature compensation value
◆ SI7210_OTP_ADDR_COEFFS_200MT_CERAMIC
#define SI7210_OTP_ADDR_COEFFS_200MT_CERAMIC 0x3F |
OTP 200mT scale ceramic magnet temperature compensation value