Description

Tamper configuration options. Levels, signals and filter options.

Macros

#define SL_SE_TAMPER_LEVEL_IGNORE 0
No action taken.
#define SL_SE_TAMPER_LEVEL_INTERRUPT 1
Generate interrupt.
#define SL_SE_TAMPER_LEVEL_FILTER 2
Increment filter counter.
#define SL_SE_TAMPER_LEVEL_RESET 4
System reset.
#define SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP 7
Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL!
#define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0
Reserved tamper signal.
#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1
Filter counter exceeds threshold.
#define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2
SE watchdog timeout.
#define SL_SE_TAMPER_SIGNAL_RESERVED_2 0x3
Reserved tamper signal.
#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2 0x4
SE RAM 2-bit ECC error.
#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT 0x5
SE CPU hardfault.
#define SL_SE_TAMPER_SIGNAL_RESERVED_3 0x6
Reserved tamper signal.
#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0x7
SE software triggers an assert.
#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED 0x8
Secure boot of SE firmware failed.
#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9
Secure boot of user code failed.
#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA
Unauthorised command received over the Mailbox interface.
#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB
Unauthorised command received over the DCI interface.
#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR 0xC
Flash content couldn't be properly authenticated.
#define SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD
Reserved tamper signal.
#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE
Integrity error of internal storage is detected.
#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF
TRNG monitor detected lack of entropy.
#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x10
Debug lock internal logic check failed.
#define SL_SE_TAMPER_ATAMPDET_EMPGD 0x11
Electromagnetic pulse glitch detector.
#define SL_SE_TAMPER_ATAMPDET_SUPGD 0x12
Supply glitch detector.
#define SL_SE_TAMPER_SE_ICACHE_ERROR 0x13
SE ICache RAM error.
#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1 0x14
SE RAM 1-bit ECC error.
#define SL_SE_TAMPER_SIGNAL_BOD 0x15
Brown-out-detector threshold alert.
#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x16
On-device temperature sensor.
#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW 0x17
DPLL lock fail low.
#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH 0x18
DPLL lock fail high.
#define SL_SE_TAMPER_SIGNAL_PRS0 0x19
PRS channel 0 asserted.
#define SL_SE_TAMPER_SIGNAL_PRS1 0x1a
PRS channel 1 asserted.
#define SL_SE_TAMPER_SIGNAL_PRS2 0x1b
PRS channel 2 asserted.
#define SL_SE_TAMPER_SIGNAL_PRS3 0x1c
PRS channel 3 asserted.
#define SL_SE_TAMPER_SIGNAL_PRS4 0x1d
PRS channel 4 asserted.
#define SL_SE_TAMPER_SIGNAL_PRS5 0x1e
PRS channel 5 asserted.
#define SL_SE_TAMPER_SIGNAL_PRS6 0x1f
PRS channel 6 asserted.
#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20
Number of tamper signals.
#define SL_SE_TAMPER_FILTER_PERIOD_32MS 0x0
Timeout ~32ms.
#define SL_SE_TAMPER_FILTER_PERIOD_64MS 0x1
Timeout ~64ms.
#define SL_SE_TAMPER_FILTER_PERIOD_128MS 0x2
Timeout ~128ms.
#define SL_SE_TAMPER_FILTER_PERIOD_256MS 0x3
Timeout ~256ms.
#define SL_SE_TAMPER_FILTER_PERIOD_512MS 0x4
Timeout ~512ms.
#define SL_SE_TAMPER_FILTER_PERIOD_1S 0x5
Timeout ~1s.
#define SL_SE_TAMPER_FILTER_PERIOD_2S 0x6
Timeout ~2s.
#define SL_SE_TAMPER_FILTER_PERIOD_4S 0x7
Timeout ~4.1s.
#define SL_SE_TAMPER_FILTER_PERIOD_8S 0x8
Timeout ~8.2s.
#define SL_SE_TAMPER_FILTER_PERIOD_16S 0x9
Timeout ~16.4s.
#define SL_SE_TAMPER_FILTER_PERIOD_33S 0xA
Timeout ~32.8s.
#define SL_SE_TAMPER_FILTER_PERIOD_1MIN 0xB
Timeout ~1.1min.
#define SL_SE_TAMPER_FILTER_PERIOD_2MIN 0xC
Timeout ~2.2min.
#define SL_SE_TAMPER_FILTER_PERIOD_4MIN 0xD
Timeout ~4.4min.
#define SL_SE_TAMPER_FILTER_PERIOD_9MIN 0xE
Timeout ~8.7min.
#define SL_SE_TAMPER_FILTER_PERIOD_18MIN 0xF
Timeout ~17.5min.
#define SL_SE_TAMPER_FILTER_PERIOD_35MIN 0x10
Timeout ~35min.
#define SL_SE_TAMPER_FILTER_PERIOD_1H 0x11
Timeout ~1.2h.
#define SL_SE_TAMPER_FILTER_PERIOD_2H 0x12
Timeout ~2.3h.
#define SL_SE_TAMPER_FILTER_PERIOD_5H 0x13
Timeout ~4.7h.
#define SL_SE_TAMPER_FILTER_PERIOD_9H 0x14
Timeout ~9.3h.
#define SL_SE_TAMPER_FILTER_PERIOD_19H 0x15
Timeout ~18.6h.
#define SL_SE_TAMPER_FILTER_PERIOD_2DAYS 0x16
Timeout ~1.6days.
#define SL_SE_TAMPER_FILTER_PERIOD_3DAYS 0x17
Timeout ~3.1days.
#define SL_SE_TAMPER_FILTER_PERIOD_6DAYS 0x18
Timeout ~6.2days.
#define SL_SE_TAMPER_FILTER_PERIOD_12DAYS 0x19
Timeout ~12.4days.
#define SL_SE_TAMPER_FILTER_PERIOD_25DAYS 0x1A
Timeout ~24.9days.
#define SL_SE_TAMPER_FILTER_PERIOD_50DAYS 0x1B
Timeout ~49.7days.
#define SL_SE_TAMPER_FILTER_PERIOD_100DAYS 0x1C
Timeout ~99.4days.
#define SL_SE_TAMPER_FILTER_PERIOD_199DAYS 0x1D
Timeout ~198.8days.
#define SL_SE_TAMPER_FILTER_PERIOD_398DAYS 0x1E
Timeout ~397.7days.
#define SL_SE_TAMPER_FILTER_PERIOD_795DAYS 0x1F
Timeout ~795.4days.
#define SL_SE_TAMPER_FILTER_THRESHOLD_2 0x7
Counter threshold 2.
#define SL_SE_TAMPER_FILTER_THRESHOLD_4 0x6
Counter threshold 4.
#define SL_SE_TAMPER_FILTER_THRESHOLD_8 0x5
Counter threshold 8.
#define SL_SE_TAMPER_FILTER_THRESHOLD_16 0x4
Counter threshold 16.
#define SL_SE_TAMPER_FILTER_THRESHOLD_32 0x3
Counter threshold 32.
#define SL_SE_TAMPER_FILTER_THRESHOLD_64 0x2
Counter threshold 64.
#define SL_SE_TAMPER_FILTER_THRESHOLD_128 0x1
Counter threshold 128.
#define SL_SE_TAMPER_FILTER_THRESHOLD_256 0x0
Counter threshold 256.
#define SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON (1UL << 1)
Tamper flags.

Macro Definition Documentation

SL_SE_TAMPER_LEVEL_IGNORE

#define SL_SE_TAMPER_LEVEL_IGNORE   0

No action taken.

SL_SE_TAMPER_LEVEL_INTERRUPT

#define SL_SE_TAMPER_LEVEL_INTERRUPT   1

Generate interrupt.

SL_SE_TAMPER_LEVEL_FILTER

#define SL_SE_TAMPER_LEVEL_FILTER   2

Increment filter counter.

SL_SE_TAMPER_LEVEL_RESET

#define SL_SE_TAMPER_LEVEL_RESET   4

System reset.

SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP

#define SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP   7

Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL!

SL_SE_TAMPER_SIGNAL_RESERVED_1

#define SL_SE_TAMPER_SIGNAL_RESERVED_1   0x0

Reserved tamper signal.

SL_SE_TAMPER_SIGNAL_FILTER_COUNTER

#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER   0x1

Filter counter exceeds threshold.

SL_SE_TAMPER_SIGNAL_WATCHDOG

#define SL_SE_TAMPER_SIGNAL_WATCHDOG   0x2

SE watchdog timeout.

SL_SE_TAMPER_SIGNAL_RESERVED_2

#define SL_SE_TAMPER_SIGNAL_RESERVED_2   0x3

Reserved tamper signal.

SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2

#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2   0x4

SE RAM 2-bit ECC error.

SL_SE_TAMPER_SIGNAL_SE_HARDFAULT

#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT   0x5

SE CPU hardfault.

SL_SE_TAMPER_SIGNAL_RESERVED_3

#define SL_SE_TAMPER_SIGNAL_RESERVED_3   0x6

Reserved tamper signal.

SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION

#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION   0x7

SE software triggers an assert.

SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED

#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED   0x8

Secure boot of SE firmware failed.

SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED

#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED   0x9

Secure boot of user code failed.

SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR

#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR   0xA

Unauthorised command received over the Mailbox interface.

SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR

#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR   0xB

Unauthorised command received over the DCI interface.

SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR

#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR   0xC

Flash content couldn't be properly authenticated.

SL_SE_TAMPER_SIGNAL_RESERVED_4

#define SL_SE_TAMPER_SIGNAL_RESERVED_4   0xD

Reserved tamper signal.

SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED

#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED   0xE

Integrity error of internal storage is detected.

SL_SE_TAMPER_SIGNAL_TRNG_MONITOR

#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR   0xF

TRNG monitor detected lack of entropy.

SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR

#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR   0x10

Debug lock internal logic check failed.

SL_SE_TAMPER_ATAMPDET_EMPGD

#define SL_SE_TAMPER_ATAMPDET_EMPGD   0x11

Electromagnetic pulse glitch detector.

SL_SE_TAMPER_ATAMPDET_SUPGD

#define SL_SE_TAMPER_ATAMPDET_SUPGD   0x12

Supply glitch detector.

SL_SE_TAMPER_SE_ICACHE_ERROR

#define SL_SE_TAMPER_SE_ICACHE_ERROR   0x13

SE ICache RAM error.

SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1

#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1   0x14

SE RAM 1-bit ECC error.

SL_SE_TAMPER_SIGNAL_BOD

#define SL_SE_TAMPER_SIGNAL_BOD   0x15

Brown-out-detector threshold alert.

SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR

#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR   0x16

On-device temperature sensor.

SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW

#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW   0x17

DPLL lock fail low.

SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH

#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH   0x18

DPLL lock fail high.

SL_SE_TAMPER_SIGNAL_PRS0

#define SL_SE_TAMPER_SIGNAL_PRS0   0x19

PRS channel 0 asserted.

SL_SE_TAMPER_SIGNAL_PRS1

#define SL_SE_TAMPER_SIGNAL_PRS1   0x1a

PRS channel 1 asserted.

SL_SE_TAMPER_SIGNAL_PRS2

#define SL_SE_TAMPER_SIGNAL_PRS2   0x1b

PRS channel 2 asserted.

SL_SE_TAMPER_SIGNAL_PRS3

#define SL_SE_TAMPER_SIGNAL_PRS3   0x1c

PRS channel 3 asserted.

SL_SE_TAMPER_SIGNAL_PRS4

#define SL_SE_TAMPER_SIGNAL_PRS4   0x1d

PRS channel 4 asserted.

SL_SE_TAMPER_SIGNAL_PRS5

#define SL_SE_TAMPER_SIGNAL_PRS5   0x1e

PRS channel 5 asserted.

SL_SE_TAMPER_SIGNAL_PRS6

#define SL_SE_TAMPER_SIGNAL_PRS6   0x1f

PRS channel 6 asserted.

SL_SE_TAMPER_SIGNAL_NUM_SIGNALS

#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS   0x20

Number of tamper signals.

SL_SE_TAMPER_FILTER_PERIOD_32MS

#define SL_SE_TAMPER_FILTER_PERIOD_32MS   0x0

Timeout ~32ms.

SL_SE_TAMPER_FILTER_PERIOD_64MS

#define SL_SE_TAMPER_FILTER_PERIOD_64MS   0x1

Timeout ~64ms.

SL_SE_TAMPER_FILTER_PERIOD_128MS

#define SL_SE_TAMPER_FILTER_PERIOD_128MS   0x2

Timeout ~128ms.

SL_SE_TAMPER_FILTER_PERIOD_256MS

#define SL_SE_TAMPER_FILTER_PERIOD_256MS   0x3

Timeout ~256ms.

SL_SE_TAMPER_FILTER_PERIOD_512MS

#define SL_SE_TAMPER_FILTER_PERIOD_512MS   0x4

Timeout ~512ms.

SL_SE_TAMPER_FILTER_PERIOD_1S

#define SL_SE_TAMPER_FILTER_PERIOD_1S   0x5

Timeout ~1s.

SL_SE_TAMPER_FILTER_PERIOD_2S

#define SL_SE_TAMPER_FILTER_PERIOD_2S   0x6

Timeout ~2s.

SL_SE_TAMPER_FILTER_PERIOD_4S

#define SL_SE_TAMPER_FILTER_PERIOD_4S   0x7

Timeout ~4.1s.

SL_SE_TAMPER_FILTER_PERIOD_8S

#define SL_SE_TAMPER_FILTER_PERIOD_8S   0x8

Timeout ~8.2s.

SL_SE_TAMPER_FILTER_PERIOD_16S

#define SL_SE_TAMPER_FILTER_PERIOD_16S   0x9

Timeout ~16.4s.

SL_SE_TAMPER_FILTER_PERIOD_33S

#define SL_SE_TAMPER_FILTER_PERIOD_33S   0xA

Timeout ~32.8s.

SL_SE_TAMPER_FILTER_PERIOD_1MIN

#define SL_SE_TAMPER_FILTER_PERIOD_1MIN   0xB

Timeout ~1.1min.

SL_SE_TAMPER_FILTER_PERIOD_2MIN

#define SL_SE_TAMPER_FILTER_PERIOD_2MIN   0xC

Timeout ~2.2min.

SL_SE_TAMPER_FILTER_PERIOD_4MIN

#define SL_SE_TAMPER_FILTER_PERIOD_4MIN   0xD

Timeout ~4.4min.

SL_SE_TAMPER_FILTER_PERIOD_9MIN

#define SL_SE_TAMPER_FILTER_PERIOD_9MIN   0xE

Timeout ~8.7min.

SL_SE_TAMPER_FILTER_PERIOD_18MIN

#define SL_SE_TAMPER_FILTER_PERIOD_18MIN   0xF

Timeout ~17.5min.

SL_SE_TAMPER_FILTER_PERIOD_35MIN

#define SL_SE_TAMPER_FILTER_PERIOD_35MIN   0x10

Timeout ~35min.

SL_SE_TAMPER_FILTER_PERIOD_1H

#define SL_SE_TAMPER_FILTER_PERIOD_1H   0x11

Timeout ~1.2h.

SL_SE_TAMPER_FILTER_PERIOD_2H

#define SL_SE_TAMPER_FILTER_PERIOD_2H   0x12

Timeout ~2.3h.

SL_SE_TAMPER_FILTER_PERIOD_5H

#define SL_SE_TAMPER_FILTER_PERIOD_5H   0x13

Timeout ~4.7h.

SL_SE_TAMPER_FILTER_PERIOD_9H

#define SL_SE_TAMPER_FILTER_PERIOD_9H   0x14

Timeout ~9.3h.

SL_SE_TAMPER_FILTER_PERIOD_19H

#define SL_SE_TAMPER_FILTER_PERIOD_19H   0x15

Timeout ~18.6h.

SL_SE_TAMPER_FILTER_PERIOD_2DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_2DAYS   0x16

Timeout ~1.6days.

SL_SE_TAMPER_FILTER_PERIOD_3DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_3DAYS   0x17

Timeout ~3.1days.

SL_SE_TAMPER_FILTER_PERIOD_6DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_6DAYS   0x18

Timeout ~6.2days.

SL_SE_TAMPER_FILTER_PERIOD_12DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_12DAYS   0x19

Timeout ~12.4days.

SL_SE_TAMPER_FILTER_PERIOD_25DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_25DAYS   0x1A

Timeout ~24.9days.

SL_SE_TAMPER_FILTER_PERIOD_50DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_50DAYS   0x1B

Timeout ~49.7days.

SL_SE_TAMPER_FILTER_PERIOD_100DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_100DAYS   0x1C

Timeout ~99.4days.

SL_SE_TAMPER_FILTER_PERIOD_199DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_199DAYS   0x1D

Timeout ~198.8days.

SL_SE_TAMPER_FILTER_PERIOD_398DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_398DAYS   0x1E

Timeout ~397.7days.

SL_SE_TAMPER_FILTER_PERIOD_795DAYS

#define SL_SE_TAMPER_FILTER_PERIOD_795DAYS   0x1F

Timeout ~795.4days.

SL_SE_TAMPER_FILTER_THRESHOLD_2

#define SL_SE_TAMPER_FILTER_THRESHOLD_2   0x7

Counter threshold 2.

SL_SE_TAMPER_FILTER_THRESHOLD_4

#define SL_SE_TAMPER_FILTER_THRESHOLD_4   0x6

Counter threshold 4.

SL_SE_TAMPER_FILTER_THRESHOLD_8

#define SL_SE_TAMPER_FILTER_THRESHOLD_8   0x5

Counter threshold 8.

SL_SE_TAMPER_FILTER_THRESHOLD_16

#define SL_SE_TAMPER_FILTER_THRESHOLD_16   0x4

Counter threshold 16.

SL_SE_TAMPER_FILTER_THRESHOLD_32

#define SL_SE_TAMPER_FILTER_THRESHOLD_32   0x3

Counter threshold 32.

SL_SE_TAMPER_FILTER_THRESHOLD_64

#define SL_SE_TAMPER_FILTER_THRESHOLD_64   0x2

Counter threshold 64.

SL_SE_TAMPER_FILTER_THRESHOLD_128

#define SL_SE_TAMPER_FILTER_THRESHOLD_128   0x1

Counter threshold 128.

SL_SE_TAMPER_FILTER_THRESHOLD_256

#define SL_SE_TAMPER_FILTER_THRESHOLD_256   0x0

Counter threshold 256.

SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON

#define SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON   (1UL << 1)

Tamper flags.