SMU Bit FieldsDevices > SMU
Macro Definition Documentation
#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_BMPUFS
Definition at line
846
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL |
Bit mask for SMU_BMPUFSMASTERID
Definition at line
845
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 |
Shift value for SMU_BMPUFSMASTERID
Definition at line
844
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFS_MASK 0x000000FFUL |
Mask for SMU_BMPUFS
Definition at line
843
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFS_RESETVALUE 0x00000000UL |
Default value for SMU_BMPUFS
Definition at line
842
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_BMPUFSADDR
Definition at line
854
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL |
Bit mask for SMU_BMPUFSADDR
Definition at line
853
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 |
Shift value for SMU_BMPUFSADDR
Definition at line
852
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL |
Mask for SMU_BMPUFSADDR
Definition at line
851
of file
efr32bg21_smu.h
.
#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL |
Default value for SMU_BMPUFSADDR
Definition at line
850
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_BUFC_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUPATD0
Definition at line
789
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_BUFC_MASK 0x4UL |
Bit mask for SMU_BUFC
Definition at line
788
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_BUFC_SHIFT 2 |
Shift value for SMU_BUFC
Definition at line
787
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUPATD0
Definition at line
799
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_LDMA_MASK 0x10UL |
Bit mask for SMU_LDMA
Definition at line
798
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_LDMA_SHIFT 4 |
Shift value for SMU_LDMA
Definition at line
797
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_MASK 0x0000003FUL |
Mask for SMU_BMPUPATD0
Definition at line
775
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUPATD0
Definition at line
779
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL |
Bit mask for SMU_RADIOAES
Definition at line
778
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 |
Shift value for SMU_RADIOAES
Definition at line
777
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUPATD0
Definition at line
794
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_MASK 0x8UL |
Bit mask for SMU_RADIOIFADCDEBUG
Definition at line
793
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_SHIFT 3 |
Shift value for SMU_RADIOIFADCDEBUG
Definition at line
792
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUPATD0
Definition at line
784
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL |
Bit mask for SMU_RADIOSUBSYSTEM
Definition at line
783
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 |
Shift value for SMU_RADIOSUBSYSTEM
Definition at line
782
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL |
Default value for SMU_BMPUPATD0
Definition at line
774
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_SEDMA_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUPATD0
Definition at line
804
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_SEDMA_MASK 0x20UL |
Bit mask for SMU_SEDMA
Definition at line
803
of file
efr32bg21_smu.h
.
#define _SMU_BMPUPATD0_SEDMA_SHIFT 5 |
Shift value for SMU_SEDMA
Definition at line
802
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_BUFC_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUSATD0
Definition at line
823
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_BUFC_MASK 0x4UL |
Bit mask for SMU_BUFC
Definition at line
822
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_BUFC_SHIFT 2 |
Shift value for SMU_BUFC
Definition at line
821
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUSATD0
Definition at line
833
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_LDMA_MASK 0x10UL |
Bit mask for SMU_LDMA
Definition at line
832
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_LDMA_SHIFT 4 |
Shift value for SMU_LDMA
Definition at line
831
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_MASK 0x0000003FUL |
Mask for SMU_BMPUSATD0
Definition at line
809
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUSATD0
Definition at line
813
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL |
Bit mask for SMU_RADIOAES
Definition at line
812
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 |
Shift value for SMU_RADIOAES
Definition at line
811
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUSATD0
Definition at line
828
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_MASK 0x8UL |
Bit mask for SMU_RADIOIFADCDEBUG
Definition at line
827
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_SHIFT 3 |
Shift value for SMU_RADIOIFADCDEBUG
Definition at line
826
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUSATD0
Definition at line
818
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL |
Bit mask for SMU_RADIOSUBSYSTEM
Definition at line
817
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 |
Shift value for SMU_RADIOSUBSYSTEM
Definition at line
816
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL |
Default value for SMU_BMPUSATD0
Definition at line
808
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_SEDMA_DEFAULT 0x00000001UL |
Mode DEFAULT for SMU_BMPUSATD0
Definition at line
838
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_SEDMA_MASK 0x20UL |
Bit mask for SMU_SEDMA
Definition at line
837
of file
efr32bg21_smu.h
.
#define _SMU_BMPUSATD0_SEDMA_SHIFT 5 |
Shift value for SMU_SEDMA
Definition at line
836
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x00002000UL |
Mode DEFAULT for SMU_ESAUMRB01
Definition at line
880
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL |
Bit mask for SMU_ESAUMRB01
Definition at line
879
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 |
Shift value for SMU_ESAUMRB01
Definition at line
878
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL |
Mask for SMU_ESAUMRB01
Definition at line
877
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB01_RESETVALUE 0x02000000UL |
Default value for SMU_ESAUMRB01
Definition at line
876
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x00004000UL |
Mode DEFAULT for SMU_ESAUMRB12
Definition at line
888
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL |
Bit mask for SMU_ESAUMRB12
Definition at line
887
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 |
Shift value for SMU_ESAUMRB12
Definition at line
886
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL |
Mask for SMU_ESAUMRB12
Definition at line
885
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB12_RESETVALUE 0x04000000UL |
Default value for SMU_ESAUMRB12
Definition at line
884
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL |
Mode DEFAULT for SMU_ESAUMRB45
Definition at line
896
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL |
Bit mask for SMU_ESAUMRB45
Definition at line
895
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 |
Shift value for SMU_ESAUMRB45
Definition at line
894
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL |
Mask for SMU_ESAUMRB45
Definition at line
893
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL |
Default value for SMU_ESAUMRB45
Definition at line
892
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL |
Mode DEFAULT for SMU_ESAUMRB56
Definition at line
904
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL |
Bit mask for SMU_ESAUMRB56
Definition at line
903
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 |
Shift value for SMU_ESAUMRB56
Definition at line
902
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL |
Mask for SMU_ESAUMRB56
Definition at line
901
of file
efr32bg21_smu.h
.
#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL |
Default value for SMU_ESAUMRB56
Definition at line
900
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_ESAURTYPES0
Definition at line
863
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL |
Bit mask for SMU_ESAUR3NS
Definition at line
862
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 |
Shift value for SMU_ESAUR3NS
Definition at line
861
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES0_MASK 0x00001000UL |
Mask for SMU_ESAURTYPES0
Definition at line
859
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL |
Default value for SMU_ESAURTYPES0
Definition at line
858
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_ESAURTYPES1
Definition at line
872
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL |
Bit mask for SMU_ESAUR11NS
Definition at line
871
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 |
Shift value for SMU_ESAUR11NS
Definition at line
870
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES1_MASK 0x00001000UL |
Mask for SMU_ESAURTYPES1
Definition at line
868
of file
efr32bg21_smu.h
.
#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL |
Default value for SMU_ESAURTYPES1
Definition at line
867
of file
efr32bg21_smu.h
.
#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IEN
Definition at line
267
of file
efr32bg21_smu.h
.
#define _SMU_IEN_BMPUSEC_MASK 0x20000UL |
Bit mask for SMU_BMPUSEC
Definition at line
266
of file
efr32bg21_smu.h
.
#define _SMU_IEN_BMPUSEC_SHIFT 17 |
Shift value for SMU_BMPUSEC
Definition at line
265
of file
efr32bg21_smu.h
.
#define _SMU_IEN_MASK 0x00030005UL |
Mask for SMU_IEN
Definition at line
248
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IEN
Definition at line
257
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUINST_MASK 0x4UL |
Bit mask for SMU_PPUINST
Definition at line
256
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUINST_SHIFT 2 |
Shift value for SMU_PPUINST
Definition at line
255
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IEN
Definition at line
252
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line
251
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line
250
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IEN
Definition at line
262
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUSEC_MASK 0x10000UL |
Bit mask for SMU_PPUSEC
Definition at line
261
of file
efr32bg21_smu.h
.
#define _SMU_IEN_PPUSEC_SHIFT 16 |
Shift value for SMU_PPUSEC
Definition at line
260
of file
efr32bg21_smu.h
.
#define _SMU_IEN_RESETVALUE 0x00000000UL |
Default value for SMU_IEN
Definition at line
247
of file
efr32bg21_smu.h
.
#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IF
Definition at line
243
of file
efr32bg21_smu.h
.
#define _SMU_IF_BMPUSEC_MASK 0x20000UL |
Bit mask for SMU_BMPUSEC
Definition at line
242
of file
efr32bg21_smu.h
.
#define _SMU_IF_BMPUSEC_SHIFT 17 |
Shift value for SMU_BMPUSEC
Definition at line
241
of file
efr32bg21_smu.h
.
#define _SMU_IF_MASK 0x00030005UL |
Mask for SMU_IF
Definition at line
224
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IF
Definition at line
233
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUINST_MASK 0x4UL |
Bit mask for SMU_PPUINST
Definition at line
232
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUINST_SHIFT 2 |
Shift value for SMU_PPUINST
Definition at line
231
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IF
Definition at line
228
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUPRIV_MASK 0x1UL |
Bit mask for SMU_PPUPRIV
Definition at line
227
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUPRIV_SHIFT 0 |
Shift value for SMU_PPUPRIV
Definition at line
226
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IF
Definition at line
238
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUSEC_MASK 0x10000UL |
Bit mask for SMU_PPUSEC
Definition at line
237
of file
efr32bg21_smu.h
.
#define _SMU_IF_PPUSEC_SHIFT 16 |
Shift value for SMU_PPUSEC
Definition at line
236
of file
efr32bg21_smu.h
.
#define _SMU_IF_RESETVALUE 0x00000000UL |
Default value for SMU_IF
Definition at line
223
of file
efr32bg21_smu.h
.
#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_IPVERSION
Definition at line
191
of file
efr32bg21_smu.h
.
#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL |
Bit mask for SMU_IPVERSION
Definition at line
190
of file
efr32bg21_smu.h
.
#define _SMU_IPVERSION_IPVERSION_SHIFT 0 |
Shift value for SMU_IPVERSION
Definition at line
189
of file
efr32bg21_smu.h
.
#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL |
Mask for SMU_IPVERSION
Definition at line
188
of file
efr32bg21_smu.h
.
#define _SMU_IPVERSION_RESETVALUE 0x00000000UL |
Default value for SMU_IPVERSION
Definition at line
187
of file
efr32bg21_smu.h
.
#define _SMU_LOCK_MASK 0x00FFFFFFUL |
Mask for SMU_LOCK
Definition at line
214
of file
efr32bg21_smu.h
.
#define _SMU_LOCK_RESETVALUE 0x00000000UL |
Default value for SMU_LOCK
Definition at line
213
of file
efr32bg21_smu.h
.
#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_LOCK
Definition at line
217
of file
efr32bg21_smu.h
.
#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL |
Bit mask for SMU_SMULOCKKEY
Definition at line
216
of file
efr32bg21_smu.h
.
#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 |
Shift value for SMU_SMULOCKKEY
Definition at line
215
of file
efr32bg21_smu.h
.
#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL |
Mode UNLOCK for SMU_LOCK
Definition at line
218
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_M33CTRL
Definition at line
291
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL |
Bit mask for SMU_LOCKNSMPU
Definition at line
290
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 |
Shift value for SMU_LOCKNSMPU
Definition at line
289
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_M33CTRL
Definition at line
281
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL |
Bit mask for SMU_LOCKNSVTOR
Definition at line
280
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 |
Shift value for SMU_LOCKNSVTOR
Definition at line
279
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_M33CTRL
Definition at line
296
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL |
Bit mask for SMU_LOCKSAU
Definition at line
295
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 |
Shift value for SMU_LOCKSAU
Definition at line
294
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_M33CTRL
Definition at line
286
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL |
Bit mask for SMU_LOCKSMPU
Definition at line
285
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 |
Shift value for SMU_LOCKSMPU
Definition at line
284
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_M33CTRL
Definition at line
276
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL |
Bit mask for SMU_LOCKSVTAIRCR
Definition at line
275
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 |
Shift value for SMU_LOCKSVTAIRCR
Definition at line
274
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_MASK 0x0000001FUL |
Mask for SMU_M33CTRL
Definition at line
272
of file
efr32bg21_smu.h
.
#define _SMU_M33CTRL_RESETVALUE 0x00000000UL |
Default value for SMU_M33CTRL
Definition at line
271
of file
efr32bg21_smu.h
.
#define _SMU_PPUFS_MASK 0x000000FFUL |
Mask for SMU_PPUFS
Definition at line
767
of file
efr32bg21_smu.h
.
#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUFS
Definition at line
770
of file
efr32bg21_smu.h
.
#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL |
Bit mask for SMU_PPUFSPERIPHID
Definition at line
769
of file
efr32bg21_smu.h
.
#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 |
Shift value for SMU_PPUFSPERIPHID
Definition at line
768
of file
efr32bg21_smu.h
.
#define _SMU_PPUFS_RESETVALUE 0x00000000UL |
Default value for SMU_PPUFS
Definition at line
766
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
440
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_BURAM_MASK 0x10000000UL |
Bit mask for SMU_BURAM
Definition at line
439
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_BURAM_SHIFT 28 |
Shift value for SMU_BURAM
Definition at line
438
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
415
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_BURTC_MASK 0x800000UL |
Bit mask for SMU_BURTC
Definition at line
414
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_BURTC_SHIFT 23 |
Shift value for SMU_BURTC
Definition at line
413
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
425
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x2000000UL |
Bit mask for SMU_CHIPTESTCTRL
Definition at line
424
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 25 |
Shift value for SMU_CHIPTESTCTRL
Definition at line
423
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
310
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_CMU_MASK 0x4UL |
Bit mask for SMU_CMU
Definition at line
309
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_CMU_SHIFT 2 |
Shift value for SMU_CMU
Definition at line
308
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
330
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_DPLL0_MASK 0x40UL |
Bit mask for SMU_DPLL0
Definition at line
329
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_DPLL0_SHIFT 6 |
Shift value for SMU_DPLL0
Definition at line
328
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
305
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_EMU_MASK 0x2UL |
Bit mask for SMU_EMU
Definition at line
304
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_EMU_SHIFT 1 |
Shift value for SMU_EMU
Definition at line
303
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
325
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_FSRCO_MASK 0x20UL |
Bit mask for SMU_FSRCO
Definition at line
324
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_FSRCO_SHIFT 5 |
Shift value for SMU_FSRCO
Definition at line
323
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
450
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_GPCRC_MASK 0x40000000UL |
Bit mask for SMU_GPCRC
Definition at line
449
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_GPCRC_SHIFT 30 |
Shift value for SMU_GPCRC
Definition at line
448
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
365
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_GPIO_MASK 0x2000UL |
Bit mask for SMU_GPIO
Definition at line
364
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_GPIO_SHIFT 13 |
Shift value for SMU_GPIO
Definition at line
363
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
320
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL |
Bit mask for SMU_HFRCO0
Definition at line
319
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_HFRCO0_SHIFT 4 |
Shift value for SMU_HFRCO0
Definition at line
318
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
420
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_I2C1_MASK 0x1000000UL |
Bit mask for SMU_I2C1
Definition at line
419
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_I2C1_SHIFT 24 |
Shift value for SMU_I2C1
Definition at line
418
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
355
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_ICACHE0_MASK 0x800UL |
Bit mask for SMU_ICACHE0
Definition at line
354
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_ICACHE0_SHIFT 11 |
Shift value for SMU_ICACHE0
Definition at line
353
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_IFADCDEBUG_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
445
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_IFADCDEBUG_MASK 0x20000000UL |
Bit mask for SMU_IFADCDEBUG
Definition at line
444
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_IFADCDEBUG_SHIFT 29 |
Shift value for SMU_IFADCDEBUG
Definition at line
443
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_IMEM_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
350
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_IMEM_MASK 0x400UL |
Bit mask for SMU_IMEM
Definition at line
349
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_IMEM_SHIFT 10 |
Shift value for SMU_IMEM
Definition at line
348
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
370
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LDMA_MASK 0x4000UL |
Bit mask for SMU_LDMA
Definition at line
369
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LDMA_SHIFT 14 |
Shift value for SMU_LDMA
Definition at line
368
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
375
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x8000UL |
Bit mask for SMU_LDMAXBAR
Definition at line
374
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 15 |
Shift value for SMU_LDMAXBAR
Definition at line
373
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
340
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LFRCO_MASK 0x100UL |
Bit mask for SMU_LFRCO
Definition at line
339
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LFRCO_SHIFT 8 |
Shift value for SMU_LFRCO
Definition at line
338
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
335
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LFXO_MASK 0x80UL |
Bit mask for SMU_LFXO
Definition at line
334
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LFXO_SHIFT 7 |
Shift value for SMU_LFXO
Definition at line
333
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LVGD_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
430
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LVGD_MASK 0x4000000UL |
Bit mask for SMU_LVGD
Definition at line
429
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_LVGD_SHIFT 26 |
Shift value for SMU_LVGD
Definition at line
428
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_MASK 0xFFFFFFFEUL |
Mask for SMU_PPUPATD0
Definition at line
301
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_PRS0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
360
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_PRS0_MASK 0x1000UL |
Bit mask for SMU_PRS0
Definition at line
359
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_PRS0_SHIFT 12 |
Shift value for SMU_PRS0
Definition at line
358
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL |
Default value for SMU_PPUPATD0
Definition at line
300
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_RTCC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
455
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_RTCC_MASK 0x80000000UL |
Bit mask for SMU_RTCC
Definition at line
454
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_RTCC_SHIFT 31 |
Shift value for SMU_RTCC
Definition at line
453
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
435
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_SYSCFG_MASK 0x8000000UL |
Bit mask for SMU_SYSCFG
Definition at line
434
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_SYSCFG_SHIFT 27 |
Shift value for SMU_SYSCFG
Definition at line
433
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_SYXO0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
315
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_SYXO0_MASK 0x8UL |
Bit mask for SMU_SYXO0
Definition at line
314
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_SYXO0_SHIFT 3 |
Shift value for SMU_SYXO0
Definition at line
313
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
380
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER0_MASK 0x10000UL |
Bit mask for SMU_TIMER0
Definition at line
379
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER0_SHIFT 16 |
Shift value for SMU_TIMER0
Definition at line
378
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
385
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER1_MASK 0x20000UL |
Bit mask for SMU_TIMER1
Definition at line
384
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER1_SHIFT 17 |
Shift value for SMU_TIMER1
Definition at line
383
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
390
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER2_MASK 0x40000UL |
Bit mask for SMU_TIMER2
Definition at line
389
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER2_SHIFT 18 |
Shift value for SMU_TIMER2
Definition at line
388
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
395
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER3_MASK 0x80000UL |
Bit mask for SMU_TIMER3
Definition at line
394
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_TIMER3_SHIFT 19 |
Shift value for SMU_TIMER3
Definition at line
393
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
345
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL |
Bit mask for SMU_ULFRCO
Definition at line
344
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_ULFRCO_SHIFT 9 |
Shift value for SMU_ULFRCO
Definition at line
343
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
400
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART0_MASK 0x100000UL |
Bit mask for SMU_USART0
Definition at line
399
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART0_SHIFT 20 |
Shift value for SMU_USART0
Definition at line
398
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
405
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART1_MASK 0x200000UL |
Bit mask for SMU_USART1
Definition at line
404
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART1_SHIFT 21 |
Shift value for SMU_USART1
Definition at line
403
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART2_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD0
Definition at line
410
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART2_MASK 0x400000UL |
Bit mask for SMU_USART2
Definition at line
409
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD0_USART2_SHIFT 22 |
Shift value for SMU_USART2
Definition at line
408
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
474
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_ACMP0_MASK 0x4UL |
Bit mask for SMU_ACMP0
Definition at line
473
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_ACMP0_SHIFT 2 |
Shift value for SMU_ACMP0
Definition at line
472
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
479
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_ACMP1_MASK 0x8UL |
Bit mask for SMU_ACMP1
Definition at line
478
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_ACMP1_SHIFT 3 |
Shift value for SMU_ACMP1
Definition at line
477
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AES_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
509
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AES_MASK 0x200UL |
Bit mask for SMU_AES
Definition at line
508
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AES_SHIFT 9 |
Shift value for SMU_AES
Definition at line
507
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
524
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AHBRADIO_MASK 0x1000UL |
Bit mask for SMU_AHBRADIO
Definition at line
523
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AHBRADIO_SHIFT 12 |
Shift value for SMU_AHBRADIO
Definition at line
522
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
504
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AMUXCP0_MASK 0x100UL |
Bit mask for SMU_AMUXCP0
Definition at line
503
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_AMUXCP0_SHIFT 8 |
Shift value for SMU_AMUXCP0
Definition at line
502
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_BUFC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
514
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_BUFC_MASK 0x400UL |
Bit mask for SMU_BUFC
Definition at line
513
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_BUFC_SHIFT 10 |
Shift value for SMU_BUFC
Definition at line
512
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
489
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_HFRCO1_MASK 0x20UL |
Bit mask for SMU_HFRCO1
Definition at line
488
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_HFRCO1_SHIFT 5 |
Shift value for SMU_HFRCO1
Definition at line
487
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
484
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_I2C0_MASK 0x10UL |
Bit mask for SMU_I2C0
Definition at line
483
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_I2C0_SHIFT 4 |
Shift value for SMU_I2C0
Definition at line
482
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
469
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_IADC0_MASK 0x2UL |
Bit mask for SMU_IADC0
Definition at line
468
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_IADC0_SHIFT 1 |
Shift value for SMU_IADC0
Definition at line
467
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_LETIMER_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
464
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_LETIMER_MASK 0x1UL |
Bit mask for SMU_LETIMER
Definition at line
463
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_LETIMER_SHIFT 0 |
Shift value for SMU_LETIMER
Definition at line
462
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_MASK 0x00003FFFUL |
Mask for SMU_PPUPATD1
Definition at line
460
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL |
Default value for SMU_PPUPATD1
Definition at line
459
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
529
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x2000UL |
Bit mask for SMU_SEMAILBOX
Definition at line
528
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 13 |
Shift value for SMU_SEMAILBOX
Definition at line
527
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
519
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_SMU_MASK 0x800UL |
Bit mask for SMU_SMU
Definition at line
518
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_SMU_SHIFT 11 |
Shift value for SMU_SMU
Definition at line
517
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
494
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_WDOG0_MASK 0x40UL |
Bit mask for SMU_WDOG0
Definition at line
493
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_WDOG0_SHIFT 6 |
Shift value for SMU_WDOG0
Definition at line
492
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUPATD1
Definition at line
499
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_WDOG1_MASK 0x80UL |
Bit mask for SMU_WDOG1
Definition at line
498
of file
efr32bg21_smu.h
.
#define _SMU_PPUPATD1_WDOG1_SHIFT 7 |
Shift value for SMU_WDOG1
Definition at line
497
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
673
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_BURAM_MASK 0x10000000UL |
Bit mask for SMU_BURAM
Definition at line
672
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_BURAM_SHIFT 28 |
Shift value for SMU_BURAM
Definition at line
671
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
648
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_BURTC_MASK 0x800000UL |
Bit mask for SMU_BURTC
Definition at line
647
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_BURTC_SHIFT 23 |
Shift value for SMU_BURTC
Definition at line
646
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
658
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x2000000UL |
Bit mask for SMU_CHIPTESTCTRL
Definition at line
657
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 25 |
Shift value for SMU_CHIPTESTCTRL
Definition at line
656
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
543
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_CMU_MASK 0x4UL |
Bit mask for SMU_CMU
Definition at line
542
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_CMU_SHIFT 2 |
Shift value for SMU_CMU
Definition at line
541
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
563
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_DPLL0_MASK 0x40UL |
Bit mask for SMU_DPLL0
Definition at line
562
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_DPLL0_SHIFT 6 |
Shift value for SMU_DPLL0
Definition at line
561
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
538
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_EMU_MASK 0x2UL |
Bit mask for SMU_EMU
Definition at line
537
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_EMU_SHIFT 1 |
Shift value for SMU_EMU
Definition at line
536
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
558
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_FSRCO_MASK 0x20UL |
Bit mask for SMU_FSRCO
Definition at line
557
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_FSRCO_SHIFT 5 |
Shift value for SMU_FSRCO
Definition at line
556
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
683
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_GPCRC_MASK 0x40000000UL |
Bit mask for SMU_GPCRC
Definition at line
682
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_GPCRC_SHIFT 30 |
Shift value for SMU_GPCRC
Definition at line
681
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
598
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_GPIO_MASK 0x2000UL |
Bit mask for SMU_GPIO
Definition at line
597
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_GPIO_SHIFT 13 |
Shift value for SMU_GPIO
Definition at line
596
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
553
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL |
Bit mask for SMU_HFRCO0
Definition at line
552
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_HFRCO0_SHIFT 4 |
Shift value for SMU_HFRCO0
Definition at line
551
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
653
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_I2C1_MASK 0x1000000UL |
Bit mask for SMU_I2C1
Definition at line
652
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_I2C1_SHIFT 24 |
Shift value for SMU_I2C1
Definition at line
651
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
588
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_ICACHE0_MASK 0x800UL |
Bit mask for SMU_ICACHE0
Definition at line
587
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_ICACHE0_SHIFT 11 |
Shift value for SMU_ICACHE0
Definition at line
586
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_IFADCDEBUG_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
678
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_IFADCDEBUG_MASK 0x20000000UL |
Bit mask for SMU_IFADCDEBUG
Definition at line
677
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_IFADCDEBUG_SHIFT 29 |
Shift value for SMU_IFADCDEBUG
Definition at line
676
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_IMEM_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
583
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_IMEM_MASK 0x400UL |
Bit mask for SMU_IMEM
Definition at line
582
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_IMEM_SHIFT 10 |
Shift value for SMU_IMEM
Definition at line
581
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
603
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LDMA_MASK 0x4000UL |
Bit mask for SMU_LDMA
Definition at line
602
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LDMA_SHIFT 14 |
Shift value for SMU_LDMA
Definition at line
601
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
608
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x8000UL |
Bit mask for SMU_LDMAXBAR
Definition at line
607
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 15 |
Shift value for SMU_LDMAXBAR
Definition at line
606
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
573
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LFRCO_MASK 0x100UL |
Bit mask for SMU_LFRCO
Definition at line
572
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LFRCO_SHIFT 8 |
Shift value for SMU_LFRCO
Definition at line
571
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
568
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LFXO_MASK 0x80UL |
Bit mask for SMU_LFXO
Definition at line
567
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LFXO_SHIFT 7 |
Shift value for SMU_LFXO
Definition at line
566
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LVGD_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
663
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LVGD_MASK 0x4000000UL |
Bit mask for SMU_LVGD
Definition at line
662
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_LVGD_SHIFT 26 |
Shift value for SMU_LVGD
Definition at line
661
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_MASK 0xFFFFFFFEUL |
Mask for SMU_PPUSATD0
Definition at line
534
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_PRS0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
593
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_PRS0_MASK 0x1000UL |
Bit mask for SMU_PRS0
Definition at line
592
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_PRS0_SHIFT 12 |
Shift value for SMU_PRS0
Definition at line
591
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_RESETVALUE 0x00000000UL |
Default value for SMU_PPUSATD0
Definition at line
533
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_RTCC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
688
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_RTCC_MASK 0x80000000UL |
Bit mask for SMU_RTCC
Definition at line
687
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_RTCC_SHIFT 31 |
Shift value for SMU_RTCC
Definition at line
686
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
668
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_SYSCFG_MASK 0x8000000UL |
Bit mask for SMU_SYSCFG
Definition at line
667
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_SYSCFG_SHIFT 27 |
Shift value for SMU_SYSCFG
Definition at line
666
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_SYXO0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
548
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_SYXO0_MASK 0x8UL |
Bit mask for SMU_SYXO0
Definition at line
547
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_SYXO0_SHIFT 3 |
Shift value for SMU_SYXO0
Definition at line
546
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
613
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER0_MASK 0x10000UL |
Bit mask for SMU_TIMER0
Definition at line
612
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER0_SHIFT 16 |
Shift value for SMU_TIMER0
Definition at line
611
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
618
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER1_MASK 0x20000UL |
Bit mask for SMU_TIMER1
Definition at line
617
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER1_SHIFT 17 |
Shift value for SMU_TIMER1
Definition at line
616
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
623
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER2_MASK 0x40000UL |
Bit mask for SMU_TIMER2
Definition at line
622
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER2_SHIFT 18 |
Shift value for SMU_TIMER2
Definition at line
621
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
628
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER3_MASK 0x80000UL |
Bit mask for SMU_TIMER3
Definition at line
627
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_TIMER3_SHIFT 19 |
Shift value for SMU_TIMER3
Definition at line
626
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
578
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL |
Bit mask for SMU_ULFRCO
Definition at line
577
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_ULFRCO_SHIFT 9 |
Shift value for SMU_ULFRCO
Definition at line
576
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
633
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART0_MASK 0x100000UL |
Bit mask for SMU_USART0
Definition at line
632
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART0_SHIFT 20 |
Shift value for SMU_USART0
Definition at line
631
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
638
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART1_MASK 0x200000UL |
Bit mask for SMU_USART1
Definition at line
637
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART1_SHIFT 21 |
Shift value for SMU_USART1
Definition at line
636
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART2_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD0
Definition at line
643
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART2_MASK 0x400000UL |
Bit mask for SMU_USART2
Definition at line
642
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD0_USART2_SHIFT 22 |
Shift value for SMU_USART2
Definition at line
641
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
707
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_ACMP0_MASK 0x4UL |
Bit mask for SMU_ACMP0
Definition at line
706
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_ACMP0_SHIFT 2 |
Shift value for SMU_ACMP0
Definition at line
705
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
712
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_ACMP1_MASK 0x8UL |
Bit mask for SMU_ACMP1
Definition at line
711
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_ACMP1_SHIFT 3 |
Shift value for SMU_ACMP1
Definition at line
710
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AES_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
742
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AES_MASK 0x200UL |
Bit mask for SMU_AES
Definition at line
741
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AES_SHIFT 9 |
Shift value for SMU_AES
Definition at line
740
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
757
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AHBRADIO_MASK 0x1000UL |
Bit mask for SMU_AHBRADIO
Definition at line
756
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AHBRADIO_SHIFT 12 |
Shift value for SMU_AHBRADIO
Definition at line
755
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
737
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AMUXCP0_MASK 0x100UL |
Bit mask for SMU_AMUXCP0
Definition at line
736
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_AMUXCP0_SHIFT 8 |
Shift value for SMU_AMUXCP0
Definition at line
735
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_BUFC_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
747
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_BUFC_MASK 0x400UL |
Bit mask for SMU_BUFC
Definition at line
746
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_BUFC_SHIFT 10 |
Shift value for SMU_BUFC
Definition at line
745
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
722
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_HFRCO1_MASK 0x20UL |
Bit mask for SMU_HFRCO1
Definition at line
721
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_HFRCO1_SHIFT 5 |
Shift value for SMU_HFRCO1
Definition at line
720
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
717
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_I2C0_MASK 0x10UL |
Bit mask for SMU_I2C0
Definition at line
716
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_I2C0_SHIFT 4 |
Shift value for SMU_I2C0
Definition at line
715
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
702
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_IADC0_MASK 0x2UL |
Bit mask for SMU_IADC0
Definition at line
701
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_IADC0_SHIFT 1 |
Shift value for SMU_IADC0
Definition at line
700
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_LETIMER_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
697
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_LETIMER_MASK 0x1UL |
Bit mask for SMU_LETIMER
Definition at line
696
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_LETIMER_SHIFT 0 |
Shift value for SMU_LETIMER
Definition at line
695
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_MASK 0x00003FFFUL |
Mask for SMU_PPUSATD1
Definition at line
693
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_RESETVALUE 0x00000000UL |
Default value for SMU_PPUSATD1
Definition at line
692
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
762
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x2000UL |
Bit mask for SMU_SEMAILBOX
Definition at line
761
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 13 |
Shift value for SMU_SEMAILBOX
Definition at line
760
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
752
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_SMU_MASK 0x800UL |
Bit mask for SMU_SMU
Definition at line
751
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_SMU_SHIFT 11 |
Shift value for SMU_SMU
Definition at line
750
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
727
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_WDOG0_MASK 0x40UL |
Bit mask for SMU_WDOG0
Definition at line
726
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_WDOG0_SHIFT 6 |
Shift value for SMU_WDOG0
Definition at line
725
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_PPUSATD1
Definition at line
732
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_WDOG1_MASK 0x80UL |
Bit mask for SMU_WDOG1
Definition at line
731
of file
efr32bg21_smu.h
.
#define _SMU_PPUSATD1_WDOG1_SHIFT 7 |
Shift value for SMU_WDOG1
Definition at line
730
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_MASK 0x00000003UL |
Mask for SMU_STATUS
Definition at line
196
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_RESETVALUE 0x00000000UL |
Default value for SMU_STATUS
Definition at line
195
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_STATUS
Definition at line
200
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL |
Mode LOCKED for SMU_STATUS
Definition at line
202
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMULOCK_MASK 0x1UL |
Bit mask for SMU_SMULOCK
Definition at line
199
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMULOCK_SHIFT 0 |
Shift value for SMU_SMULOCK
Definition at line
198
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL |
Mode UNLOCKED for SMU_STATUS
Definition at line
201
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL |
Mode DEFAULT for SMU_STATUS
Definition at line
209
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL |
Bit mask for SMU_SMUPRGERR
Definition at line
208
of file
efr32bg21_smu.h
.
#define _SMU_STATUS_SMUPRGERR_SHIFT 1 |
Shift value for SMU_SMUPRGERR
Definition at line
207
of file
efr32bg21_smu.h
.
#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT ( _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_BMPUFS
Definition at line
847
of file
efr32bg21_smu.h
.
#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT ( _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_BMPUFSADDR
Definition at line
855
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_BUFC (0x1UL << 2) |
RADIO BUFFER controller privileged mode
Definition at line
786
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_BUFC_DEFAULT ( _SMU_BMPUPATD0_BUFC_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_BMPUPATD0
Definition at line
790
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_LDMA (0x1UL << 4) |
MCU LDMA privileged mode
Definition at line
796
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_LDMA_DEFAULT ( _SMU_BMPUPATD0_LDMA_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_BMPUPATD0
Definition at line
800
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) |
RADIO AES DMA privileged mode
Definition at line
776
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_RADIOAES_DEFAULT ( _SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_BMPUPATD0
Definition at line
780
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_RADIOIFADCDEBUG (0x1UL << 3) |
RADIO IFADC debug privileged mode
Definition at line
791
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT ( _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_BMPUPATD0
Definition at line
795
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) |
RADIO subsystem masters privileged mode
Definition at line
781
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT ( _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_BMPUPATD0
Definition at line
785
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_SEDMA (0x1UL << 5) |
SE mailbox DMA privileged mode
Definition at line
801
of file
efr32bg21_smu.h
.
#define SMU_BMPUPATD0_SEDMA_DEFAULT ( _SMU_BMPUPATD0_SEDMA_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_BMPUPATD0
Definition at line
805
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_BUFC (0x1UL << 2) |
RADIO BUFFER controller secure mode
Definition at line
820
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_BUFC_DEFAULT ( _SMU_BMPUSATD0_BUFC_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_BMPUSATD0
Definition at line
824
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_LDMA (0x1UL << 4) |
MCU LDMA secure mode
Definition at line
830
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_LDMA_DEFAULT ( _SMU_BMPUSATD0_LDMA_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_BMPUSATD0
Definition at line
834
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) |
RADIO AES DMA secure mode
Definition at line
810
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_RADIOAES_DEFAULT ( _SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_BMPUSATD0
Definition at line
814
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_RADIOIFADCDEBUG (0x1UL << 3) |
RADIO IFADC debug secure mode
Definition at line
825
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT ( _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_BMPUSATD0
Definition at line
829
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) |
RADIO subsystem masters secure mode
Definition at line
815
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT ( _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_BMPUSATD0
Definition at line
819
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_SEDMA (0x1UL << 5) |
MCU to SE mailbox DMA secure mode
Definition at line
835
of file
efr32bg21_smu.h
.
#define SMU_BMPUSATD0_SEDMA_DEFAULT ( _SMU_BMPUSATD0_SEDMA_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_BMPUSATD0
Definition at line
839
of file
efr32bg21_smu.h
.
#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT ( _SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_ESAUMRB01
Definition at line
881
of file
efr32bg21_smu.h
.
#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT ( _SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_ESAUMRB12
Definition at line
889
of file
efr32bg21_smu.h
.
#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT ( _SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_ESAUMRB45
Definition at line
897
of file
efr32bg21_smu.h
.
#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT ( _SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_ESAUMRB56
Definition at line
905
of file
efr32bg21_smu.h
.
#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) |
Region 3 Non-Secure
Definition at line
860
of file
efr32bg21_smu.h
.
#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT ( _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_ESAURTYPES0
Definition at line
864
of file
efr32bg21_smu.h
.
#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) |
Region 11 Non-Secure
Definition at line
869
of file
efr32bg21_smu.h
.
#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT ( _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_ESAURTYPES1
Definition at line
873
of file
efr32bg21_smu.h
.
#define SMU_IEN_BMPUSEC (0x1UL << 17) |
BMPU Security Interrupt Flag
Definition at line
264
of file
efr32bg21_smu.h
.
#define SMU_IEN_BMPUSEC_DEFAULT ( _SMU_IEN_BMPUSEC_DEFAULT << 17) |
Shifted mode DEFAULT for SMU_IEN
Definition at line
268
of file
efr32bg21_smu.h
.
#define SMU_IEN_PPUINST (0x1UL << 2) |
PPU Instruction Interrupt Flag
Definition at line
254
of file
efr32bg21_smu.h
.
#define SMU_IEN_PPUINST_DEFAULT ( _SMU_IEN_PPUINST_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_IEN
Definition at line
258
of file
efr32bg21_smu.h
.
#define SMU_IEN_PPUPRIV (0x1UL << 0) |
PPU Privilege Interrupt Flag
Definition at line
249
of file
efr32bg21_smu.h
.
#define SMU_IEN_PPUPRIV_DEFAULT ( _SMU_IEN_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IEN
Definition at line
253
of file
efr32bg21_smu.h
.
#define SMU_IEN_PPUSEC (0x1UL << 16) |
PPU Security Interrupt Flag
Definition at line
259
of file
efr32bg21_smu.h
.
#define SMU_IEN_PPUSEC_DEFAULT ( _SMU_IEN_PPUSEC_DEFAULT << 16) |
Shifted mode DEFAULT for SMU_IEN
Definition at line
263
of file
efr32bg21_smu.h
.
#define SMU_IF_BMPUSEC (0x1UL << 17) |
BMPU Security Interrupt Flag
Definition at line
240
of file
efr32bg21_smu.h
.
#define SMU_IF_BMPUSEC_DEFAULT ( _SMU_IF_BMPUSEC_DEFAULT << 17) |
Shifted mode DEFAULT for SMU_IF
Definition at line
244
of file
efr32bg21_smu.h
.
#define SMU_IF_PPUINST (0x1UL << 2) |
PPU Instruction Interrupt Flag
Definition at line
230
of file
efr32bg21_smu.h
.
#define SMU_IF_PPUINST_DEFAULT ( _SMU_IF_PPUINST_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_IF
Definition at line
234
of file
efr32bg21_smu.h
.
#define SMU_IF_PPUPRIV (0x1UL << 0) |
PPU Privilege Interrupt Flag
Definition at line
225
of file
efr32bg21_smu.h
.
#define SMU_IF_PPUPRIV_DEFAULT ( _SMU_IF_PPUPRIV_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IF
Definition at line
229
of file
efr32bg21_smu.h
.
#define SMU_IF_PPUSEC (0x1UL << 16) |
PPU Security Interrupt Flag
Definition at line
235
of file
efr32bg21_smu.h
.
#define SMU_IF_PPUSEC_DEFAULT ( _SMU_IF_PPUSEC_DEFAULT << 16) |
Shifted mode DEFAULT for SMU_IF
Definition at line
239
of file
efr32bg21_smu.h
.
#define SMU_IPVERSION_IPVERSION_DEFAULT ( _SMU_IPVERSION_IPVERSION_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_IPVERSION
Definition at line
192
of file
efr32bg21_smu.h
.
#define SMU_LOCK_SMULOCKKEY_DEFAULT ( _SMU_LOCK_SMULOCKKEY_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_LOCK
Definition at line
219
of file
efr32bg21_smu.h
.
#define SMU_LOCK_SMULOCKKEY_UNLOCK ( _SMU_LOCK_SMULOCKKEY_UNLOCK << 0) |
Shifted mode UNLOCK for SMU_LOCK
Definition at line
220
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) |
New BitField
Definition at line
288
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKNSMPU_DEFAULT ( _SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_M33CTRL
Definition at line
292
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) |
New BitField
Definition at line
278
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT ( _SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_M33CTRL
Definition at line
282
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) |
New BitField
Definition at line
293
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKSAU_DEFAULT ( _SMU_M33CTRL_LOCKSAU_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_M33CTRL
Definition at line
297
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) |
New BitField
Definition at line
283
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKSMPU_DEFAULT ( _SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_M33CTRL
Definition at line
287
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) |
New BitField
Definition at line
273
of file
efr32bg21_smu.h
.
#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT ( _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_M33CTRL
Definition at line
277
of file
efr32bg21_smu.h
.
#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT ( _SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUFS
Definition at line
771
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_BURAM (0x1UL << 28) |
BURAM Privileged Access
Definition at line
437
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_BURAM_DEFAULT ( _SMU_PPUPATD0_BURAM_DEFAULT << 28) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
441
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_BURTC (0x1UL << 23) |
BURTC Privileged Access
Definition at line
412
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_BURTC_DEFAULT ( _SMU_PPUPATD0_BURTC_DEFAULT << 23) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
416
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 25) |
CHIPTESTCTRL Privileged Access
Definition at line
422
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT ( _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 25) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
426
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_CMU (0x1UL << 2) |
CMU Privileged Access
Definition at line
307
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_CMU_DEFAULT ( _SMU_PPUPATD0_CMU_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
311
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_DPLL0 (0x1UL << 6) |
DPLL0 Privileged Access
Definition at line
327
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_DPLL0_DEFAULT ( _SMU_PPUPATD0_DPLL0_DEFAULT << 6) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
331
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_EMU (0x1UL << 1) |
EMU Privileged Access
Definition at line
302
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_EMU_DEFAULT ( _SMU_PPUPATD0_EMU_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
306
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_FSRCO (0x1UL << 5) |
FSRCO Privileged Access
Definition at line
322
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_FSRCO_DEFAULT ( _SMU_PPUPATD0_FSRCO_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
326
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_GPCRC (0x1UL << 30) |
GPCRC Privileged Access
Definition at line
447
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_GPCRC_DEFAULT ( _SMU_PPUPATD0_GPCRC_DEFAULT << 30) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
451
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_GPIO (0x1UL << 13) |
GPIO Privileged Access
Definition at line
362
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_GPIO_DEFAULT ( _SMU_PPUPATD0_GPIO_DEFAULT << 13) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
366
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) |
HFRCO0 Privileged Access
Definition at line
317
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_HFRCO0_DEFAULT ( _SMU_PPUPATD0_HFRCO0_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
321
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_I2C1 (0x1UL << 24) |
I2C1 Privileged Access
Definition at line
417
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_I2C1_DEFAULT ( _SMU_PPUPATD0_I2C1_DEFAULT << 24) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
421
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_ICACHE0 (0x1UL << 11) |
ICACHE0 Privileged Access
Definition at line
352
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_ICACHE0_DEFAULT ( _SMU_PPUPATD0_ICACHE0_DEFAULT << 11) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
356
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_IFADCDEBUG (0x1UL << 29) |
IFADCDEBUG Privileged Access
Definition at line
442
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_IFADCDEBUG_DEFAULT ( _SMU_PPUPATD0_IFADCDEBUG_DEFAULT << 29) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
446
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_IMEM (0x1UL << 10) |
IMEM Privileged Access
Definition at line
347
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_IMEM_DEFAULT ( _SMU_PPUPATD0_IMEM_DEFAULT << 10) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
351
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LDMA (0x1UL << 14) |
LDMA Privileged Access
Definition at line
367
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LDMA_DEFAULT ( _SMU_PPUPATD0_LDMA_DEFAULT << 14) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
371
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 15) |
LDMAXBAR Privileged Access
Definition at line
372
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LDMAXBAR_DEFAULT ( _SMU_PPUPATD0_LDMAXBAR_DEFAULT << 15) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
376
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LFRCO (0x1UL << 8) |
LFRCO Privileged Access
Definition at line
337
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LFRCO_DEFAULT ( _SMU_PPUPATD0_LFRCO_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
341
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LFXO (0x1UL << 7) |
LFXO Privileged Access
Definition at line
332
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LFXO_DEFAULT ( _SMU_PPUPATD0_LFXO_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
336
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LVGD (0x1UL << 26) |
LVGD Privileged Access
Definition at line
427
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_LVGD_DEFAULT ( _SMU_PPUPATD0_LVGD_DEFAULT << 26) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
431
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_PRS0 (0x1UL << 12) |
PRS0 Privileged Access
Definition at line
357
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_PRS0_DEFAULT ( _SMU_PPUPATD0_PRS0_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
361
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_RTCC (0x1UL << 31) |
RTCC Privileged Access
Definition at line
452
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_RTCC_DEFAULT ( _SMU_PPUPATD0_RTCC_DEFAULT << 31) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
456
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_SYSCFG (0x1UL << 27) |
SYSCFG Privileged Access
Definition at line
432
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_SYSCFG_DEFAULT ( _SMU_PPUPATD0_SYSCFG_DEFAULT << 27) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
436
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_SYXO0 (0x1UL << 3) |
SYXO0 Privileged Access
Definition at line
312
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_SYXO0_DEFAULT ( _SMU_PPUPATD0_SYXO0_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
316
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER0 (0x1UL << 16) |
TIMER0 Privileged Access
Definition at line
377
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER0_DEFAULT ( _SMU_PPUPATD0_TIMER0_DEFAULT << 16) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
381
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER1 (0x1UL << 17) |
TIMER1 Privileged Access
Definition at line
382
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER1_DEFAULT ( _SMU_PPUPATD0_TIMER1_DEFAULT << 17) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
386
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER2 (0x1UL << 18) |
TIMER2 Privileged Access
Definition at line
387
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER2_DEFAULT ( _SMU_PPUPATD0_TIMER2_DEFAULT << 18) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
391
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER3 (0x1UL << 19) |
TIMER3 Privileged Access
Definition at line
392
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_TIMER3_DEFAULT ( _SMU_PPUPATD0_TIMER3_DEFAULT << 19) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
396
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_ULFRCO (0x1UL << 9) |
ULFRCO Privileged Access
Definition at line
342
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_ULFRCO_DEFAULT ( _SMU_PPUPATD0_ULFRCO_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
346
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_USART0 (0x1UL << 20) |
USART0 Privileged Access
Definition at line
397
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_USART0_DEFAULT ( _SMU_PPUPATD0_USART0_DEFAULT << 20) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
401
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_USART1 (0x1UL << 21) |
USART1 Privileged Access
Definition at line
402
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_USART1_DEFAULT ( _SMU_PPUPATD0_USART1_DEFAULT << 21) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
406
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_USART2 (0x1UL << 22) |
USART2 Privileged Access
Definition at line
407
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD0_USART2_DEFAULT ( _SMU_PPUPATD0_USART2_DEFAULT << 22) |
Shifted mode DEFAULT for SMU_PPUPATD0
Definition at line
411
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_ACMP0 (0x1UL << 2) |
ACMP0 Privileged Access
Definition at line
471
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_ACMP0_DEFAULT ( _SMU_PPUPATD1_ACMP0_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
475
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_ACMP1 (0x1UL << 3) |
ACMP1 Privileged Access
Definition at line
476
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_ACMP1_DEFAULT ( _SMU_PPUPATD1_ACMP1_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
480
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_AES (0x1UL << 9) |
AES Privileged Access
Definition at line
506
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_AES_DEFAULT ( _SMU_PPUPATD1_AES_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
510
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_AHBRADIO (0x1UL << 12) |
AHBRADIO Privileged Access
Definition at line
521
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_AHBRADIO_DEFAULT ( _SMU_PPUPATD1_AHBRADIO_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
525
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 8) |
AMUXCP0 Privileged Access
Definition at line
501
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_AMUXCP0_DEFAULT ( _SMU_PPUPATD1_AMUXCP0_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
505
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_BUFC (0x1UL << 10) |
BUFC Privileged Access
Definition at line
511
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_BUFC_DEFAULT ( _SMU_PPUPATD1_BUFC_DEFAULT << 10) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
515
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_HFRCO1 (0x1UL << 5) |
HFRCO1 Privileged Access
Definition at line
486
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_HFRCO1_DEFAULT ( _SMU_PPUPATD1_HFRCO1_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
490
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_I2C0 (0x1UL << 4) |
I2C0 Privileged Access
Definition at line
481
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_I2C0_DEFAULT ( _SMU_PPUPATD1_I2C0_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
485
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_IADC0 (0x1UL << 1) |
IADC0 Privileged Access
Definition at line
466
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_IADC0_DEFAULT ( _SMU_PPUPATD1_IADC0_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
470
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_LETIMER (0x1UL << 0) |
LETIMER Privileged Access
Definition at line
461
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_LETIMER_DEFAULT ( _SMU_PPUPATD1_LETIMER_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
465
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 13) |
SE MAILBOX Privileged Access
Definition at line
526
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_SEMAILBOX_DEFAULT ( _SMU_PPUPATD1_SEMAILBOX_DEFAULT << 13) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
530
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_SMU (0x1UL << 11) |
SMU Privileged Access
Definition at line
516
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_SMU_DEFAULT ( _SMU_PPUPATD1_SMU_DEFAULT << 11) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
520
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_WDOG0 (0x1UL << 6) |
WDOG0 Privileged Access
Definition at line
491
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_WDOG0_DEFAULT ( _SMU_PPUPATD1_WDOG0_DEFAULT << 6) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
495
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_WDOG1 (0x1UL << 7) |
WDOG1 Privileged Access
Definition at line
496
of file
efr32bg21_smu.h
.
#define SMU_PPUPATD1_WDOG1_DEFAULT ( _SMU_PPUPATD1_WDOG1_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUPATD1
Definition at line
500
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_BURAM (0x1UL << 28) |
BURAM Secure Access
Definition at line
670
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_BURAM_DEFAULT ( _SMU_PPUSATD0_BURAM_DEFAULT << 28) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
674
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_BURTC (0x1UL << 23) |
BURTC Secure Access
Definition at line
645
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_BURTC_DEFAULT ( _SMU_PPUSATD0_BURTC_DEFAULT << 23) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
649
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 25) |
CHIPTESTCTRL Secure Access
Definition at line
655
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT ( _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 25) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
659
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_CMU (0x1UL << 2) |
CMU Secure Access
Definition at line
540
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_CMU_DEFAULT ( _SMU_PPUSATD0_CMU_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
544
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_DPLL0 (0x1UL << 6) |
DPLL0 Secure Access
Definition at line
560
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_DPLL0_DEFAULT ( _SMU_PPUSATD0_DPLL0_DEFAULT << 6) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
564
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_EMU (0x1UL << 1) |
EMU Secure Access
Definition at line
535
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_EMU_DEFAULT ( _SMU_PPUSATD0_EMU_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
539
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_FSRCO (0x1UL << 5) |
FSRCO Secure Access
Definition at line
555
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_FSRCO_DEFAULT ( _SMU_PPUSATD0_FSRCO_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
559
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_GPCRC (0x1UL << 30) |
GPCRC Secure Access
Definition at line
680
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_GPCRC_DEFAULT ( _SMU_PPUSATD0_GPCRC_DEFAULT << 30) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
684
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_GPIO (0x1UL << 13) |
GPIO Secure Access
Definition at line
595
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_GPIO_DEFAULT ( _SMU_PPUSATD0_GPIO_DEFAULT << 13) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
599
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) |
HFRCO0 Secure Access
Definition at line
550
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_HFRCO0_DEFAULT ( _SMU_PPUSATD0_HFRCO0_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
554
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_I2C1 (0x1UL << 24) |
I2C1 Secure Access
Definition at line
650
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_I2C1_DEFAULT ( _SMU_PPUSATD0_I2C1_DEFAULT << 24) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
654
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_ICACHE0 (0x1UL << 11) |
ICACHE0 Secure Access
Definition at line
585
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_ICACHE0_DEFAULT ( _SMU_PPUSATD0_ICACHE0_DEFAULT << 11) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
589
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_IFADCDEBUG (0x1UL << 29) |
IFADCDEBUG Secure Access
Definition at line
675
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_IFADCDEBUG_DEFAULT ( _SMU_PPUSATD0_IFADCDEBUG_DEFAULT << 29) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
679
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_IMEM (0x1UL << 10) |
IMEM Secure Access
Definition at line
580
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_IMEM_DEFAULT ( _SMU_PPUSATD0_IMEM_DEFAULT << 10) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
584
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LDMA (0x1UL << 14) |
LDMA Secure Access
Definition at line
600
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LDMA_DEFAULT ( _SMU_PPUSATD0_LDMA_DEFAULT << 14) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
604
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 15) |
LDMAXBAR Secure Access
Definition at line
605
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LDMAXBAR_DEFAULT ( _SMU_PPUSATD0_LDMAXBAR_DEFAULT << 15) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
609
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LFRCO (0x1UL << 8) |
LFRCO Secure Access
Definition at line
570
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LFRCO_DEFAULT ( _SMU_PPUSATD0_LFRCO_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
574
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LFXO (0x1UL << 7) |
LFXO Secure Access
Definition at line
565
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LFXO_DEFAULT ( _SMU_PPUSATD0_LFXO_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
569
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LVGD (0x1UL << 26) |
LVGD Secure Access
Definition at line
660
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_LVGD_DEFAULT ( _SMU_PPUSATD0_LVGD_DEFAULT << 26) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
664
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_PRS0 (0x1UL << 12) |
PRS0 Secure Access
Definition at line
590
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_PRS0_DEFAULT ( _SMU_PPUSATD0_PRS0_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
594
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_RTCC (0x1UL << 31) |
RTCC Secure Access
Definition at line
685
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_RTCC_DEFAULT ( _SMU_PPUSATD0_RTCC_DEFAULT << 31) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
689
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_SYSCFG (0x1UL << 27) |
SYSCFG Secure Access
Definition at line
665
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_SYSCFG_DEFAULT ( _SMU_PPUSATD0_SYSCFG_DEFAULT << 27) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
669
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_SYXO0 (0x1UL << 3) |
SYXO0 Secure Access
Definition at line
545
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_SYXO0_DEFAULT ( _SMU_PPUSATD0_SYXO0_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
549
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER0 (0x1UL << 16) |
TIMER0 Secure Access
Definition at line
610
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER0_DEFAULT ( _SMU_PPUSATD0_TIMER0_DEFAULT << 16) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
614
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER1 (0x1UL << 17) |
TIMER1 Secure Access
Definition at line
615
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER1_DEFAULT ( _SMU_PPUSATD0_TIMER1_DEFAULT << 17) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
619
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER2 (0x1UL << 18) |
TIMER2 Secure Access
Definition at line
620
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER2_DEFAULT ( _SMU_PPUSATD0_TIMER2_DEFAULT << 18) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
624
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER3 (0x1UL << 19) |
TIMER3 Secure Access
Definition at line
625
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_TIMER3_DEFAULT ( _SMU_PPUSATD0_TIMER3_DEFAULT << 19) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
629
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_ULFRCO (0x1UL << 9) |
ULFRCO Secure Access
Definition at line
575
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_ULFRCO_DEFAULT ( _SMU_PPUSATD0_ULFRCO_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
579
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_USART0 (0x1UL << 20) |
USART0 Secure Access
Definition at line
630
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_USART0_DEFAULT ( _SMU_PPUSATD0_USART0_DEFAULT << 20) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
634
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_USART1 (0x1UL << 21) |
USART1 Secure Access
Definition at line
635
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_USART1_DEFAULT ( _SMU_PPUSATD0_USART1_DEFAULT << 21) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
639
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_USART2 (0x1UL << 22) |
USART2 Secure Access
Definition at line
640
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD0_USART2_DEFAULT ( _SMU_PPUSATD0_USART2_DEFAULT << 22) |
Shifted mode DEFAULT for SMU_PPUSATD0
Definition at line
644
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_ACMP0 (0x1UL << 2) |
ACMP0 Secure Access
Definition at line
704
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_ACMP0_DEFAULT ( _SMU_PPUSATD1_ACMP0_DEFAULT << 2) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
708
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_ACMP1 (0x1UL << 3) |
ACMP1 Secure Access
Definition at line
709
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_ACMP1_DEFAULT ( _SMU_PPUSATD1_ACMP1_DEFAULT << 3) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
713
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_AES (0x1UL << 9) |
AES Secure Access
Definition at line
739
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_AES_DEFAULT ( _SMU_PPUSATD1_AES_DEFAULT << 9) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
743
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_AHBRADIO (0x1UL << 12) |
AHBRADIO Secure Access
Definition at line
754
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_AHBRADIO_DEFAULT ( _SMU_PPUSATD1_AHBRADIO_DEFAULT << 12) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
758
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 8) |
AMUXCP0 Secure Access
Definition at line
734
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_AMUXCP0_DEFAULT ( _SMU_PPUSATD1_AMUXCP0_DEFAULT << 8) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
738
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_BUFC (0x1UL << 10) |
BUFC Secure Access
Definition at line
744
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_BUFC_DEFAULT ( _SMU_PPUSATD1_BUFC_DEFAULT << 10) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
748
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_HFRCO1 (0x1UL << 5) |
HFRCO1 Secure Access
Definition at line
719
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_HFRCO1_DEFAULT ( _SMU_PPUSATD1_HFRCO1_DEFAULT << 5) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
723
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_I2C0 (0x1UL << 4) |
I2C0 Secure Access
Definition at line
714
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_I2C0_DEFAULT ( _SMU_PPUSATD1_I2C0_DEFAULT << 4) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
718
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_IADC0 (0x1UL << 1) |
IADC0 Secure Access
Definition at line
699
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_IADC0_DEFAULT ( _SMU_PPUSATD1_IADC0_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
703
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_LETIMER (0x1UL << 0) |
LETIMER Secure Access
Definition at line
694
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_LETIMER_DEFAULT ( _SMU_PPUSATD1_LETIMER_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
698
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 13) |
SE MAILBOX Secure Access
Definition at line
759
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_SEMAILBOX_DEFAULT ( _SMU_PPUSATD1_SEMAILBOX_DEFAULT << 13) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
763
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_SMU (0x1UL << 11) |
SMU Secure Access
Definition at line
749
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_SMU_DEFAULT ( _SMU_PPUSATD1_SMU_DEFAULT << 11) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
753
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_WDOG0 (0x1UL << 6) |
WDOG0 Secure Access
Definition at line
724
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_WDOG0_DEFAULT ( _SMU_PPUSATD1_WDOG0_DEFAULT << 6) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
728
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_WDOG1 (0x1UL << 7) |
WDOG1 Secure Access
Definition at line
729
of file
efr32bg21_smu.h
.
#define SMU_PPUSATD1_WDOG1_DEFAULT ( _SMU_PPUSATD1_WDOG1_DEFAULT << 7) |
Shifted mode DEFAULT for SMU_PPUSATD1
Definition at line
733
of file
efr32bg21_smu.h
.
#define SMU_STATUS_SMULOCK (0x1UL << 0) |
SMU Lock
Definition at line
197
of file
efr32bg21_smu.h
.
#define SMU_STATUS_SMULOCK_DEFAULT ( _SMU_STATUS_SMULOCK_DEFAULT << 0) |
Shifted mode DEFAULT for SMU_STATUS
Definition at line
203
of file
efr32bg21_smu.h
.
#define SMU_STATUS_SMULOCK_LOCKED ( _SMU_STATUS_SMULOCK_LOCKED << 0) |
Shifted mode LOCKED for SMU_STATUS
Definition at line
205
of file
efr32bg21_smu.h
.
#define SMU_STATUS_SMULOCK_UNLOCKED ( _SMU_STATUS_SMULOCK_UNLOCKED << 0) |
Shifted mode UNLOCKED for SMU_STATUS
Definition at line
204
of file
efr32bg21_smu.h
.
#define SMU_STATUS_SMUPRGERR (0x1UL << 1) |
SMU Programming Error
Definition at line
206
of file
efr32bg21_smu.h
.
#define SMU_STATUS_SMUPRGERR_DEFAULT ( _SMU_STATUS_SMUPRGERR_DEFAULT << 1) |
Shifted mode DEFAULT for SMU_STATUS
Definition at line
210
of file
efr32bg21_smu.h
.