EFR32BG21A020F1024IM32 CoreDevices > EFR32BG21A020F1024IM32
Detailed Description
Processor and Core Peripheral Section.
Macros | |
#define | __CM33_REV 0x0000U |
#define | __DSP_PRESENT 1U |
#define | __FPU_PRESENT 1U |
#define | __MPU_PRESENT 1U |
#define | __NVIC_PRIO_BITS 4U |
#define | __SAUREGION_PRESENT 1U |
#define | __TZ_PRESENT 1U |
#define | __Vendor_SysTickConfig 0U |
#define | __VTOR_PRESENT 1U |
Macro Definition Documentation
#define __CM33_REV 0x0000U |
Cortex-M33 Core revision r0p2
Definition at line 134
of file efr32bg21a020f1024im32.h
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#define __DSP_PRESENT 1U |
Presence of DSP
Definition at line 135
of file efr32bg21a020f1024im32.h
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#define __FPU_PRESENT 1U |
Presence of FPU
Definition at line 136
of file efr32bg21a020f1024im32.h
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#define __MPU_PRESENT 1U |
Presence of MPU
Definition at line 137
of file efr32bg21a020f1024im32.h
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#define __NVIC_PRIO_BITS 4U |
NVIC interrupt priority bits
Definition at line 141
of file efr32bg21a020f1024im32.h
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Referenced by CORE_AtomicDisableIrq(), CORE_EnterAtomic(), CORE_IrqIsBlocked(), CORE_IrqIsDisabled(), CORE_YieldAtomic(), and LDMA_Init().
#define __SAUREGION_PRESENT 1U |
Presence of FPU
Definition at line 138
of file efr32bg21a020f1024im32.h
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#define __TZ_PRESENT 1U |
Presence of TrustZone
Definition at line 139
of file efr32bg21a020f1024im32.h
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#define __Vendor_SysTickConfig 0U |
Is 1 if different SysTick counter is used
Definition at line 142
of file efr32bg21a020f1024im32.h
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#define __VTOR_PRESENT 1U |
Presence of VTOR register in SCB
Definition at line 140
of file efr32bg21a020f1024im32.h
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