EFR32BG21A020F1024IM32 PartDevices > EFR32BG21A020F1024IM32
Macros |
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| #define | _EFR32_BG_FAMILY 1 /** Device Family Identifier*/ |
| #define | _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ |
| #define | _EFR_DEVICE 1 /** Product Line Identifier */ |
| #define | _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ |
| #define | _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ |
| #define | _SILICON_LABS_32B_SERIES_2_CONFIG 1 /** Product Config Identifier */ |
| #define | _SILICON_LABS_32B_SERIES_2_CONFIG_1 /** Product Config Identifier */ |
| #define | _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ |
| #define | _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ |
| #define | _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ |
| #define | _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID 200 /** Silicon Labs internal use only */ |
| #define | _SILICON_LABS_GECKO_INTERNAL_SDID_200 /** Silicon Labs internal use only */ |
| #define | _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_STANDARD /** Security feature set */ |
| #define | _SILICON_LABS_SECURITY_FEATURE_ADVANCED 1U /** Advanced */ |
| #define | _SILICON_LABS_SECURITY_FEATURE_STANDARD 0U /** Standard */ |
| #define | ACMP_COUNT 2 /** 2 ACMPs available */ |
| #define | ACMP_PRESENT /** ACMP is available in this part */ |
| #define | AGC_COUNT 1 /** 1 AGCs available */ |
| #define | AGC_PRESENT /** AGC is available in this part */ |
| #define | AMUXCP_COUNT 1 /** 1 AMUXCPs available */ |
| #define | AMUXCP_PRESENT /** AMUXCP is available in this part */ |
| #define | BUFC_COUNT 1 /** 1 BUFCs available */ |
| #define | BUFC_PRESENT /** BUFC is available in this part */ |
| #define | BURAM_COUNT 1 /** 1 BURAMs available */ |
| #define | BURAM_PRESENT /** BURAM is available in this part */ |
| #define | BURTC_COUNT 1 /** 1 BURTCs available */ |
| #define | BURTC_PRESENT /** BURTC is available in this part */ |
| #define | CMU_COUNT 1 /** 1 CMUs available */ |
| #define | CMU_PRESENT /** CMU is available in this part */ |
| #define | DEVINFO_COUNT 1 /** 1 DEVINFOs available */ |
| #define | DEVINFO_PRESENT /** DEVINFO is available in this part */ |
| #define | DMA_CHAN_COUNT LDMA_CH_NUM |
| #define | DMEM_RAM0_RAM_MEM_BASE ((uint32_t) 0x20000000UL) /** DMEM_RAM0_RAM base address */ |
| #define | DMEM_RAM0_RAM_MEM_BITS ((uint32_t) 0x11UL) /** DMEM_RAM0_RAM used bits */ |
| #define | DMEM_RAM0_RAM_MEM_END ((uint32_t) 0x20017FFFUL) /** DMEM_RAM0_RAM end address */ |
| #define | DMEM_RAM0_RAM_MEM_SIZE ((uint32_t) 0x00018000UL) /** DMEM_RAM0_RAM avaliable address space */ |
| #define | DPLL_COUNT 1 /** 1 DPLLs available */ |
| #define | DPLL_PRESENT /** DPLL is available in this part */ |
| #define | EMU_COUNT 1 /** 1 EMUs available */ |
| #define | EMU_PRESENT /** EMU is available in this part */ |
| #define | EXT_IRQ_COUNT 61 |
| #define | FLASH_BASE (0x00000000UL) |
| #define | FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /** FLASH_MEM base address */ |
| #define | FLASH_MEM_BITS ((uint32_t) 0x15UL) /** FLASH_MEM used bits */ |
| #define | FLASH_MEM_END ((uint32_t) 0x000FFFFFUL) /** FLASH_MEM end address */ |
| #define | FLASH_MEM_SIZE ((uint32_t) 0x00100000UL) /** FLASH_MEM avaliable address space */ |
| #define | FLASH_PAGE_SIZE (1UL << MSC_MAIN_PSIZE_BITS) |
| #define | FLASH_SIZE (0x00100000UL) |
| #define | FRC_COUNT 1 /** 1 FRCs available */ |
| #define | FRC_PRESENT /** FRC is available in this part */ |
| #define | FSRCO_COUNT 1 /** 1 FSRCOs available */ |
| #define | FSRCO_PRESENT /** FSRCO is available in this part */ |
| #define | GPCRC_COUNT 1 /** 1 GPCRCs available */ |
| #define | GPCRC_PRESENT /** GPCRC is available in this part */ |
| #define | GPIO_COUNT 1 /** 1 GPIOs available */ |
| #define | GPIO_EM4WU0_PIN 5U |
| #define | GPIO_EM4WU0_PORT GPIO_PA_INDEX |
| #define | GPIO_EM4WU3_PIN 1U |
| #define | GPIO_EM4WU3_PORT GPIO_PB_INDEX |
| #define | GPIO_EM4WU6_PIN 0U |
| #define | GPIO_EM4WU6_PORT GPIO_PC_INDEX |
| #define | GPIO_EM4WU7_PIN 5U |
| #define | GPIO_EM4WU7_PORT GPIO_PC_INDEX |
| #define | GPIO_EM4WU9_PIN 2U |
| #define | GPIO_EM4WU9_PORT GPIO_PD_INDEX |
| #define | GPIO_PA_COUNT 7U |
| #define | GPIO_PA_INDEX 0U |
| #define | GPIO_PA_PIN0 1U |
| #define | GPIO_PA_PIN1 1U |
| #define | GPIO_PA_PIN2 1U |
| #define | GPIO_PA_PIN3 1U |
| #define | GPIO_PA_PIN4 1U |
| #define | GPIO_PA_PIN5 1U |
| #define | GPIO_PA_PIN6 1U |
| #define | GPIO_PB_COUNT 2U |
| #define | GPIO_PB_INDEX 1U |
| #define | GPIO_PB_PIN0 1U |
| #define | GPIO_PB_PIN1 1U |
| #define | GPIO_PC_COUNT 5U |
| #define | GPIO_PC_INDEX 2U |
| #define | GPIO_PC_PIN1 1U |
| #define | GPIO_PC_PIN2 1U |
| #define | GPIO_PC_PIN3 1U |
| #define | GPIO_PC_PIN4 1U |
| #define | GPIO_PC_PIN5 1U |
| #define | GPIO_PD_COUNT 5U |
| #define | GPIO_PD_INDEX 3U |
| #define | GPIO_PD_PIN0 1U |
| #define | GPIO_PD_PIN1 1U |
| #define | GPIO_PD_PIN2 1U |
| #define | GPIO_PD_PIN3 1U |
| #define | GPIO_PD_PIN4 1U |
| #define | GPIO_PRESENT /** GPIO is available in this part */ |
| #define | GPIO_SWCLK_PIN 1U |
| #define | GPIO_SWCLK_PORT GPIO_PA_INDEX |
| #define | GPIO_SWDIO_PIN 2U |
| #define | GPIO_SWDIO_PORT GPIO_PA_INDEX |
| #define | GPIO_SWV_PIN 3U |
| #define | GPIO_SWV_PORT GPIO_PA_INDEX |
| #define | GPIO_TDI_PIN 4U |
| #define | GPIO_TDI_PORT GPIO_PA_INDEX |
| #define | GPIO_TDO_PIN 3U |
| #define | GPIO_TDO_PORT GPIO_PA_INDEX |
| #define | GPIO_TRACECLK_PIN 4U |
| #define | GPIO_TRACECLK_PORT GPIO_PA_INDEX |
| #define | GPIO_TRACEDATA0_PIN 3U |
| #define | GPIO_TRACEDATA0_PORT GPIO_PA_INDEX |
| #define | HFRCO_COUNT 1 /** 1 HFRCOs available */ |
| #define | HFRCO_PRESENT /** HFRCO is available in this part */ |
| #define | HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ |
| #define | HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ |
| #define | HFXO_COUNT 1 /** 1 HFXOs available */ |
| #define | HFXO_PRESENT /** HFXO is available in this part */ |
| #define | I2C_COUNT 2 /** 2 I2Cs available */ |
| #define | I2C_PRESENT /** I2C is available in this part */ |
| #define | IADC_COUNT 1 /** 1 IADCs available */ |
| #define | IADC_PRESENT /** IADC is available in this part */ |
| #define | ICACHE_COUNT 1 /** 1 ICACHEs available */ |
| #define | ICACHE_PRESENT /** ICACHE is available in this part */ |
| #define | LDMA_COUNT 1 /** 1 LDMAs available */ |
| #define | LDMA_PRESENT /** LDMA is available in this part */ |
| #define | LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ |
| #define | LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ |
| #define | LETIMER_COUNT 1 /** 1 LETIMERs available */ |
| #define | LETIMER_PRESENT /** LETIMER is available in this part */ |
| #define | LFRCO_COUNT 1 /** 1 LFRCOs available */ |
| #define | LFRCO_PRESENT /** LFRCO is available in this part */ |
| #define | LFXO_COUNT 1 /** 1 LFXOs available */ |
| #define | LFXO_LF_EXTCLK_PIN 1U |
| #define | LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX |
| #define | LFXO_LFXTAL_I_PIN 1U |
| #define | LFXO_LFXTAL_I_PORT GPIO_PD_INDEX |
| #define | LFXO_LFXTAL_O_PIN 0U |
| #define | LFXO_LFXTAL_O_PORT GPIO_PD_INDEX |
| #define | LFXO_PRESENT /** LFXO is available in this part */ |
| #define | LVGD_COUNT 1 /** 1 LVGDs available */ |
| #define | LVGD_PRESENT /** LVGD is available in this part */ |
| #define | MODEM_COUNT 1 /** 1 MODEMs available */ |
| #define | MODEM_PRESENT /** MODEM is available in this part */ |
| #define | MSC_COUNT 1 /** 1 MSCs available */ |
| #define | MSC_FLASH_CHIPCONFIG_MEM_BASE ((uint32_t) 0x0FE0E000UL) /** MSC_FLASH_CHIPCONFIG base address */ |
| #define | MSC_FLASH_CHIPCONFIG_MEM_BITS ((uint32_t) 0xBUL) /** MSC_FLASH_CHIPCONFIG used bits */ |
| #define | MSC_FLASH_CHIPCONFIG_MEM_END ((uint32_t) 0x0FE0E3FFUL) /** MSC_FLASH_CHIPCONFIG end address */ |
| #define | MSC_FLASH_CHIPCONFIG_MEM_SIZE ((uint32_t) 0x00000400UL) /** MSC_FLASH_CHIPCONFIG avaliable address space */ |
| #define | MSC_FLASH_DEVINFO_MEM_BASE ((uint32_t) 0x0FE08000UL) /** MSC_FLASH_DEVINFO base address */ |
| #define | MSC_FLASH_DEVINFO_MEM_BITS ((uint32_t) 0xBUL) /** MSC_FLASH_DEVINFO used bits */ |
| #define | MSC_FLASH_DEVINFO_MEM_END ((uint32_t) 0x0FE083FFUL) /** MSC_FLASH_DEVINFO end address */ |
| #define | MSC_FLASH_DEVINFO_MEM_SIZE ((uint32_t) 0x00000400UL) /** MSC_FLASH_DEVINFO avaliable address space */ |
| #define | MSC_FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /** MSC_FLASH base address */ |
| #define | MSC_FLASH_MEM_BITS ((uint32_t) 0x15UL) /** MSC_FLASH used bits */ |
| #define | MSC_FLASH_MEM_END ((uint32_t) 0x000FFFFFUL) /** MSC_FLASH end address */ |
| #define | MSC_FLASH_MEM_SIZE ((uint32_t) 0x00100000UL) /** MSC_FLASH avaliable address space */ |
| #define | MSC_FLASH_RESERVED_MEM_BASE ((uint32_t) 0x0FF00000UL) /** MSC_FLASH_RESERVED base address */ |
| #define | MSC_FLASH_RESERVED_MEM_BITS ((uint32_t) 0x15UL) /** MSC_FLASH_RESERVED used bits */ |
| #define | MSC_FLASH_RESERVED_MEM_END ((uint32_t) 0x0FFFFFFFUL) /** MSC_FLASH_RESERVED end address */ |
| #define | MSC_FLASH_RESERVED_MEM_SIZE ((uint32_t) 0x00100000UL) /** MSC_FLASH_RESERVED avaliable address space */ |
| #define | MSC_FLASH_USERDATA_MEM_BASE ((uint32_t) 0x0FE00000UL) /** MSC_FLASH_USERDATA base address */ |
| #define | MSC_FLASH_USERDATA_MEM_BITS ((uint32_t) 0xBUL) /** MSC_FLASH_USERDATA used bits */ |
| #define | MSC_FLASH_USERDATA_MEM_END ((uint32_t) 0x0FE003FFUL) /** MSC_FLASH_USERDATA end address */ |
| #define | MSC_FLASH_USERDATA_MEM_SIZE ((uint32_t) 0x00000400UL) /** MSC_FLASH_USERDATA avaliable address space */ |
| #define | MSC_PRESENT /** MSC is available in this part */ |
| #define | PART_NUMBER "EFR32BG21A020F1024IM32" |
| #define | PROTIMER_COUNT 1 /** 1 PROTIMERs available */ |
| #define | PROTIMER_PRESENT /** PROTIMER is available in this part */ |
| #define | PRS_COUNT 1 /** 1 PRSs available */ |
| #define | PRS_PRESENT /** PRS is available in this part */ |
| #define | RAC_COUNT 1 /** 1 RACs available */ |
| #define | RAC_PRESENT /** RAC is available in this part */ |
| #define | RADIOAES_COUNT 1 /** 1 RADIOAESs available */ |
| #define | RADIOAES_PRESENT /** RADIOAES is available in this part */ |
| #define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) /** RAM_MEM base address */ |
| #define | RAM_MEM_BITS ((uint32_t) 0x11UL) /** RAM_MEM used bits */ |
| #define | RAM_MEM_END ((uint32_t) 0x20017FFFUL) /** RAM_MEM end address */ |
| #define | RAM_MEM_SIZE ((uint32_t) 0x00018000UL) /** RAM_MEM avaliable address space */ |
| #define | RDMEM_FRCRAM_FRCRAM_MEM_BASE ((uint32_t) 0xB0002000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ |
| #define | RDMEM_FRCRAM_FRCRAM_MEM_BITS ((uint32_t) 0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ |
| #define | RDMEM_FRCRAM_FRCRAM_MEM_END ((uint32_t) 0xB0002FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ |
| #define | RDMEM_FRCRAM_FRCRAM_MEM_SIZE ((uint32_t) 0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM avaliable address space */ |
| #define | RDMEM_FRCRAM_NS_MEM_BASE ((uint32_t) 0xB0002000UL) /** RDMEM_FRCRAM_NS base address */ |
| #define | RDMEM_FRCRAM_NS_MEM_BITS ((uint32_t) 0xDUL) /** RDMEM_FRCRAM_NS used bits */ |
| #define | RDMEM_FRCRAM_NS_MEM_END ((uint32_t) 0xB0002FFFUL) /** RDMEM_FRCRAM_NS end address */ |
| #define | RDMEM_FRCRAM_NS_MEM_SIZE ((uint32_t) 0x00001000UL) /** RDMEM_FRCRAM_NS avaliable address space */ |
| #define | RDMEM_FRCRAM_S_MEM_BASE ((uint32_t) 0xA0002000UL) /** RDMEM_FRCRAM_S base address */ |
| #define | RDMEM_FRCRAM_S_MEM_BITS ((uint32_t) 0xDUL) /** RDMEM_FRCRAM_S used bits */ |
| #define | RDMEM_FRCRAM_S_MEM_END ((uint32_t) 0xA0002FFFUL) /** RDMEM_FRCRAM_S end address */ |
| #define | RDMEM_FRCRAM_S_MEM_SIZE ((uint32_t) 0x00001000UL) /** RDMEM_FRCRAM_S avaliable address space */ |
| #define | RDMEM_SEQRAM_NS_MEM_BASE ((uint32_t) 0xB0000000UL) /** RDMEM_SEQRAM_NS base address */ |
| #define | RDMEM_SEQRAM_NS_MEM_BITS ((uint32_t) 0xEUL) /** RDMEM_SEQRAM_NS used bits */ |
| #define | RDMEM_SEQRAM_NS_MEM_END ((uint32_t) 0xB0001FFFUL) /** RDMEM_SEQRAM_NS end address */ |
| #define | RDMEM_SEQRAM_NS_MEM_SIZE ((uint32_t) 0x00002000UL) /** RDMEM_SEQRAM_NS avaliable address space */ |
| #define | RDMEM_SEQRAM_S_MEM_BASE ((uint32_t) 0xA0000000UL) /** RDMEM_SEQRAM_S base address */ |
| #define | RDMEM_SEQRAM_S_MEM_BITS ((uint32_t) 0xEUL) /** RDMEM_SEQRAM_S used bits */ |
| #define | RDMEM_SEQRAM_S_MEM_END ((uint32_t) 0xA0001FFFUL) /** RDMEM_SEQRAM_S end address */ |
| #define | RDMEM_SEQRAM_S_MEM_SIZE ((uint32_t) 0x00002000UL) /** RDMEM_SEQRAM_S avaliable address space */ |
| #define | RDMEM_SEQRAM_SEQRAM_MEM_BASE ((uint32_t) 0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ |
| #define | RDMEM_SEQRAM_SEQRAM_MEM_BITS ((uint32_t) 0xEUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ |
| #define | RDMEM_SEQRAM_SEQRAM_MEM_END ((uint32_t) 0xB0001FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ |
| #define | RDMEM_SEQRAM_SEQRAM_MEM_SIZE ((uint32_t) 0x00002000UL) /** RDMEM_SEQRAM_SEQRAM_MEM avaliable address space */ |
| #define | RFCRC_COUNT 1 /** 1 RFCRCs available */ |
| #define | RFCRC_PRESENT /** RFCRC is available in this part */ |
| #define | RTCC_COUNT 1 /** 1 RTCCs available */ |
| #define | RTCC_PRESENT /** RTCC is available in this part */ |
| #define | SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ |
| #define | SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ |
| #define | SMU_COUNT 1 /** 1 SMUs available */ |
| #define | SMU_PRESENT /** SMU is available in this part */ |
| #define | SRAM_BASE (0x20000000UL) |
| #define | SRAM_SIZE (0x00018000UL) |
| #define | SYNTH_COUNT 1 /** 1 SYNTHs available */ |
| #define | SYNTH_PRESENT /** SYNTH is available in this part */ |
| #define | SYSCFG_COUNT 1 /** 1 SYSCFGs available */ |
| #define | SYSCFG_PRESENT /** SYSCFG is available in this part */ |
| #define | TIMER_COUNT 4 /** 4 TIMERs available */ |
| #define | TIMER_PRESENT /** TIMER is available in this part */ |
| #define | ULFRCO_COUNT 1 /** 1 ULFRCOs available */ |
| #define | ULFRCO_PRESENT /** ULFRCO is available in this part */ |
| #define | USART_COUNT 3 /** 3 USARTs available */ |
| #define | USART_PRESENT /** USART is available in this part */ |
| #define | USERDATA_BASE ((uint32_t) 0x0FE00000UL) /** USERDATA base address */ |
| #define | USERDATA_BITS ((uint32_t) 0xBUL) /** USERDATA used bits */ |
| #define | USERDATA_END ((uint32_t) 0x0FE003FFUL) /** USERDATA end address */ |
| #define | USERDATA_SIZE ((uint32_t) 0x00000400UL) /** USERDATA avaliable address space */ |
| #define | WDOG_COUNT 2 /** 2 WDOGs available */ |
| #define | WDOG_PRESENT /** WDOG is available in this part */ |
Macro Definition Documentation
| #define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ |
Family / Line / Series / Config
Definition at line
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| #define DMA_CHAN_COUNT LDMA_CH_NUM |
Number of DMA channels
Definition at line
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Referenced by NANDFLASH_Init() .
| #define EXT_IRQ_COUNT 61 |
Number of External (NVIC) interrupts
Definition at line
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Referenced by CORE_GetNvicRamTableHandler() , CORE_IrqIsBlocked() , CORE_NvicIRQDisabled() , CORE_NvicMaskClearIRQ() , CORE_NvicMaskSetIRQ() , and CORE_SetNvicRamTableHandler() .
| #define FLASH_BASE (0x00000000UL) |
Flash and SRAM limits for EFR32BG21A020F1024IM32 Flash Base Address
Definition at line
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| #define FLASH_PAGE_SIZE (1UL << MSC_MAIN_PSIZE_BITS) |
Flash Memory page size
Definition at line
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Referenced by MSC_ErasePage() , MSC_WriteWord() , and SYSTEM_GetFlashPageSize() .
| #define FLASH_SIZE (0x00100000UL) |
Available Flash Memory
Definition at line
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| #define GPIO_EM4WU0_PIN 5U |
Pin of EM4WU0.
Definition at line
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| #define GPIO_EM4WU0_PORT GPIO_PA_INDEX |
Port of EM4WU0.
Definition at line
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| #define GPIO_EM4WU3_PIN 1U |
Pin of EM4WU3.
Definition at line
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| #define GPIO_EM4WU3_PORT GPIO_PB_INDEX |
Port of EM4WU3.
Definition at line
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| #define GPIO_EM4WU6_PIN 0U |
Pin of EM4WU6.
Definition at line
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| #define GPIO_EM4WU6_PORT GPIO_PC_INDEX |
Port of EM4WU6.
Definition at line
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| #define GPIO_EM4WU7_PIN 5U |
Pin of EM4WU7.
Definition at line
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| #define GPIO_EM4WU7_PORT GPIO_PC_INDEX |
Port of EM4WU7.
Definition at line
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| #define GPIO_EM4WU9_PIN 2U |
Pin of EM4WU9.
Definition at line
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| #define GPIO_EM4WU9_PORT GPIO_PD_INDEX |
Port of EM4WU9.
Definition at line
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| #define GPIO_PA_COUNT 7U |
Number of pins on port PA
Definition at line
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| #define GPIO_PA_INDEX 0U |
Index of port PA
Definition at line
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| #define GPIO_PA_PIN0 1U |
GPIO pin PA0 is present.
Definition at line
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| #define GPIO_PA_PIN1 1U |
GPIO pin PA1 is present.
Definition at line
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| #define GPIO_PA_PIN2 1U |
GPIO pin PA2 is present.
Definition at line
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| #define GPIO_PA_PIN3 1U |
GPIO pin PA3 is present.
Definition at line
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| #define GPIO_PA_PIN4 1U |
GPIO pin PA4 is present.
Definition at line
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| #define GPIO_PA_PIN5 1U |
GPIO pin PA5 is present.
Definition at line
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| #define GPIO_PA_PIN6 1U |
GPIO pin PA6 is present.
Definition at line
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| #define GPIO_PB_COUNT 2U |
Number of pins on port PB
Definition at line
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| #define GPIO_PB_INDEX 1U |
Index of port PB
Definition at line
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| #define GPIO_PB_PIN0 1U |
GPIO pin PB0 is present.
Definition at line
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| #define GPIO_PB_PIN1 1U |
GPIO pin PB1 is present.
Definition at line
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| #define GPIO_PC_COUNT 5U |
Number of pins on port PC
Definition at line
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| #define GPIO_PC_INDEX 2U |
Index of port PC
Definition at line
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| #define GPIO_PC_PIN1 1U |
GPIO pin PC1 is present.
Definition at line
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| #define GPIO_PC_PIN2 1U |
GPIO pin PC2 is present.
Definition at line
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| #define GPIO_PC_PIN3 1U |
GPIO pin PC3 is present.
Definition at line
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| #define GPIO_PC_PIN4 1U |
GPIO pin PC4 is present.
Definition at line
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| #define GPIO_PC_PIN5 1U |
GPIO pin PC5 is present.
Definition at line
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| #define GPIO_PD_COUNT 5U |
Number of pins on port PD
Definition at line
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| #define GPIO_PD_INDEX 3U |
Index of port PD
Definition at line
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| #define GPIO_PD_PIN0 1U |
GPIO pin PD0 is present.
Definition at line
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.
| #define GPIO_PD_PIN1 1U |
GPIO pin PD1 is present.
Definition at line
274
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_PD_PIN2 1U |
GPIO pin PD2 is present.
Definition at line
275
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_PD_PIN3 1U |
GPIO pin PD3 is present.
Definition at line
276
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_PD_PIN4 1U |
GPIO pin PD4 is present.
Definition at line
277
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_SWCLK_PIN 1U |
Pin of SWCLK.
Definition at line
281
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_SWCLK_PORT GPIO_PA_INDEX |
Port of SWCLK.
Definition at line
280
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_SWDIO_PIN 2U |
Pin of SWDIO.
Definition at line
283
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_SWDIO_PORT GPIO_PA_INDEX |
Port of SWDIO.
Definition at line
282
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_SWV_PIN 3U |
Pin of SWV.
Definition at line
285
of file
efr32bg21a020f1024im32.h
.
Referenced by DBG_SWOEnable() .
| #define GPIO_SWV_PORT GPIO_PA_INDEX |
Port of SWV.
Definition at line
284
of file
efr32bg21a020f1024im32.h
.
Referenced by DBG_SWOEnable() .
| #define GPIO_TDI_PIN 4U |
Pin of TDI.
Definition at line
287
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_TDI_PORT GPIO_PA_INDEX |
Port of TDI.
Definition at line
286
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_TDO_PIN 3U |
Pin of TDO.
Definition at line
289
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_TDO_PORT GPIO_PA_INDEX |
Port of TDO.
Definition at line
288
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_TRACECLK_PIN 4U |
Pin of TRACECLK.
Definition at line
291
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_TRACECLK_PORT GPIO_PA_INDEX |
Port of TRACECLK.
Definition at line
290
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_TRACEDATA0_PIN 3U |
Pin of TRACEDATA0.
Definition at line
293
of file
efr32bg21a020f1024im32.h
.
| #define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX |
Port of TRACEDATA0.
Definition at line
292
of file
efr32bg21a020f1024im32.h
.
| #define LFXO_LF_EXTCLK_PIN 1U |
Pin of LF_EXTCLK.
Definition at line
309
of file
efr32bg21a020f1024im32.h
.
| #define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX |
Port of LF_EXTCLK.
Definition at line
308
of file
efr32bg21a020f1024im32.h
.
| #define LFXO_LFXTAL_I_PIN 1U |
Pin of LFXTAL_I.
Definition at line
305
of file
efr32bg21a020f1024im32.h
.
| #define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX |
Port of LFXTAL_I.
Definition at line
304
of file
efr32bg21a020f1024im32.h
.
| #define LFXO_LFXTAL_O_PIN 0U |
Pin of LFXTAL_O.
Definition at line
307
of file
efr32bg21a020f1024im32.h
.
| #define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX |
Port of LFXTAL_O.
Definition at line
306
of file
efr32bg21a020f1024im32.h
.
| #define MSC_FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /** MSC_FLASH base address */ |
Memory Base addresses and limits
Definition at line
180
of file
efr32bg21a020f1024im32.h
.
| #define PART_NUMBER "EFR32BG21A020F1024IM32" |
Part number Configure part number Part Number
Definition at line
159
of file
efr32bg21a020f1024im32.h
.
| #define SRAM_BASE (0x20000000UL) |
SRAM Base Address
Definition at line
245
of file
efr32bg21a020f1024im32.h
.
Referenced by BUS_RamBitRead() , BUS_RamBitWrite() , CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .
| #define SRAM_SIZE (0x00018000UL) |
Available SRAM Memory
Definition at line
246
of file
efr32bg21a020f1024im32.h
.
Referenced by CORE_InitNvicVectorTable() , and EMU_RamPowerDown() .