DEVINFO Bit FieldsDevices > Device Information and Calibration

Macros

#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK   0x7F00UL
 
#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT   8
 
#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK   0x7F000000UL
 
#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT   24
 
#define _DEVINFO_ADC0CAL0_MASK   0x7FFF7FFFUL
 
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK   0xF0UL
 
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT   4
 
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK   0xF00000UL
 
#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT   20
 
#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK   0xFUL
 
#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT   0
 
#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK   0xF0000UL
 
#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT   16
 
#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK   0x7F000000UL
 
#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT   24
 
#define _DEVINFO_ADC0CAL1_GAINVDD_MASK   0x7F00UL
 
#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT   8
 
#define _DEVINFO_ADC0CAL1_MASK   0x7FFF7FFFUL
 
#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK   0xF00000UL
 
#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT   20
 
#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK   0xF0UL
 
#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT   4
 
#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK   0xF0000UL
 
#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT   16
 
#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK   0xFUL
 
#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT   0
 
#define _DEVINFO_ADC0CAL2_MASK   0x000000FFUL
 
#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK   0xF0UL
 
#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT   4
 
#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK   0xFUL
 
#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT   0
 
#define _DEVINFO_ADC0CAL3_MASK   0x0000FFF0UL
 
#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK   0xFFF0UL
 
#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT   4
 
#define _DEVINFO_ADC1CAL0_GAIN1V25_MASK   0x7F00UL
 
#define _DEVINFO_ADC1CAL0_GAIN1V25_SHIFT   8
 
#define _DEVINFO_ADC1CAL0_GAIN2V5_MASK   0x7F000000UL
 
#define _DEVINFO_ADC1CAL0_GAIN2V5_SHIFT   24
 
#define _DEVINFO_ADC1CAL0_MASK   0x7FFF7FFFUL
 
#define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_MASK   0xF0UL
 
#define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_SHIFT   4
 
#define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_MASK   0xF00000UL
 
#define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_SHIFT   20
 
#define _DEVINFO_ADC1CAL0_OFFSET1V25_MASK   0xFUL
 
#define _DEVINFO_ADC1CAL0_OFFSET1V25_SHIFT   0
 
#define _DEVINFO_ADC1CAL0_OFFSET2V5_MASK   0xF0000UL
 
#define _DEVINFO_ADC1CAL0_OFFSET2V5_SHIFT   16
 
#define _DEVINFO_ADC1CAL1_GAIN5VDIFF_MASK   0x7F000000UL
 
#define _DEVINFO_ADC1CAL1_GAIN5VDIFF_SHIFT   24
 
#define _DEVINFO_ADC1CAL1_GAINVDD_MASK   0x7F00UL
 
#define _DEVINFO_ADC1CAL1_GAINVDD_SHIFT   8
 
#define _DEVINFO_ADC1CAL1_MASK   0x7FFF7FFFUL
 
#define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_MASK   0xF00000UL
 
#define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_SHIFT   20
 
#define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_MASK   0xF0UL
 
#define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_SHIFT   4
 
#define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_MASK   0xF0000UL
 
#define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_SHIFT   16
 
#define _DEVINFO_ADC1CAL1_OFFSETVDD_MASK   0xFUL
 
#define _DEVINFO_ADC1CAL1_OFFSETVDD_SHIFT   0
 
#define _DEVINFO_ADC1CAL2_MASK   0x000000FFUL
 
#define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_MASK   0xF0UL
 
#define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_SHIFT   4
 
#define _DEVINFO_ADC1CAL2_OFFSET2XVDD_MASK   0xFUL
 
#define _DEVINFO_ADC1CAL2_OFFSET2XVDD_SHIFT   0
 
#define _DEVINFO_ADC1CAL3_MASK   0x0000FFF0UL
 
#define _DEVINFO_ADC1CAL3_TEMPREAD1V25_MASK   0xFFF0UL
 
#define _DEVINFO_ADC1CAL3_TEMPREAD1V25_SHIFT   4
 
#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL0_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL10_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL11_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL12_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL13_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL13_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL13_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL13_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL13_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL13_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL13_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL13_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL13_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL13_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL13_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL14_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL14_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL14_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL14_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL14_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL14_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL14_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL14_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL14_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL14_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL14_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL3_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL6_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL7_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT   28
 
#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT   25
 
#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT   21
 
#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT   8
 
#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT   16
 
#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT   24
 
#define _DEVINFO_AUXHFRCOCAL8_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK   0x7FUL
 
#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT   0
 
#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT   28
 
#define _DEVINFO_CAL_CRC_MASK   0xFFFFUL
 
#define _DEVINFO_CAL_CRC_SHIFT   0
 
#define _DEVINFO_CAL_MASK   0x00FFFFFFUL
 
#define _DEVINFO_CAL_TEMP_MASK   0xFF0000UL
 
#define _DEVINFO_CAL_TEMP_SHIFT   16
 
#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK   0xFFUL
 
#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT   0
 
#define _DEVINFO_CSENGAINCAL_MASK   0x000000FFUL
 
#define _DEVINFO_CURRMON5V_MASK   0x00000000UL
 
#define _DEVINFO_CUSTOMINFO_MASK   0xFFFF0000UL
 
#define _DEVINFO_CUSTOMINFO_PARTNO_MASK   0xFFFF0000UL
 
#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT   16
 
#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK   0xFFUL
 
#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT   0
 
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK   0xFF00UL
 
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT   8
 
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK   0xFF0000UL
 
#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT   16
 
#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK   0xFF000000UL
 
#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT   24
 
#define _DEVINFO_DCDCLNVCTRL0_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK   0xFFUL
 
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT   0
 
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK   0xFF00UL
 
#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT   8
 
#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK   0x0000FFFFUL
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK   0xFFUL
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT   0
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK   0xFF00UL
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT   8
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK   0xFF0000UL
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT   16
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK   0xFF000000UL
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT   24
 
#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK   0xFFUL
 
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT   0
 
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK   0xFF0000UL
 
#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT   16
 
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK   0xFF00UL
 
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT   8
 
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK   0xFF000000UL
 
#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT   24
 
#define _DEVINFO_DCDCLPVCTRL0_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK   0xFFUL
 
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT   0
 
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK   0xFF0000UL
 
#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT   16
 
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK   0xFF00UL
 
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT   8
 
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK   0xFF000000UL
 
#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT   24
 
#define _DEVINFO_DCDCLPVCTRL1_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK   0xFFUL
 
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT   0
 
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK   0xFF0000UL
 
#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT   16
 
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK   0xFF00UL
 
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT   8
 
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK   0xFF000000UL
 
#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT   24
 
#define _DEVINFO_DCDCLPVCTRL2_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK   0xFFUL
 
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT   0
 
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK   0xFF0000UL
 
#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT   16
 
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK   0xFF00UL
 
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT   8
 
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK   0xFF000000UL
 
#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT   24
 
#define _DEVINFO_DCDCLPVCTRL3_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_DEVINFOREV_MAJOR_MASK   0xE0UL
 
#define _DEVINFO_DEVINFOREV_MAJOR_SHIFT   5
 
#define _DEVINFO_DEVINFOREV_MASK   0x000000FFUL
 
#define _DEVINFO_DEVINFOREV_MINOR_MASK   0x1FUL
 
#define _DEVINFO_DEVINFOREV_MINOR_SHIFT   0
 
#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK   0xFFUL
 
#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT   0
 
#define _DEVINFO_EMUTEMP_MASK   0x000000FFUL
 
#define _DEVINFO_EUI48H_MASK   0x0000FFFFUL
 
#define _DEVINFO_EUI48H_OUI48H_MASK   0xFFFFUL
 
#define _DEVINFO_EUI48H_OUI48H_SHIFT   0
 
#define _DEVINFO_EUI48L_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_EUI48L_OUI48L_MASK   0xFF000000UL
 
#define _DEVINFO_EUI48L_OUI48L_SHIFT   24
 
#define _DEVINFO_EUI48L_UNIQUEID_MASK   0xFFFFFFUL
 
#define _DEVINFO_EUI48L_UNIQUEID_SHIFT   0
 
#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL0_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL0_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL0_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL0_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL10_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL10_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL10_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL10_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL11_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL11_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL11_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL11_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL12_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL12_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL12_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL12_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL13_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL13_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL13_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL13_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL13_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL13_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL13_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL13_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL13_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL13_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL13_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL13_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL13_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL13_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL13_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL13_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL13_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL14_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL14_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL14_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL14_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL14_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL14_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL14_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL14_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL14_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL14_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL14_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL14_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL14_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL14_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL14_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL14_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL14_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL15_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL15_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL15_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL15_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL15_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL15_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL15_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL15_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL15_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL15_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL15_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL15_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL15_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL15_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL15_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL15_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL15_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL16_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL16_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL16_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL16_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL16_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL16_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL16_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL16_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL16_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL16_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL16_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL16_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL16_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL16_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL16_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL16_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL16_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL3_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL3_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL3_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL3_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL6_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL6_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL6_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL6_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL7_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL7_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL7_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL7_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT   28
 
#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT   25
 
#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT   21
 
#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT   8
 
#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT   16
 
#define _DEVINFO_HFRCOCAL8_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT   24
 
#define _DEVINFO_HFRCOCAL8_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_HFRCOCAL8_TUNING_MASK   0x7FUL
 
#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT   0
 
#define _DEVINFO_HFRCOCAL8_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT   28
 
#define _DEVINFO_IDAC0CAL0_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK   0xFFUL
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT   0
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK   0xFF00UL
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT   8
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK   0xFF0000UL
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT   16
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK   0xFF000000UL
 
#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT   24
 
#define _DEVINFO_IDAC0CAL1_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK   0xFFUL
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT   0
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK   0xFF00UL
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT   8
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK   0xFF0000UL
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT   16
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK   0xFF000000UL
 
#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT   24
 
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK   0xFF000000UL
 
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT   24
 
#define _DEVINFO_MEMINFO_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_MEMINFO_PINCOUNT_MASK   0xFF0000UL
 
#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT   16
 
#define _DEVINFO_MEMINFO_PKGTYPE_BGA   0x0000004CUL
 
#define _DEVINFO_MEMINFO_PKGTYPE_MASK   0xFF00UL
 
#define _DEVINFO_MEMINFO_PKGTYPE_QFN   0x0000004DUL
 
#define _DEVINFO_MEMINFO_PKGTYPE_QFP   0x00000051UL
 
#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT   8
 
#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP   0x0000004AUL
 
#define _DEVINFO_MEMINFO_TEMPGRADE_MASK   0xFFUL
 
#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70   0x00000003UL
 
#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105   0x00000002UL
 
#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125   0x00000001UL
 
#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85   0x00000000UL
 
#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT   0
 
#define _DEVINFO_MSIZE_FLASH_MASK   0xFFFFUL
 
#define _DEVINFO_MSIZE_FLASH_SHIFT   0
 
#define _DEVINFO_MSIZE_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_MSIZE_SRAM_MASK   0xFFFF0000UL
 
#define _DEVINFO_MSIZE_SRAM_SHIFT   16
 
#define _DEVINFO_OPA0CAL0_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL0_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL0_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL0_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL0_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL0_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL0_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL0_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL0_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL0_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL0_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL0_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL0_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA0CAL1_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL1_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL1_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL1_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL1_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL1_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL1_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL1_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL1_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL1_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL1_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL1_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL1_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA0CAL2_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL2_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL2_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL2_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL2_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL2_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL2_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL2_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL2_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL2_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL2_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL2_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL2_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA0CAL3_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL3_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL3_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL3_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL3_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL3_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL3_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL3_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL3_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL3_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL3_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL3_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL3_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA0CAL4_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL4_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL4_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL4_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL4_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL4_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL4_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL4_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL4_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL4_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL4_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL4_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL4_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA0CAL5_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL5_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL5_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL5_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL5_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL5_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL5_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL5_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL5_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL5_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL5_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL5_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL5_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA0CAL6_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL6_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL6_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL6_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL6_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL6_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL6_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL6_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL6_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL6_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL6_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL6_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL6_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA0CAL7_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA0CAL7_CM1_SHIFT   0
 
#define _DEVINFO_OPA0CAL7_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA0CAL7_CM2_SHIFT   5
 
#define _DEVINFO_OPA0CAL7_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA0CAL7_CM3_SHIFT   10
 
#define _DEVINFO_OPA0CAL7_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA0CAL7_GM3_SHIFT   17
 
#define _DEVINFO_OPA0CAL7_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA0CAL7_GM_SHIFT   13
 
#define _DEVINFO_OPA0CAL7_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA0CAL7_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA0CAL7_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL0_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL0_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL0_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL0_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL0_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL0_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL0_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL0_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL0_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL0_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL0_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL0_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL0_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL1_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL1_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL1_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL1_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL1_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL1_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL1_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL1_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL1_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL1_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL1_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL1_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL1_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL2_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL2_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL2_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL2_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL2_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL2_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL2_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL2_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL2_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL2_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL2_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL2_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL2_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL3_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL3_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL3_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL3_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL3_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL3_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL3_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL3_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL3_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL3_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL3_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL3_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL3_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL4_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL4_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL4_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL4_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL4_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL4_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL4_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL4_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL4_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL4_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL4_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL4_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL4_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL5_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL5_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL5_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL5_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL5_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL5_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL5_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL5_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL5_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL5_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL5_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL5_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL5_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL6_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL6_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL6_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL6_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL6_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL6_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL6_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL6_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL6_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL6_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL6_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL6_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL6_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA1CAL7_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA1CAL7_CM1_SHIFT   0
 
#define _DEVINFO_OPA1CAL7_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA1CAL7_CM2_SHIFT   5
 
#define _DEVINFO_OPA1CAL7_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA1CAL7_CM3_SHIFT   10
 
#define _DEVINFO_OPA1CAL7_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA1CAL7_GM3_SHIFT   17
 
#define _DEVINFO_OPA1CAL7_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA1CAL7_GM_SHIFT   13
 
#define _DEVINFO_OPA1CAL7_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA1CAL7_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA1CAL7_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL0_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL0_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL0_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL0_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL0_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL0_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL0_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL0_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL0_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL0_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL0_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL0_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL0_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL1_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL1_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL1_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL1_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL1_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL1_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL1_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL1_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL1_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL1_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL1_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL1_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL1_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL2_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL2_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL2_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL2_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL2_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL2_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL2_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL2_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL2_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL2_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL2_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL2_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL2_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL3_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL3_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL3_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL3_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL3_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL3_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL3_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL3_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL3_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL3_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL3_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL3_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL3_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL4_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL4_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL4_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL4_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL4_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL4_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL4_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL4_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL4_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL4_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL4_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL4_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL4_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL5_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL5_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL5_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL5_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL5_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL5_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL5_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL5_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL5_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL5_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL5_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL5_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL5_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL6_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL6_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL6_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL6_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL6_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL6_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL6_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL6_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL6_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL6_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL6_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL6_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL6_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA2CAL7_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA2CAL7_CM1_SHIFT   0
 
#define _DEVINFO_OPA2CAL7_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA2CAL7_CM2_SHIFT   5
 
#define _DEVINFO_OPA2CAL7_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA2CAL7_CM3_SHIFT   10
 
#define _DEVINFO_OPA2CAL7_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA2CAL7_GM3_SHIFT   17
 
#define _DEVINFO_OPA2CAL7_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA2CAL7_GM_SHIFT   13
 
#define _DEVINFO_OPA2CAL7_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA2CAL7_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA2CAL7_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL0_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL0_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL0_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL0_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL0_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL0_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL0_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL0_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL0_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL0_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL0_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL0_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL0_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL0_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL0_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL1_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL1_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL1_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL1_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL1_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL1_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL1_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL1_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL1_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL1_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL1_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL1_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL1_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL1_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL1_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL2_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL2_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL2_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL2_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL2_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL2_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL2_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL2_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL2_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL2_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL2_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL2_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL2_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL2_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL2_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL3_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL3_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL3_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL3_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL3_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL3_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL3_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL3_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL3_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL3_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL3_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL3_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL3_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL3_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL3_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL4_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL4_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL4_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL4_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL4_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL4_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL4_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL4_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL4_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL4_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL4_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL4_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL4_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL4_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL4_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL5_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL5_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL5_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL5_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL5_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL5_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL5_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL5_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL5_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL5_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL5_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL5_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL5_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL5_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL5_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL6_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL6_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL6_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL6_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL6_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL6_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL6_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL6_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL6_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL6_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL6_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL6_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL6_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL6_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL6_OFFSETP_SHIFT   20
 
#define _DEVINFO_OPA3CAL7_CM1_MASK   0xFUL
 
#define _DEVINFO_OPA3CAL7_CM1_SHIFT   0
 
#define _DEVINFO_OPA3CAL7_CM2_MASK   0x1E0UL
 
#define _DEVINFO_OPA3CAL7_CM2_SHIFT   5
 
#define _DEVINFO_OPA3CAL7_CM3_MASK   0xC00UL
 
#define _DEVINFO_OPA3CAL7_CM3_SHIFT   10
 
#define _DEVINFO_OPA3CAL7_GM3_MASK   0x60000UL
 
#define _DEVINFO_OPA3CAL7_GM3_SHIFT   17
 
#define _DEVINFO_OPA3CAL7_GM_MASK   0xE000UL
 
#define _DEVINFO_OPA3CAL7_GM_SHIFT   13
 
#define _DEVINFO_OPA3CAL7_MASK   0x7DF6EDEFUL
 
#define _DEVINFO_OPA3CAL7_OFFSETN_MASK   0x7C000000UL
 
#define _DEVINFO_OPA3CAL7_OFFSETN_SHIFT   26
 
#define _DEVINFO_OPA3CAL7_OFFSETP_MASK   0x1F00000UL
 
#define _DEVINFO_OPA3CAL7_OFFSETP_SHIFT   20
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G   0x00000047UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG   0x00000048UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B   0x00000064UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG   0x0000004DUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B   0x00000057UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B   0x00000053UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG   0x0000004AUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B   0x00000055UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B   0x00000051UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG   0x00000049UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B   0x00000067UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG   0x0000004BUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG   0x0000004CUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B   0x00000020UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P   0x0000001FUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V   0x00000021UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B   0x0000002CUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P   0x0000002BUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V   0x0000002DUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B   0x00000038UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P   0x00000037UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V   0x00000039UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B   0x00000014UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P   0x00000013UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V   0x00000015UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B   0x00000026UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P   0x00000025UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V   0x00000027UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B   0x00000032UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P   0x00000031UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V   0x00000033UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B   0x0000003EUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P   0x0000003DUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V   0x0000003FUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B   0x0000001AUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P   0x00000019UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V   0x0000001BUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B   0x0000001DUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P   0x0000001CUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V   0x0000001EUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B   0x00000029UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P   0x00000028UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V   0x0000002AUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B   0x00000035UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P   0x00000034UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V   0x00000036UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B   0x00000011UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P   0x00000010UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V   0x00000012UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG   0x0000007AUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG   0x00000078UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG   0x00000079UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_G   0x00000047UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_GG   0x00000048UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_HG   0x0000004DUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_LG   0x0000004AUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_MASK   0xFF0000UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT   16
 
#define _DEVINFO_PART_DEVICE_FAMILY_TG   0x00000049UL
 
#define _DEVINFO_PART_DEVICE_FAMILY_WG   0x0000004BUL
 
#define _DEVINFO_PART_DEVICE_FAMILY_ZG   0x0000004CUL
 
#define _DEVINFO_PART_DEVICE_NUMBER_MASK   0xFFFFUL
 
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT   0
 
#define _DEVINFO_PART_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_PART_PROD_REV_MASK   0xFF000000UL
 
#define _DEVINFO_PART_PROD_REV_SHIFT   24
 
#define _DEVINFO_UNIQUEH_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_UNIQUEH_UNIQUEH_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT   0
 
#define _DEVINFO_UNIQUEL_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_UNIQUEL_UNIQUEL_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT   0
 
#define _DEVINFO_USHFRCOCAL11_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_USHFRCOCAL11_CLKDIV_SHIFT   25
 
#define _DEVINFO_USHFRCOCAL11_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_USHFRCOCAL11_CMPBIAS_SHIFT   21
 
#define _DEVINFO_USHFRCOCAL11_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_USHFRCOCAL11_FINETUNING_SHIFT   8
 
#define _DEVINFO_USHFRCOCAL11_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_USHFRCOCAL11_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_USHFRCOCAL11_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_USHFRCOCAL11_FREQRANGE_SHIFT   16
 
#define _DEVINFO_USHFRCOCAL11_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_USHFRCOCAL11_LDOHP_SHIFT   24
 
#define _DEVINFO_USHFRCOCAL11_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_USHFRCOCAL11_TUNING_MASK   0x7FUL
 
#define _DEVINFO_USHFRCOCAL11_TUNING_SHIFT   0
 
#define _DEVINFO_USHFRCOCAL11_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_USHFRCOCAL11_VREFTC_SHIFT   28
 
#define _DEVINFO_USHFRCOCAL13_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_USHFRCOCAL13_CLKDIV_SHIFT   25
 
#define _DEVINFO_USHFRCOCAL13_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_USHFRCOCAL13_CMPBIAS_SHIFT   21
 
#define _DEVINFO_USHFRCOCAL13_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_USHFRCOCAL13_FINETUNING_SHIFT   8
 
#define _DEVINFO_USHFRCOCAL13_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_USHFRCOCAL13_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_USHFRCOCAL13_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_USHFRCOCAL13_FREQRANGE_SHIFT   16
 
#define _DEVINFO_USHFRCOCAL13_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_USHFRCOCAL13_LDOHP_SHIFT   24
 
#define _DEVINFO_USHFRCOCAL13_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_USHFRCOCAL13_TUNING_MASK   0x7FUL
 
#define _DEVINFO_USHFRCOCAL13_TUNING_SHIFT   0
 
#define _DEVINFO_USHFRCOCAL13_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_USHFRCOCAL13_VREFTC_SHIFT   28
 
#define _DEVINFO_USHFRCOCAL14_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_USHFRCOCAL14_CLKDIV_SHIFT   25
 
#define _DEVINFO_USHFRCOCAL14_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_USHFRCOCAL14_CMPBIAS_SHIFT   21
 
#define _DEVINFO_USHFRCOCAL14_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_USHFRCOCAL14_FINETUNING_SHIFT   8
 
#define _DEVINFO_USHFRCOCAL14_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_USHFRCOCAL14_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_USHFRCOCAL14_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_USHFRCOCAL14_FREQRANGE_SHIFT   16
 
#define _DEVINFO_USHFRCOCAL14_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_USHFRCOCAL14_LDOHP_SHIFT   24
 
#define _DEVINFO_USHFRCOCAL14_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_USHFRCOCAL14_TUNING_MASK   0x7FUL
 
#define _DEVINFO_USHFRCOCAL14_TUNING_SHIFT   0
 
#define _DEVINFO_USHFRCOCAL14_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_USHFRCOCAL14_VREFTC_SHIFT   28
 
#define _DEVINFO_USHFRCOCAL7_CLKDIV_MASK   0x6000000UL
 
#define _DEVINFO_USHFRCOCAL7_CLKDIV_SHIFT   25
 
#define _DEVINFO_USHFRCOCAL7_CMPBIAS_MASK   0xE00000UL
 
#define _DEVINFO_USHFRCOCAL7_CMPBIAS_SHIFT   21
 
#define _DEVINFO_USHFRCOCAL7_FINETUNING_MASK   0x3F00UL
 
#define _DEVINFO_USHFRCOCAL7_FINETUNING_SHIFT   8
 
#define _DEVINFO_USHFRCOCAL7_FINETUNINGEN_MASK   0x8000000UL
 
#define _DEVINFO_USHFRCOCAL7_FINETUNINGEN_SHIFT   27
 
#define _DEVINFO_USHFRCOCAL7_FREQRANGE_MASK   0x1F0000UL
 
#define _DEVINFO_USHFRCOCAL7_FREQRANGE_SHIFT   16
 
#define _DEVINFO_USHFRCOCAL7_LDOHP_MASK   0x1000000UL
 
#define _DEVINFO_USHFRCOCAL7_LDOHP_SHIFT   24
 
#define _DEVINFO_USHFRCOCAL7_MASK   0xFFFF3F7FUL
 
#define _DEVINFO_USHFRCOCAL7_TUNING_MASK   0x7FUL
 
#define _DEVINFO_USHFRCOCAL7_TUNING_SHIFT   0
 
#define _DEVINFO_USHFRCOCAL7_VREFTC_MASK   0xF0000000UL
 
#define _DEVINFO_USHFRCOCAL7_VREFTC_SHIFT   28
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK   0x3F000UL
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT   12
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK   0x3FUL
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT   0
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK   0xFC0000UL
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT   18
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK   0xFC0UL
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT   6
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK   0x3F000000UL
 
#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT   24
 
#define _DEVINFO_VDAC0ALTCAL_MASK   0x3FFFFFFFUL
 
#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK   0xF0UL
 
#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT   4
 
#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK   0xF00UL
 
#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT   8
 
#define _DEVINFO_VDAC0CH1CAL_MASK   0x00000FF7UL
 
#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK   0x7UL
 
#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT   0
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK   0x3F000UL
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT   12
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK   0x3FUL
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT   0
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK   0xFC0000UL
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT   18
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK   0xFC0UL
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT   6
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK   0x3F000000UL
 
#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT   24
 
#define _DEVINFO_VDAC0MAINCAL_MASK   0x3FFFFFFFUL
 
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK   0xF00000UL
 
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT   20
 
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK   0xF0000UL
 
#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT   16
 
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK   0xF0000000UL
 
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT   28
 
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK   0xF000000UL
 
#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT   24
 
#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK   0xF0UL
 
#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT   4
 
#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK   0xFUL
 
#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT   0
 
#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK   0xF000UL
 
#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT   12
 
#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK   0xF00UL
 
#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT   8
 
#define _DEVINFO_VMONCAL0_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK   0xF0UL
 
#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT   4
 
#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK   0xFUL
 
#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT   0
 
#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK   0xF000UL
 
#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT   12
 
#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK   0xF00UL
 
#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT   8
 
#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK   0xF00000UL
 
#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT   20
 
#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK   0xF0000UL
 
#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT   16
 
#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK   0xF0000000UL
 
#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT   28
 
#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK   0xF000000UL
 
#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT   24
 
#define _DEVINFO_VMONCAL1_MASK   0xFFFFFFFFUL
 
#define _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK   0xF0UL
 
#define _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT   4
 
#define _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK   0xFUL
 
#define _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT   0
 
#define _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK   0xF000UL
 
#define _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT   12
 
#define _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK   0xF00UL
 
#define _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT   8
 
#define _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK   0xF00000UL
 
#define _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT   20
 
#define _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK   0xF0000UL
 
#define _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT   16
 
#define _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK   0xF0000000UL
 
#define _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT   28
 
#define _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK   0xF000000UL
 
#define _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT   24
 
#define _DEVINFO_VMONCAL2_MASK   0xFFFFFFFFUL
 
#define DEVINFO_MEMINFO_PKGTYPE_BGA   (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8)
 
#define DEVINFO_MEMINFO_PKGTYPE_QFN   (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8)
 
#define DEVINFO_MEMINFO_PKGTYPE_QFP   (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8)
 
#define DEVINFO_MEMINFO_PKGTYPE_WLCSP   (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)
 
#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70   (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)
 
#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105   (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0)
 
#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125   (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0)
 
#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85   (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32G   (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG   (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B   (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG   (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B   (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B   (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG   (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B   (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B   (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG   (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B   (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG   (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG   (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V   (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG   (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG   (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG   (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_G   (_DEVINFO_PART_DEVICE_FAMILY_G << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_GG   (_DEVINFO_PART_DEVICE_FAMILY_GG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_HG   (_DEVINFO_PART_DEVICE_FAMILY_HG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_LG   (_DEVINFO_PART_DEVICE_FAMILY_LG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_TG   (_DEVINFO_PART_DEVICE_FAMILY_TG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_WG   (_DEVINFO_PART_DEVICE_FAMILY_WG << 16)
 
#define DEVINFO_PART_DEVICE_FAMILY_ZG   (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16)
 

Macro Definition Documentation

#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK   0x7F00UL

Bit mask for GAIN1V25

Definition at line 384 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT   8

Shift value for GAIN1V25

Definition at line 383 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK   0x7F000000UL

Bit mask for GAIN2V5

Definition at line 390 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT   24

Shift value for GAIN2V5

Definition at line 389 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_MASK   0x7FFF7FFFUL

Mask for DEVINFO_ADC0CAL0

Definition at line 378 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK   0xF0UL

Bit mask for NEGSEOFFSET1V25

Definition at line 382 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT   4

Shift value for NEGSEOFFSET1V25

Definition at line 381 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK   0xF00000UL

Bit mask for NEGSEOFFSET2V5

Definition at line 388 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT   20

Shift value for NEGSEOFFSET2V5

Definition at line 387 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK   0xFUL

Bit mask for OFFSET1V25

Definition at line 380 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT   0

Shift value for OFFSET1V25

Definition at line 379 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK   0xF0000UL

Bit mask for OFFSET2V5

Definition at line 386 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT   16

Shift value for OFFSET2V5

Definition at line 385 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK   0x7F000000UL

Bit mask for GAIN5VDIFF

Definition at line 405 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT   24

Shift value for GAIN5VDIFF

Definition at line 404 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_GAINVDD_MASK   0x7F00UL

Bit mask for GAINVDD

Definition at line 399 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT   8

Shift value for GAINVDD

Definition at line 398 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_MASK   0x7FFF7FFFUL

Mask for DEVINFO_ADC0CAL1

Definition at line 393 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK   0xF00000UL

Bit mask for NEGSEOFFSET5VDIFF

Definition at line 403 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT   20

Shift value for NEGSEOFFSET5VDIFF

Definition at line 402 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK   0xF0UL

Bit mask for NEGSEOFFSETVDD

Definition at line 397 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT   4

Shift value for NEGSEOFFSETVDD

Definition at line 396 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK   0xF0000UL

Bit mask for OFFSET5VDIFF

Definition at line 401 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT   16

Shift value for OFFSET5VDIFF

Definition at line 400 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK   0xFUL

Bit mask for OFFSETVDD

Definition at line 395 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT   0

Shift value for OFFSETVDD

Definition at line 394 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL2_MASK   0x000000FFUL

Mask for DEVINFO_ADC0CAL2

Definition at line 408 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK   0xF0UL

Bit mask for NEGSEOFFSET2XVDD

Definition at line 412 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT   4

Shift value for NEGSEOFFSET2XVDD

Definition at line 411 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK   0xFUL

Bit mask for OFFSET2XVDD

Definition at line 410 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT   0

Shift value for OFFSET2XVDD

Definition at line 409 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL3_MASK   0x0000FFF0UL

Mask for DEVINFO_ADC0CAL3

Definition at line 415 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK   0xFFF0UL

Bit mask for TEMPREAD1V25

Definition at line 417 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT   4

Shift value for TEMPREAD1V25

Definition at line 416 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_GAIN1V25_MASK   0x7F00UL

Bit mask for GAIN1V25

Definition at line 426 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_GAIN1V25_SHIFT   8

Shift value for GAIN1V25

Definition at line 425 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_GAIN2V5_MASK   0x7F000000UL

Bit mask for GAIN2V5

Definition at line 432 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_GAIN2V5_SHIFT   24

Shift value for GAIN2V5

Definition at line 431 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_MASK   0x7FFF7FFFUL

Mask for DEVINFO_ADC1CAL0

Definition at line 420 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_MASK   0xF0UL

Bit mask for NEGSEOFFSET1V25

Definition at line 424 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_NEGSEOFFSET1V25_SHIFT   4

Shift value for NEGSEOFFSET1V25

Definition at line 423 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_MASK   0xF00000UL

Bit mask for NEGSEOFFSET2V5

Definition at line 430 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_NEGSEOFFSET2V5_SHIFT   20

Shift value for NEGSEOFFSET2V5

Definition at line 429 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_OFFSET1V25_MASK   0xFUL

Bit mask for OFFSET1V25

Definition at line 422 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_OFFSET1V25_SHIFT   0

Shift value for OFFSET1V25

Definition at line 421 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_OFFSET2V5_MASK   0xF0000UL

Bit mask for OFFSET2V5

Definition at line 428 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL0_OFFSET2V5_SHIFT   16

Shift value for OFFSET2V5

Definition at line 427 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_GAIN5VDIFF_MASK   0x7F000000UL

Bit mask for GAIN5VDIFF

Definition at line 447 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_GAIN5VDIFF_SHIFT   24

Shift value for GAIN5VDIFF

Definition at line 446 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_GAINVDD_MASK   0x7F00UL

Bit mask for GAINVDD

Definition at line 441 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_GAINVDD_SHIFT   8

Shift value for GAINVDD

Definition at line 440 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_MASK   0x7FFF7FFFUL

Mask for DEVINFO_ADC1CAL1

Definition at line 435 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_MASK   0xF00000UL

Bit mask for NEGSEOFFSET5VDIFF

Definition at line 445 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_NEGSEOFFSET5VDIFF_SHIFT   20

Shift value for NEGSEOFFSET5VDIFF

Definition at line 444 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_MASK   0xF0UL

Bit mask for NEGSEOFFSETVDD

Definition at line 439 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_NEGSEOFFSETVDD_SHIFT   4

Shift value for NEGSEOFFSETVDD

Definition at line 438 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_MASK   0xF0000UL

Bit mask for OFFSET5VDIFF

Definition at line 443 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_OFFSET5VDIFF_SHIFT   16

Shift value for OFFSET5VDIFF

Definition at line 442 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_OFFSETVDD_MASK   0xFUL

Bit mask for OFFSETVDD

Definition at line 437 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL1_OFFSETVDD_SHIFT   0

Shift value for OFFSETVDD

Definition at line 436 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL2_MASK   0x000000FFUL

Mask for DEVINFO_ADC1CAL2

Definition at line 450 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_MASK   0xF0UL

Bit mask for NEGSEOFFSET2XVDD

Definition at line 454 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL2_NEGSEOFFSET2XVDD_SHIFT   4

Shift value for NEGSEOFFSET2XVDD

Definition at line 453 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL2_OFFSET2XVDD_MASK   0xFUL

Bit mask for OFFSET2XVDD

Definition at line 452 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL2_OFFSET2XVDD_SHIFT   0

Shift value for OFFSET2XVDD

Definition at line 451 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL3_MASK   0x0000FFF0UL

Mask for DEVINFO_ADC1CAL3

Definition at line 457 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL3_TEMPREAD1V25_MASK   0xFFF0UL

Bit mask for TEMPREAD1V25

Definition at line 459 of file efm32gg11b_devinfo.h.

#define _DEVINFO_ADC1CAL3_TEMPREAD1V25_SHIFT   4

Shift value for TEMPREAD1V25

Definition at line 458 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 702 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 701 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 698 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 697 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 694 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 693 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 704 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 703 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 696 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 695 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 700 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 699 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL0

Definition at line 690 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 692 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 691 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 706 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 705 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 797 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 796 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 793 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 792 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 789 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 788 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 799 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 798 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 791 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 790 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 795 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 794 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL10

Definition at line 785 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 787 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 786 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 801 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 800 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 816 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 815 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 812 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 811 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 808 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 807 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 818 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 817 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 810 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 809 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 814 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 813 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL11

Definition at line 804 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 806 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 805 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 820 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 819 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 835 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 834 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 831 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 830 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 827 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 826 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 837 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 836 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 829 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 828 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 833 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 832 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL12

Definition at line 823 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 825 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 824 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 839 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 838 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 854 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 853 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 850 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 849 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 846 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 845 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 856 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 855 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 848 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 847 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 852 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 851 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL13

Definition at line 842 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 844 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 843 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 858 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL13_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 857 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 873 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 872 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 869 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 868 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 865 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 864 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 875 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 874 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 867 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 866 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 871 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 870 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL14

Definition at line 861 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 863 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 862 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 877 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL14_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 876 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 721 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 720 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 717 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 716 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 713 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 712 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 723 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 722 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 715 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 714 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 719 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 718 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL3

Definition at line 709 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 711 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 710 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 725 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 724 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 740 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 739 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 736 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 735 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 732 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 731 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 742 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 741 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 734 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 733 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 738 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 737 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL6

Definition at line 728 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 730 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 729 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 744 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 743 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 759 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 758 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 755 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 754 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 751 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 750 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 761 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 760 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 753 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 752 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 757 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 756 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL7

Definition at line 747 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 749 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 748 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 763 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 762 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 778 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 777 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 774 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 773 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 770 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 769 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 780 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 779 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 772 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 771 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 776 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 775 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_MASK   0xFFFF3F7FUL

Mask for DEVINFO_AUXHFRCOCAL8

Definition at line 766 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 768 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 767 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 782 of file efm32gg11b_devinfo.h.

#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 781 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CAL_CRC_MASK   0xFFFFUL

Bit mask for CRC

Definition at line 173 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CAL_CRC_SHIFT   0

Shift value for CRC

Definition at line 172 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CAL_MASK   0x00FFFFFFUL

Mask for DEVINFO_CAL

Definition at line 171 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CAL_TEMP_MASK   0xFF0000UL

Bit mask for TEMP

Definition at line 175 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetCalibrationTemperature(), and TEMPDRV_Init().

#define _DEVINFO_CAL_TEMP_SHIFT   16

Shift value for TEMP

Definition at line 174 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetCalibrationTemperature(), and TEMPDRV_Init().

#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK   0xFFUL

Bit mask for GAINCAL

Definition at line 1613 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT   0

Shift value for GAINCAL

Definition at line 1612 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CSENGAINCAL_MASK   0x000000FFUL

Mask for DEVINFO_CSENGAINCAL

Definition at line 1611 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CURRMON5V_MASK   0x00000000UL

Mask for DEVINFO_CURRMON5V

Definition at line 1692 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CUSTOMINFO_MASK   0xFFFF0000UL

Mask for DEVINFO_CUSTOMINFO

Definition at line 190 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CUSTOMINFO_PARTNO_MASK   0xFFFF0000UL

Bit mask for PARTNO

Definition at line 192 of file efm32gg11b_devinfo.h.

#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT   16

Shift value for PARTNO

Definition at line 191 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK   0xFFUL

Bit mask for 1V2LNATT0

Definition at line 961 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT   0

Shift value for 1V2LNATT0

Definition at line 960 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK   0xFF00UL

Bit mask for 1V8LNATT0

Definition at line 963 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT   8

Shift value for 1V8LNATT0

Definition at line 962 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK   0xFF0000UL

Bit mask for 1V8LNATT1

Definition at line 965 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT   16

Shift value for 1V8LNATT1

Definition at line 964 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK   0xFF000000UL

Bit mask for 3V0LNATT1

Definition at line 967 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT   24

Shift value for 3V0LNATT1

Definition at line 966 of file efm32gg11b_devinfo.h.

Referenced by EMU_DCDCOutputVoltageSet().

#define _DEVINFO_DCDCLNVCTRL0_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLNVCTRL0

Definition at line 959 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK   0xFFUL

Bit mask for LPCMPHYSSELLPATT0

Definition at line 1016 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT   0

Shift value for LPCMPHYSSELLPATT0

Definition at line 1015 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK   0xFF00UL

Bit mask for LPCMPHYSSELLPATT1

Definition at line 1018 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT   8

Shift value for LPCMPHYSSELLPATT1

Definition at line 1017 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK   0x0000FFFFUL

Mask for DEVINFO_DCDCLPCMPHYSSEL0

Definition at line 1014 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK   0xFFUL

Bit mask for LPCMPHYSSELLPCMPBIAS0

Definition at line 1023 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT   0

Shift value for LPCMPHYSSELLPCMPBIAS0

Definition at line 1022 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK   0xFF00UL

Bit mask for LPCMPHYSSELLPCMPBIAS1

Definition at line 1025 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT   8

Shift value for LPCMPHYSSELLPCMPBIAS1

Definition at line 1024 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK   0xFF0000UL

Bit mask for LPCMPHYSSELLPCMPBIAS2

Definition at line 1027 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT   16

Shift value for LPCMPHYSSELLPCMPBIAS2

Definition at line 1026 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK   0xFF000000UL

Bit mask for LPCMPHYSSELLPCMPBIAS3

Definition at line 1029 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT   24

Shift value for LPCMPHYSSELLPCMPBIAS3

Definition at line 1028 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPCMPHYSSEL1

Definition at line 1021 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK   0xFFUL

Bit mask for 1V2LPATT0LPCMPBIAS0

Definition at line 972 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT   0

Shift value for 1V2LPATT0LPCMPBIAS0

Definition at line 971 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK   0xFF0000UL

Bit mask for 1V2LPATT0LPCMPBIAS1

Definition at line 976 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT   16

Shift value for 1V2LPATT0LPCMPBIAS1

Definition at line 975 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK   0xFF00UL

Bit mask for 1V8LPATT0LPCMPBIAS0

Definition at line 974 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT   8

Shift value for 1V8LPATT0LPCMPBIAS0

Definition at line 973 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK   0xFF000000UL

Bit mask for 1V8LPATT0LPCMPBIAS1

Definition at line 978 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT   24

Shift value for 1V8LPATT0LPCMPBIAS1

Definition at line 977 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL0_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL0

Definition at line 970 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK   0xFFUL

Bit mask for 1V2LPATT0LPCMPBIAS2

Definition at line 983 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT   0

Shift value for 1V2LPATT0LPCMPBIAS2

Definition at line 982 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK   0xFF0000UL

Bit mask for 1V2LPATT0LPCMPBIAS3

Definition at line 987 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT   16

Shift value for 1V2LPATT0LPCMPBIAS3

Definition at line 986 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK   0xFF00UL

Bit mask for 1V8LPATT0LPCMPBIAS2

Definition at line 985 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT   8

Shift value for 1V8LPATT0LPCMPBIAS2

Definition at line 984 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK   0xFF000000UL

Bit mask for 1V8LPATT0LPCMPBIAS3

Definition at line 989 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT   24

Shift value for 1V8LPATT0LPCMPBIAS3

Definition at line 988 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL1_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL1

Definition at line 981 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK   0xFFUL

Bit mask for 1V8LPATT1LPCMPBIAS0

Definition at line 994 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT   0

Shift value for 1V8LPATT1LPCMPBIAS0

Definition at line 993 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK   0xFF0000UL

Bit mask for 1V8LPATT1LPCMPBIAS1

Definition at line 998 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT   16

Shift value for 1V8LPATT1LPCMPBIAS1

Definition at line 997 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK   0xFF00UL

Bit mask for 3V0LPATT1LPCMPBIAS0

Definition at line 996 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT   8

Shift value for 3V0LPATT1LPCMPBIAS0

Definition at line 995 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK   0xFF000000UL

Bit mask for 3V0LPATT1LPCMPBIAS1

Definition at line 1000 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT   24

Shift value for 3V0LPATT1LPCMPBIAS1

Definition at line 999 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL2_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL2

Definition at line 992 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK   0xFFUL

Bit mask for 1V8LPATT1LPCMPBIAS2

Definition at line 1005 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT   0

Shift value for 1V8LPATT1LPCMPBIAS2

Definition at line 1004 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK   0xFF0000UL

Bit mask for 1V8LPATT1LPCMPBIAS3

Definition at line 1009 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT   16

Shift value for 1V8LPATT1LPCMPBIAS3

Definition at line 1008 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK   0xFF00UL

Bit mask for 3V0LPATT1LPCMPBIAS2

Definition at line 1007 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT   8

Shift value for 3V0LPATT1LPCMPBIAS2

Definition at line 1006 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK   0xFF000000UL

Bit mask for 3V0LPATT1LPCMPBIAS3

Definition at line 1011 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT   24

Shift value for 3V0LPATT1LPCMPBIAS3

Definition at line 1010 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DCDCLPVCTRL3_MASK   0xFFFFFFFFUL

Mask for DEVINFO_DCDCLPVCTRL3

Definition at line 1003 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DEVINFOREV_MAJOR_MASK   0xE0UL

Bit mask for MAJOR

Definition at line 370 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DEVINFOREV_MAJOR_SHIFT   5

Shift value for MAJOR

Definition at line 369 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DEVINFOREV_MASK   0x000000FFUL

Mask for DEVINFO_DEVINFOREV

Definition at line 366 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DEVINFOREV_MINOR_MASK   0x1FUL

Bit mask for MINOR

Definition at line 368 of file efm32gg11b_devinfo.h.

#define _DEVINFO_DEVINFOREV_MINOR_SHIFT   0

Shift value for MINOR

Definition at line 367 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK   0xFFUL

Bit mask for EMUTEMPROOM

Definition at line 375 of file efm32gg11b_devinfo.h.

Referenced by TEMPDRV_Init().

#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT   0

Shift value for EMUTEMPROOM

Definition at line 374 of file efm32gg11b_devinfo.h.

Referenced by TEMPDRV_Init().

#define _DEVINFO_EMUTEMP_MASK   0x000000FFUL

Mask for DEVINFO_EMUTEMP

Definition at line 373 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48H_MASK   0x0000FFFFUL

Mask for DEVINFO_EUI48H

Definition at line 185 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48H_OUI48H_MASK   0xFFFFUL

Bit mask for OUI48H

Definition at line 187 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48H_OUI48H_SHIFT   0

Shift value for OUI48H

Definition at line 186 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48L_MASK   0xFFFFFFFFUL

Mask for DEVINFO_EUI48L

Definition at line 178 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48L_OUI48L_MASK   0xFF000000UL

Bit mask for OUI48L

Definition at line 182 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48L_OUI48L_SHIFT   24

Shift value for OUI48L

Definition at line 181 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48L_UNIQUEID_MASK   0xFFFFFFUL

Bit mask for UNIQUEID

Definition at line 180 of file efm32gg11b_devinfo.h.

#define _DEVINFO_EUI48L_UNIQUEID_SHIFT   0

Shift value for UNIQUEID

Definition at line 179 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 474 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 473 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 470 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 469 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 466 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 465 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 476 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 475 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 468 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 467 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 472 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 471 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL0

Definition at line 462 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 464 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 463 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 478 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 477 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 569 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 568 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 565 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 564 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 561 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 560 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 571 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 570 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 563 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 562 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 567 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 566 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL10

Definition at line 557 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 559 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 558 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 573 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 572 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 588 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 587 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 584 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 583 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 580 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 579 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 590 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 589 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 582 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 581 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 586 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 585 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL11

Definition at line 576 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 578 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 577 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 592 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 591 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 607 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 606 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 603 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 602 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 599 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 598 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 609 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 608 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 601 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 600 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 605 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 604 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL12

Definition at line 595 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 597 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 596 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 611 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 610 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 626 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 625 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 622 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 621 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 618 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 617 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 628 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 627 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 620 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 619 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 624 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 623 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL13

Definition at line 614 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 616 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 615 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 630 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL13_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 629 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 645 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 644 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 641 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 640 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 637 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 636 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 647 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 646 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 639 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 638 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 643 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 642 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL14

Definition at line 633 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 635 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 634 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 649 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL14_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 648 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 664 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 663 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 660 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 659 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 656 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 655 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 666 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 665 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 658 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 657 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 662 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 661 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL15

Definition at line 652 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 654 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 653 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 668 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL15_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 667 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 683 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 682 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 679 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 678 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 675 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 674 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 685 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 684 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 677 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 676 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 681 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 680 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL16

Definition at line 671 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 673 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 672 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 687 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL16_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 686 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 493 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 492 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 489 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 488 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 485 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 484 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 495 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 494 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 487 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 486 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 491 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 490 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL3

Definition at line 481 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 483 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 482 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 497 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 496 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 512 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 511 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 508 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 507 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 504 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 503 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 514 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 513 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 506 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 505 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 510 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 509 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL6

Definition at line 500 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 502 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 501 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 516 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 515 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 531 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 530 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 527 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 526 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 523 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 522 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 533 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 532 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 525 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 524 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 529 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 528 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL7

Definition at line 519 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 521 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 520 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 535 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 534 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK   0x6000000UL

Bit mask for CLKDIV

Definition at line 550 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT   25

Shift value for CLKDIV

Definition at line 549 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK   0xE00000UL

Bit mask for CMPBIAS

Definition at line 546 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT   21

Shift value for CMPBIAS

Definition at line 545 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK   0x3F00UL

Bit mask for FINETUNING

Definition at line 542 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT   8

Shift value for FINETUNING

Definition at line 541 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK   0x8000000UL

Bit mask for FINETUNINGEN

Definition at line 552 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT   27

Shift value for FINETUNINGEN

Definition at line 551 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK   0x1F0000UL

Bit mask for FREQRANGE

Definition at line 544 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT   16

Shift value for FREQRANGE

Definition at line 543 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_LDOHP_MASK   0x1000000UL

Bit mask for LDOHP

Definition at line 548 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT   24

Shift value for LDOHP

Definition at line 547 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_MASK   0xFFFF3F7FUL

Mask for DEVINFO_HFRCOCAL8

Definition at line 538 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_TUNING_MASK   0x7FUL

Bit mask for TUNING

Definition at line 540 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT   0

Shift value for TUNING

Definition at line 539 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_VREFTC_MASK   0xF0000000UL

Bit mask for VREFTC

Definition at line 554 of file efm32gg11b_devinfo.h.

#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT   28

Shift value for VREFTC

Definition at line 553 of file efm32gg11b_devinfo.h.

#define _DEVINFO_IDAC0CAL0_MASK   0xFFFFFFFFUL

Mask for DEVINFO_IDAC0CAL0

Definition at line 937 of file efm32gg11b_devinfo.h.

#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK   0xFFUL

Bit mask for SOURCERANGE0TUNING

Definition at line 939 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT   0

Shift value for SOURCERANGE0TUNING

Definition at line 938 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK   0xFF00UL

Bit mask for SOURCERANGE1TUNING

Definition at line 941 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT   8

Shift value for SOURCERANGE1TUNING

Definition at line 940 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK   0xFF0000UL

Bit mask for SOURCERANGE2TUNING

Definition at line 943 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT   16

Shift value for SOURCERANGE2TUNING

Definition at line 942 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK   0xFF000000UL

Bit mask for SOURCERANGE3TUNING

Definition at line 945 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT   24

Shift value for SOURCERANGE3TUNING

Definition at line 944 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_MASK   0xFFFFFFFFUL

Mask for DEVINFO_IDAC0CAL1

Definition at line 948 of file efm32gg11b_devinfo.h.

#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK   0xFFUL

Bit mask for SINKRANGE0TUNING

Definition at line 950 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT   0

Shift value for SINKRANGE0TUNING

Definition at line 949 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK   0xFF00UL

Bit mask for SINKRANGE1TUNING

Definition at line 952 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT   8

Shift value for SINKRANGE1TUNING

Definition at line 951 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK   0xFF0000UL

Bit mask for SINKRANGE2TUNING

Definition at line 954 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT   16

Shift value for SINKRANGE2TUNING

Definition at line 953 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK   0xFF000000UL

Bit mask for SINKRANGE3TUNING

Definition at line 956 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT   24

Shift value for SINKRANGE3TUNING

Definition at line 955 of file efm32gg11b_devinfo.h.

Referenced by IDAC_RangeSet().

#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK   0xFF000000UL

Bit mask for FLASH_PAGE_SIZE

Definition at line 219 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetFlashPageSize().

#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT   24

Shift value for FLASH_PAGE_SIZE

Definition at line 218 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetFlashPageSize().

#define _DEVINFO_MEMINFO_MASK   0xFFFFFFFFUL

Mask for DEVINFO_MEMINFO

Definition at line 195 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PINCOUNT_MASK   0xFF0000UL

Bit mask for PINCOUNT

Definition at line 217 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT   16

Shift value for PINCOUNT

Definition at line 216 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PKGTYPE_BGA   0x0000004CUL

Mode BGA for DEVINFO_MEMINFO

Definition at line 209 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PKGTYPE_MASK   0xFF00UL

Bit mask for PKGTYPE

Definition at line 207 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PKGTYPE_QFN   0x0000004DUL

Mode QFN for DEVINFO_MEMINFO

Definition at line 210 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PKGTYPE_QFP   0x00000051UL

Mode QFP for DEVINFO_MEMINFO

Definition at line 211 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT   8

Shift value for PKGTYPE

Definition at line 206 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP   0x0000004AUL

Mode WLCSP for DEVINFO_MEMINFO

Definition at line 208 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_TEMPGRADE_MASK   0xFFUL

Bit mask for TEMPGRADE

Definition at line 197 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70   0x00000003UL

Mode N0TO70 for DEVINFO_MEMINFO

Definition at line 201 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105   0x00000002UL

Mode N40TO105 for DEVINFO_MEMINFO

Definition at line 200 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125   0x00000001UL

Mode N40TO125 for DEVINFO_MEMINFO

Definition at line 199 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85   0x00000000UL

Mode N40TO85 for DEVINFO_MEMINFO

Definition at line 198 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT   0

Shift value for TEMPGRADE

Definition at line 196 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MSIZE_FLASH_MASK   0xFFFFUL

Bit mask for FLASH

Definition at line 234 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetFlashSize(), and SYSTEM_GetSRAMSize().

#define _DEVINFO_MSIZE_FLASH_SHIFT   0

Shift value for FLASH

Definition at line 233 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetFlashSize(), and SYSTEM_GetSRAMSize().

#define _DEVINFO_MSIZE_MASK   0xFFFFFFFFUL

Mask for DEVINFO_MSIZE

Definition at line 232 of file efm32gg11b_devinfo.h.

#define _DEVINFO_MSIZE_SRAM_MASK   0xFFFF0000UL

Bit mask for SRAM

Definition at line 236 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetFlashSize(), and SYSTEM_GetSRAMSize().

#define _DEVINFO_MSIZE_SRAM_SHIFT   16

Shift value for SRAM

Definition at line 235 of file efm32gg11b_devinfo.h.

Referenced by SYSTEM_GetFlashSize(), and SYSTEM_GetSRAMSize().

#define _DEVINFO_OPA0CAL0_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1069 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_CM1_SHIFT   0

Shift value for CM1

Definition at line 1068 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1071 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_CM2_SHIFT   5

Shift value for CM2

Definition at line 1070 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1073 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_CM3_SHIFT   10

Shift value for CM3

Definition at line 1072 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1077 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_GM3_SHIFT   17

Shift value for GM3

Definition at line 1076 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1075 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_GM_SHIFT   13

Shift value for GM

Definition at line 1074 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL0

Definition at line 1067 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1081 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1080 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1079 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1078 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1086 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_CM1_SHIFT   0

Shift value for CM1

Definition at line 1085 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1088 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_CM2_SHIFT   5

Shift value for CM2

Definition at line 1087 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1090 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_CM3_SHIFT   10

Shift value for CM3

Definition at line 1089 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1094 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_GM3_SHIFT   17

Shift value for GM3

Definition at line 1093 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1092 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_GM_SHIFT   13

Shift value for GM

Definition at line 1091 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL1

Definition at line 1084 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1098 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1097 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1096 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1095 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1103 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_CM1_SHIFT   0

Shift value for CM1

Definition at line 1102 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1105 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_CM2_SHIFT   5

Shift value for CM2

Definition at line 1104 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1107 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_CM3_SHIFT   10

Shift value for CM3

Definition at line 1106 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1111 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_GM3_SHIFT   17

Shift value for GM3

Definition at line 1110 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1109 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_GM_SHIFT   13

Shift value for GM

Definition at line 1108 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL2

Definition at line 1101 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1115 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1114 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1113 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1112 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1120 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_CM1_SHIFT   0

Shift value for CM1

Definition at line 1119 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1122 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_CM2_SHIFT   5

Shift value for CM2

Definition at line 1121 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1124 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_CM3_SHIFT   10

Shift value for CM3

Definition at line 1123 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1128 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_GM3_SHIFT   17

Shift value for GM3

Definition at line 1127 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1126 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_GM_SHIFT   13

Shift value for GM

Definition at line 1125 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL3

Definition at line 1118 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1132 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1131 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1130 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1129 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1137 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_CM1_SHIFT   0

Shift value for CM1

Definition at line 1136 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1139 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_CM2_SHIFT   5

Shift value for CM2

Definition at line 1138 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1141 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_CM3_SHIFT   10

Shift value for CM3

Definition at line 1140 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1145 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_GM3_SHIFT   17

Shift value for GM3

Definition at line 1144 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1143 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_GM_SHIFT   13

Shift value for GM

Definition at line 1142 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL4

Definition at line 1135 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1149 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1148 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1147 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1146 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1154 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_CM1_SHIFT   0

Shift value for CM1

Definition at line 1153 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1156 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_CM2_SHIFT   5

Shift value for CM2

Definition at line 1155 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1158 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_CM3_SHIFT   10

Shift value for CM3

Definition at line 1157 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1162 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_GM3_SHIFT   17

Shift value for GM3

Definition at line 1161 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1160 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_GM_SHIFT   13

Shift value for GM

Definition at line 1159 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL5

Definition at line 1152 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1166 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1165 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1164 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1163 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1171 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_CM1_SHIFT   0

Shift value for CM1

Definition at line 1170 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1173 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_CM2_SHIFT   5

Shift value for CM2

Definition at line 1172 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1175 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_CM3_SHIFT   10

Shift value for CM3

Definition at line 1174 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1179 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_GM3_SHIFT   17

Shift value for GM3

Definition at line 1178 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1177 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_GM_SHIFT   13

Shift value for GM

Definition at line 1176 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL6

Definition at line 1169 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1183 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1182 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1181 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1180 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1188 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_CM1_SHIFT   0

Shift value for CM1

Definition at line 1187 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1190 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_CM2_SHIFT   5

Shift value for CM2

Definition at line 1189 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1192 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_CM3_SHIFT   10

Shift value for CM3

Definition at line 1191 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1196 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_GM3_SHIFT   17

Shift value for GM3

Definition at line 1195 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1194 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_GM_SHIFT   13

Shift value for GM

Definition at line 1193 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA0CAL7

Definition at line 1186 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1200 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1199 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1198 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1197 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1205 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_CM1_SHIFT   0

Shift value for CM1

Definition at line 1204 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1207 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_CM2_SHIFT   5

Shift value for CM2

Definition at line 1206 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1209 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_CM3_SHIFT   10

Shift value for CM3

Definition at line 1208 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1213 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_GM3_SHIFT   17

Shift value for GM3

Definition at line 1212 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1211 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_GM_SHIFT   13

Shift value for GM

Definition at line 1210 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL0

Definition at line 1203 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1217 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1216 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1215 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1214 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1222 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_CM1_SHIFT   0

Shift value for CM1

Definition at line 1221 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1224 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_CM2_SHIFT   5

Shift value for CM2

Definition at line 1223 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1226 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_CM3_SHIFT   10

Shift value for CM3

Definition at line 1225 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1230 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_GM3_SHIFT   17

Shift value for GM3

Definition at line 1229 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1228 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_GM_SHIFT   13

Shift value for GM

Definition at line 1227 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL1

Definition at line 1220 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1234 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1233 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1232 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1231 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1239 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_CM1_SHIFT   0

Shift value for CM1

Definition at line 1238 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1241 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_CM2_SHIFT   5

Shift value for CM2

Definition at line 1240 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1243 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_CM3_SHIFT   10

Shift value for CM3

Definition at line 1242 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1247 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_GM3_SHIFT   17

Shift value for GM3

Definition at line 1246 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1245 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_GM_SHIFT   13

Shift value for GM

Definition at line 1244 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL2

Definition at line 1237 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1251 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1250 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1249 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1248 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1256 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_CM1_SHIFT   0

Shift value for CM1

Definition at line 1255 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1258 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_CM2_SHIFT   5

Shift value for CM2

Definition at line 1257 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1260 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_CM3_SHIFT   10

Shift value for CM3

Definition at line 1259 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1264 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_GM3_SHIFT   17

Shift value for GM3

Definition at line 1263 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1262 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_GM_SHIFT   13

Shift value for GM

Definition at line 1261 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL3

Definition at line 1254 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1268 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1267 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1266 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1265 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1273 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_CM1_SHIFT   0

Shift value for CM1

Definition at line 1272 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1275 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_CM2_SHIFT   5

Shift value for CM2

Definition at line 1274 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1277 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_CM3_SHIFT   10

Shift value for CM3

Definition at line 1276 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1281 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_GM3_SHIFT   17

Shift value for GM3

Definition at line 1280 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1279 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_GM_SHIFT   13

Shift value for GM

Definition at line 1278 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL4

Definition at line 1271 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1285 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1284 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1283 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1282 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1290 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_CM1_SHIFT   0

Shift value for CM1

Definition at line 1289 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1292 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_CM2_SHIFT   5

Shift value for CM2

Definition at line 1291 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1294 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_CM3_SHIFT   10

Shift value for CM3

Definition at line 1293 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1298 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_GM3_SHIFT   17

Shift value for GM3

Definition at line 1297 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1296 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_GM_SHIFT   13

Shift value for GM

Definition at line 1295 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL5

Definition at line 1288 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1302 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1301 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1300 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1299 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1307 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_CM1_SHIFT   0

Shift value for CM1

Definition at line 1306 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1309 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_CM2_SHIFT   5

Shift value for CM2

Definition at line 1308 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1311 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_CM3_SHIFT   10

Shift value for CM3

Definition at line 1310 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1315 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_GM3_SHIFT   17

Shift value for GM3

Definition at line 1314 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1313 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_GM_SHIFT   13

Shift value for GM

Definition at line 1312 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL6

Definition at line 1305 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1319 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1318 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1317 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1316 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1324 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_CM1_SHIFT   0

Shift value for CM1

Definition at line 1323 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1326 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_CM2_SHIFT   5

Shift value for CM2

Definition at line 1325 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1328 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_CM3_SHIFT   10

Shift value for CM3

Definition at line 1327 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1332 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_GM3_SHIFT   17

Shift value for GM3

Definition at line 1331 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1330 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_GM_SHIFT   13

Shift value for GM

Definition at line 1329 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA1CAL7

Definition at line 1322 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1336 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1335 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1334 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1333 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1341 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_CM1_SHIFT   0

Shift value for CM1

Definition at line 1340 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1343 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_CM2_SHIFT   5

Shift value for CM2

Definition at line 1342 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1345 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_CM3_SHIFT   10

Shift value for CM3

Definition at line 1344 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1349 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_GM3_SHIFT   17

Shift value for GM3

Definition at line 1348 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1347 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_GM_SHIFT   13

Shift value for GM

Definition at line 1346 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL0

Definition at line 1339 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1353 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1352 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1351 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1350 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1358 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_CM1_SHIFT   0

Shift value for CM1

Definition at line 1357 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1360 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_CM2_SHIFT   5

Shift value for CM2

Definition at line 1359 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1362 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_CM3_SHIFT   10

Shift value for CM3

Definition at line 1361 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1366 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_GM3_SHIFT   17

Shift value for GM3

Definition at line 1365 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1364 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_GM_SHIFT   13

Shift value for GM

Definition at line 1363 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL1

Definition at line 1356 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1370 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1369 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1368 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1367 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1375 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_CM1_SHIFT   0

Shift value for CM1

Definition at line 1374 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1377 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_CM2_SHIFT   5

Shift value for CM2

Definition at line 1376 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1379 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_CM3_SHIFT   10

Shift value for CM3

Definition at line 1378 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1383 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_GM3_SHIFT   17

Shift value for GM3

Definition at line 1382 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1381 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_GM_SHIFT   13

Shift value for GM

Definition at line 1380 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL2

Definition at line 1373 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1387 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1386 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1385 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1384 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1392 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_CM1_SHIFT   0

Shift value for CM1

Definition at line 1391 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1394 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_CM2_SHIFT   5

Shift value for CM2

Definition at line 1393 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1396 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_CM3_SHIFT   10

Shift value for CM3

Definition at line 1395 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1400 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_GM3_SHIFT   17

Shift value for GM3

Definition at line 1399 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1398 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_GM_SHIFT   13

Shift value for GM

Definition at line 1397 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL3

Definition at line 1390 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1404 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1403 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1402 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1401 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1409 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_CM1_SHIFT   0

Shift value for CM1

Definition at line 1408 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1411 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_CM2_SHIFT   5

Shift value for CM2

Definition at line 1410 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1413 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_CM3_SHIFT   10

Shift value for CM3

Definition at line 1412 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1417 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_GM3_SHIFT   17

Shift value for GM3

Definition at line 1416 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1415 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_GM_SHIFT   13

Shift value for GM

Definition at line 1414 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL4

Definition at line 1407 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1421 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1420 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1419 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1418 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1426 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_CM1_SHIFT   0

Shift value for CM1

Definition at line 1425 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1428 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_CM2_SHIFT   5

Shift value for CM2

Definition at line 1427 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1430 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_CM3_SHIFT   10

Shift value for CM3

Definition at line 1429 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1434 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_GM3_SHIFT   17

Shift value for GM3

Definition at line 1433 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1432 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_GM_SHIFT   13

Shift value for GM

Definition at line 1431 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL5

Definition at line 1424 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1438 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1437 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1436 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1435 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1443 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_CM1_SHIFT   0

Shift value for CM1

Definition at line 1442 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1445 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_CM2_SHIFT   5

Shift value for CM2

Definition at line 1444 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1447 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_CM3_SHIFT   10

Shift value for CM3

Definition at line 1446 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1451 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_GM3_SHIFT   17

Shift value for GM3

Definition at line 1450 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1449 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_GM_SHIFT   13

Shift value for GM

Definition at line 1448 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL6

Definition at line 1441 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1455 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1454 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1453 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1452 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1460 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_CM1_SHIFT   0

Shift value for CM1

Definition at line 1459 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1462 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_CM2_SHIFT   5

Shift value for CM2

Definition at line 1461 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1464 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_CM3_SHIFT   10

Shift value for CM3

Definition at line 1463 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1468 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_GM3_SHIFT   17

Shift value for GM3

Definition at line 1467 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1466 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_GM_SHIFT   13

Shift value for GM

Definition at line 1465 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA2CAL7

Definition at line 1458 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1472 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1471 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1470 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1469 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1477 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_CM1_SHIFT   0

Shift value for CM1

Definition at line 1476 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1479 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_CM2_SHIFT   5

Shift value for CM2

Definition at line 1478 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1481 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_CM3_SHIFT   10

Shift value for CM3

Definition at line 1480 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1485 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_GM3_SHIFT   17

Shift value for GM3

Definition at line 1484 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1483 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_GM_SHIFT   13

Shift value for GM

Definition at line 1482 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL0

Definition at line 1475 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1489 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1488 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1487 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL0_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1486 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1494 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_CM1_SHIFT   0

Shift value for CM1

Definition at line 1493 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1496 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_CM2_SHIFT   5

Shift value for CM2

Definition at line 1495 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1498 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_CM3_SHIFT   10

Shift value for CM3

Definition at line 1497 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1502 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_GM3_SHIFT   17

Shift value for GM3

Definition at line 1501 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1500 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_GM_SHIFT   13

Shift value for GM

Definition at line 1499 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL1

Definition at line 1492 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1506 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1505 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1504 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL1_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1503 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1511 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_CM1_SHIFT   0

Shift value for CM1

Definition at line 1510 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1513 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_CM2_SHIFT   5

Shift value for CM2

Definition at line 1512 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1515 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_CM3_SHIFT   10

Shift value for CM3

Definition at line 1514 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1519 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_GM3_SHIFT   17

Shift value for GM3

Definition at line 1518 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1517 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_GM_SHIFT   13

Shift value for GM

Definition at line 1516 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL2

Definition at line 1509 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1523 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1522 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1521 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL2_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1520 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1528 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_CM1_SHIFT   0

Shift value for CM1

Definition at line 1527 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1530 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_CM2_SHIFT   5

Shift value for CM2

Definition at line 1529 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1532 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_CM3_SHIFT   10

Shift value for CM3

Definition at line 1531 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1536 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_GM3_SHIFT   17

Shift value for GM3

Definition at line 1535 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1534 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_GM_SHIFT   13

Shift value for GM

Definition at line 1533 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL3

Definition at line 1526 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1540 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1539 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1538 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL3_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1537 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1545 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_CM1_SHIFT   0

Shift value for CM1

Definition at line 1544 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1547 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_CM2_SHIFT   5

Shift value for CM2

Definition at line 1546 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1549 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_CM3_SHIFT   10

Shift value for CM3

Definition at line 1548 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1553 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_GM3_SHIFT   17

Shift value for GM3

Definition at line 1552 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1551 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_GM_SHIFT   13

Shift value for GM

Definition at line 1550 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL4

Definition at line 1543 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1557 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1556 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1555 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL4_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1554 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1562 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_CM1_SHIFT   0

Shift value for CM1

Definition at line 1561 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1564 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_CM2_SHIFT   5

Shift value for CM2

Definition at line 1563 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1566 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_CM3_SHIFT   10

Shift value for CM3

Definition at line 1565 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1570 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_GM3_SHIFT   17

Shift value for GM3

Definition at line 1569 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1568 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_GM_SHIFT   13

Shift value for GM

Definition at line 1567 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL5

Definition at line 1560 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1574 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1573 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1572 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL5_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1571 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1579 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_CM1_SHIFT   0

Shift value for CM1

Definition at line 1578 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1581 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_CM2_SHIFT   5

Shift value for CM2

Definition at line 1580 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1583 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_CM3_SHIFT   10

Shift value for CM3

Definition at line 1582 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1587 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_GM3_SHIFT   17

Shift value for GM3

Definition at line 1586 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1585 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_GM_SHIFT   13

Shift value for GM

Definition at line 1584 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL6

Definition at line 1577 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1591 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1590 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1589 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL6_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1588 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_CM1_MASK   0xFUL

Bit mask for CM1

Definition at line 1596 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_CM1_SHIFT   0

Shift value for CM1

Definition at line 1595 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_CM2_MASK   0x1E0UL

Bit mask for CM2

Definition at line 1598 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_CM2_SHIFT   5

Shift value for CM2

Definition at line 1597 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_CM3_MASK   0xC00UL

Bit mask for CM3

Definition at line 1600 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_CM3_SHIFT   10

Shift value for CM3

Definition at line 1599 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_GM3_MASK   0x60000UL

Bit mask for GM3

Definition at line 1604 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_GM3_SHIFT   17

Shift value for GM3

Definition at line 1603 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_GM_MASK   0xE000UL

Bit mask for GM

Definition at line 1602 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_GM_SHIFT   13

Shift value for GM

Definition at line 1601 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_MASK   0x7DF6EDEFUL

Mask for DEVINFO_OPA3CAL7

Definition at line 1594 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_OFFSETN_MASK   0x7C000000UL

Bit mask for OFFSETN

Definition at line 1608 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_OFFSETN_SHIFT   26

Shift value for OFFSETN

Definition at line 1607 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_OFFSETP_MASK   0x1F00000UL

Bit mask for OFFSETP

Definition at line 1606 of file efm32gg11b_devinfo.h.

#define _DEVINFO_OPA3CAL7_OFFSETP_SHIFT   20

Shift value for OFFSETP

Definition at line 1605 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G   0x00000047UL

Mode EFM32G for DEVINFO_PART

Definition at line 280 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG   0x00000048UL

Mode EFM32GG for DEVINFO_PART

Definition at line 282 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B   0x00000064UL

Mode EFM32GG11B for DEVINFO_PART

Definition at line 298 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG   0x0000004DUL

Mode EFM32HG for DEVINFO_PART

Definition at line 293 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B   0x00000057UL

Mode EFM32JG12B for DEVINFO_PART

Definition at line 297 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B   0x00000053UL

Mode EFM32JG1B for DEVINFO_PART

Definition at line 295 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG   0x0000004AUL

Mode EFM32LG for DEVINFO_PART

Definition at line 286 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B   0x00000055UL

Mode EFM32PG12B for DEVINFO_PART

Definition at line 296 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B   0x00000051UL

Mode EFM32PG1B for DEVINFO_PART

Definition at line 294 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG   0x00000049UL

Mode EFM32TG for DEVINFO_PART

Definition at line 285 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B   0x00000067UL

Mode EFM32TG11B for DEVINFO_PART

Definition at line 299 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG   0x0000004BUL

Mode EFM32WG for DEVINFO_PART

Definition at line 288 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG   0x0000004CUL

Mode EFM32ZG for DEVINFO_PART

Definition at line 291 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B   0x00000020UL

Mode EFR32BG12B for DEVINFO_PART

Definition at line 257 of file efm32gg11b_devinfo.h.

#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P &