Macros
#define	_QSPI_CONFIG_CRCENABLE_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_CRCENABLE_MASK 0x20000000UL

#define	_QSPI_CONFIG_CRCENABLE_SHIFT 29

#define	_QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_DUALBYTEOPCODEEN_MASK 0x40000000UL

#define	_QSPI_CONFIG_DUALBYTEOPCODEEN_SHIFT 30

#define	_QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_ENABLEAHBDECODER_MASK 0x800000UL

#define	_QSPI_CONFIG_ENABLEAHBDECODER_SHIFT 23

#define	_QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_ENABLEDTRPROTOCOL_MASK 0x1000000UL

#define	_QSPI_CONFIG_ENABLEDTRPROTOCOL_SHIFT 24

#define	_QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_ENBAHBADDRREMAP_MASK 0x10000UL

#define	_QSPI_CONFIG_ENBAHBADDRREMAP_SHIFT 16

#define	_QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT 0x00000001UL

#define	_QSPI_CONFIG_ENBDIRACCCTLR_MASK 0x80UL

#define	_QSPI_CONFIG_ENBDIRACCCTLR_SHIFT 7

#define	_QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_ENBLEGACYIPMODE_MASK 0x100UL

#define	_QSPI_CONFIG_ENBLEGACYIPMODE_SHIFT 8

#define	_QSPI_CONFIG_ENBSPI_DEFAULT 0x00000001UL

#define	_QSPI_CONFIG_ENBSPI_MASK 0x1UL

#define	_QSPI_CONFIG_ENBSPI_SHIFT 0

#define	_QSPI_CONFIG_ENTERXIPMODE_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_ENTERXIPMODE_MASK 0x20000UL

#define	_QSPI_CONFIG_ENTERXIPMODE_SHIFT 17

#define	_QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_ENTERXIPMODEIMM_MASK 0x40000UL

#define	_QSPI_CONFIG_ENTERXIPMODEIMM_SHIFT 18

#define	_QSPI_CONFIG_IDLE_DEFAULT 0x00000001UL

#define	_QSPI_CONFIG_IDLE_MASK 0x80000000UL

#define	_QSPI_CONFIG_IDLE_SHIFT 31

#define	_QSPI_CONFIG_MASK 0xE3FF4F8FUL

#define	_QSPI_CONFIG_MSTRBAUDDIV_DEFAULT 0x0000000FUL

#define	_QSPI_CONFIG_MSTRBAUDDIV_MASK 0x780000UL

#define	_QSPI_CONFIG_MSTRBAUDDIV_SHIFT 19

#define	_QSPI_CONFIG_PERIPHCSLINES_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_PERIPHCSLINES_MASK 0xC00UL

#define	_QSPI_CONFIG_PERIPHCSLINES_SHIFT 10

#define	_QSPI_CONFIG_PERIPHSELDEC_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_PERIPHSELDEC_MASK 0x200UL

#define	_QSPI_CONFIG_PERIPHSELDEC_SHIFT 9

#define	_QSPI_CONFIG_PHYMODEENABLE_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_PHYMODEENABLE_MASK 0x8UL

#define	_QSPI_CONFIG_PHYMODEENABLE_SHIFT 3

#define	_QSPI_CONFIG_PIPELINEPHY_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_PIPELINEPHY_MASK 0x2000000UL

#define	_QSPI_CONFIG_PIPELINEPHY_SHIFT 25

#define	_QSPI_CONFIG_RESETVALUE 0x80780081UL

#define	_QSPI_CONFIG_SELCLKPHASE_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_SELCLKPHASE_MASK 0x4UL

#define	_QSPI_CONFIG_SELCLKPHASE_SHIFT 2

#define	_QSPI_CONFIG_SELCLKPOL_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_SELCLKPOL_MASK 0x2UL

#define	_QSPI_CONFIG_SELCLKPOL_SHIFT 1

#define	_QSPI_CONFIG_WRPROTFLASH_DEFAULT 0x00000000UL

#define	_QSPI_CONFIG_WRPROTFLASH_MASK 0x4000UL

#define	_QSPI_CONFIG_WRPROTFLASH_SHIFT 14

#define	_QSPI_CTRL_MASK 0x00000003UL

#define	_QSPI_CTRL_RESETVALUE 0x00000000UL

#define	_QSPI_CTRL_TXDLYMUXSEL_DEFAULT 0x00000000UL

#define	_QSPI_CTRL_TXDLYMUXSEL_LARGE 0x00000003UL

#define	_QSPI_CTRL_TXDLYMUXSEL_MASK 0x3UL

#define	_QSPI_CTRL_TXDLYMUXSEL_MEDIUM 0x00000002UL

#define	_QSPI_CTRL_TXDLYMUXSEL_NONE 0x00000000UL

#define	_QSPI_CTRL_TXDLYMUXSEL_SHIFT 0

#define	_QSPI_DEVDELAY_DAFTER_DEFAULT 0x00000000UL

#define	_QSPI_DEVDELAY_DAFTER_MASK 0xFF00UL

#define	_QSPI_DEVDELAY_DAFTER_SHIFT 8

#define	_QSPI_DEVDELAY_DBTWN_DEFAULT 0x00000000UL

#define	_QSPI_DEVDELAY_DBTWN_MASK 0xFF0000UL

#define	_QSPI_DEVDELAY_DBTWN_SHIFT 16

#define	_QSPI_DEVDELAY_DINIT_DEFAULT 0x00000000UL

#define	_QSPI_DEVDELAY_DINIT_MASK 0xFFUL

#define	_QSPI_DEVDELAY_DINIT_SHIFT 0

#define	_QSPI_DEVDELAY_DNSS_DEFAULT 0x00000000UL

#define	_QSPI_DEVDELAY_DNSS_MASK 0xFF000000UL

#define	_QSPI_DEVDELAY_DNSS_SHIFT 24

#define	_QSPI_DEVDELAY_MASK 0xFFFFFFFFUL

#define	_QSPI_DEVDELAY_RESETVALUE 0x00000000UL

#define	_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL

#define	_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12

#define	_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL

#define	_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16

#define	_QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRRDCONFIG_DDREN_MASK 0x400UL

#define	_QSPI_DEVINSTRRDCONFIG_DDREN_SHIFT 10

#define	_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_MASK 0x1F000000UL

#define	_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT 24

#define	_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_MASK 0x300UL

#define	_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT 8

#define	_QSPI_DEVINSTRRDCONFIG_MASK 0x1F1337FFUL

#define	_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_MASK 0x100000UL

#define	_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_SHIFT 20

#define	_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT 0x00000003UL

#define	_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_MASK 0xFFUL

#define	_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT 0

#define	_QSPI_DEVINSTRRDCONFIG_RESETVALUE 0x00000003UL

#define	_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL

#define	_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12

#define	_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL

#define	_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16

#define	_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_MASK 0x1F000000UL

#define	_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT 24

#define	_QSPI_DEVINSTRWRCONFIG_MASK 0x1F0331FFUL

#define	_QSPI_DEVINSTRWRCONFIG_RESETVALUE 0x00000002UL

#define	_QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT 0x00000000UL

#define	_QSPI_DEVINSTRWRCONFIG_WELDIS_MASK 0x100UL

#define	_QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT 8

#define	_QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT 0x00000002UL

#define	_QSPI_DEVINSTRWRCONFIG_WROPCODE_MASK 0xFFUL

#define	_QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT 0

#define	_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT 0x00000100UL

#define	_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_MASK 0xFFF0UL

#define	_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_SHIFT 4

#define	_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT 0x00000010UL

#define	_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_MASK 0x1F0000UL

#define	_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_SHIFT 16

#define	_QSPI_DEVSIZECONFIG_MASK 0x01FFFFFFUL

#define	_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT 0x00000000UL

#define	_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_MASK 0x600000UL

#define	_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_SHIFT 21

#define	_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT 0x00000000UL

#define	_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_MASK 0x1800000UL

#define	_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_SHIFT 23

#define	_QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT 0x00000002UL

#define	_QSPI_DEVSIZECONFIG_NUMADDRBYTES_MASK 0xFUL

#define	_QSPI_DEVSIZECONFIG_NUMADDRBYTES_SHIFT 0

#define	_QSPI_DEVSIZECONFIG_RESETVALUE 0x00101002UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_MASK 0x1UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_SHIFT 0

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_MASK 0xFF0000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_SHIFT 16

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_MASK 0xFF000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_SHIFT 24

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_MASK 0x6UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_SHIFT 1

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_MASK 0x7F00UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_SHIFT 8

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_MASK 0x8000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_SHIFT 15

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_MASK 0xF8UL

#define	_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_SHIFT 3

#define	_QSPI_DLLOBSERVABLELOWER_MASK 0xFFFFFFFFUL

#define	_QSPI_DLLOBSERVABLELOWER_RESETVALUE 0x00000000UL

#define	_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_MASK 0x7FUL

#define	_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_SHIFT 0

#define	_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_DEFAULT 0x00000000UL

#define	_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_MASK 0x7F0000UL

#define	_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_SHIFT 16

#define	_QSPI_DLLOBSERVABLEUPPER_MASK 0x007F007FUL

#define	_QSPI_DLLOBSERVABLEUPPER_RESETVALUE 0x00000000UL

#define	_QSPI_FLASHCMDADDR_ADDR_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDADDR_ADDR_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHCMDADDR_ADDR_SHIFT 0

#define	_QSPI_FLASHCMDADDR_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHCMDADDR_RESETVALUE 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_CMDEXEC_MASK 0x1UL

#define	_QSPI_FLASHCMDCTRL_CMDEXEC_SHIFT 0

#define	_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_MASK 0x2UL

#define	_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_SHIFT 1

#define	_QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_CMDOPCODE_MASK 0xFF000000UL

#define	_QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT 24

#define	_QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_ENBCOMDADDR_MASK 0x80000UL

#define	_QSPI_FLASHCMDCTRL_ENBCOMDADDR_SHIFT 19

#define	_QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_ENBMODEBIT_MASK 0x40000UL

#define	_QSPI_FLASHCMDCTRL_ENBMODEBIT_SHIFT 18

#define	_QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_ENBREADDATA_MASK 0x800000UL

#define	_QSPI_FLASHCMDCTRL_ENBREADDATA_SHIFT 23

#define	_QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_ENBWRITEDATA_MASK 0x8000UL

#define	_QSPI_FLASHCMDCTRL_ENBWRITEDATA_SHIFT 15

#define	_QSPI_FLASHCMDCTRL_MASK 0xFFFFFF87UL

#define	_QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_NUMADDRBYTES_MASK 0x30000UL

#define	_QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT 16

#define	_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_MASK 0xF80UL

#define	_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT 7

#define	_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_MASK 0x700000UL

#define	_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT 20

#define	_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_MASK 0x7000UL

#define	_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT 12

#define	_QSPI_FLASHCMDCTRL_RESETVALUE 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_MASK 0x4UL

#define	_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_SHIFT 2

#define	_QSPI_FLASHCOMMANDCTRLMEM_MASK 0x1FF7FF03UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_MASK 0x1FF00000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_SHIFT 20

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_MASK 0xFF00UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_SHIFT 8

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_MASK 0x2UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_SHIFT 1

#define	_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_MASK 0x70000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_SHIFT 16

#define	_QSPI_FLASHCOMMANDCTRLMEM_RESETVALUE 0x00000000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT 0x00000000UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_MASK 0x1UL

#define	_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_SHIFT 0

#define	_QSPI_FLASHRDDATALOWER_DATA_DEFAULT 0x00000000UL

#define	_QSPI_FLASHRDDATALOWER_DATA_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHRDDATALOWER_DATA_SHIFT 0

#define	_QSPI_FLASHRDDATALOWER_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHRDDATALOWER_RESETVALUE 0x00000000UL

#define	_QSPI_FLASHRDDATAUPPER_DATA_DEFAULT 0x00000000UL

#define	_QSPI_FLASHRDDATAUPPER_DATA_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHRDDATAUPPER_DATA_SHIFT 0

#define	_QSPI_FLASHRDDATAUPPER_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHRDDATAUPPER_RESETVALUE 0x00000000UL

#define	_QSPI_FLASHWRDATALOWER_DATA_DEFAULT 0x00000000UL

#define	_QSPI_FLASHWRDATALOWER_DATA_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHWRDATALOWER_DATA_SHIFT 0

#define	_QSPI_FLASHWRDATALOWER_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHWRDATALOWER_RESETVALUE 0x00000000UL

#define	_QSPI_FLASHWRDATAUPPER_DATA_DEFAULT 0x00000000UL

#define	_QSPI_FLASHWRDATAUPPER_DATA_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHWRDATAUPPER_DATA_SHIFT 0

#define	_QSPI_FLASHWRDATAUPPER_MASK 0xFFFFFFFFUL

#define	_QSPI_FLASHWRDATAUPPER_RESETVALUE 0x00000000UL

#define	_QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT 0x00000000UL

#define	_QSPI_INDAHBADDRTRIGGER_ADDR_MASK 0xFFFFFFFFUL

#define	_QSPI_INDAHBADDRTRIGGER_ADDR_SHIFT 0

#define	_QSPI_INDAHBADDRTRIGGER_MASK 0xFFFFFFFFUL

#define	_QSPI_INDAHBADDRTRIGGER_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_CANCEL_MASK 0x2UL

#define	_QSPI_INDIRECTREADXFERCTRL_CANCEL_SHIFT 1

#define	_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL

#define	_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_SHIFT 5

#define	_QSPI_INDIRECTREADXFERCTRL_MASK 0x000000FFUL

#define	_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL

#define	_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_SHIFT 6

#define	_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_MASK 0x10UL

#define	_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_SHIFT 4

#define	_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_MASK 0x4UL

#define	_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_SHIFT 2

#define	_QSPI_INDIRECTREADXFERCTRL_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_MASK 0x8UL

#define	_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_SHIFT 3

#define	_QSPI_INDIRECTREADXFERCTRL_START_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERCTRL_START_MASK 0x1UL

#define	_QSPI_INDIRECTREADXFERCTRL_START_SHIFT 0

#define	_QSPI_INDIRECTREADXFERNUMBYTES_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTREADXFERNUMBYTES_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_SHIFT 0

#define	_QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERSTART_ADDR_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTREADXFERSTART_ADDR_SHIFT 0

#define	_QSPI_INDIRECTREADXFERSTART_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTREADXFERSTART_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_SHIFT 0

#define	_QSPI_INDIRECTREADXFERWATERMARK_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTREADXFERWATERMARK_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT 0x00000004UL

#define	_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_MASK 0xFUL

#define	_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_SHIFT 0

#define	_QSPI_INDIRECTTRIGGERADDRRANGE_MASK 0x0000000FUL

#define	_QSPI_INDIRECTTRIGGERADDRRANGE_RESETVALUE 0x00000004UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_MASK 0x2UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_SHIFT 1

#define	_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_SHIFT 5

#define	_QSPI_INDIRECTWRITEXFERCTRL_MASK 0x000000F7UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_SHIFT 6

#define	_QSPI_INDIRECTWRITEXFERCTRL_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_START_MASK 0x1UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_START_SHIFT 0

#define	_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_MASK 0x10UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_SHIFT 4

#define	_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_MASK 0x4UL

#define	_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_SHIFT 2

#define	_QSPI_INDIRECTWRITEXFERNUMBYTES_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTWRITEXFERNUMBYTES_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_SHIFT 0

#define	_QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERSTART_ADDR_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTWRITEXFERSTART_ADDR_SHIFT 0

#define	_QSPI_INDIRECTWRITEXFERSTART_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTWRITEXFERSTART_RESETVALUE 0x00000000UL

#define	_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT 0xFFFFFFFFUL

#define	_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_SHIFT 0

#define	_QSPI_INDIRECTWRITEXFERWATERMARK_MASK 0xFFFFFFFFUL

#define	_QSPI_INDIRECTWRITEXFERWATERMARK_RESETVALUE 0xFFFFFFFFUL

#define	_QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_ILLEGALACCESSDETMASK_MASK 0x20UL

#define	_QSPI_IRQMASK_ILLEGALACCESSDETMASK_SHIFT 5

#define	_QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_INDIRECTOPDONEMASK_MASK 0x4UL

#define	_QSPI_IRQMASK_INDIRECTOPDONEMASK_SHIFT 2

#define	_QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_INDIRECTREADREJECTMASK_MASK 0x8UL

#define	_QSPI_IRQMASK_INDIRECTREADREJECTMASK_SHIFT 3

#define	_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_MASK 0x40UL

#define	_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_SHIFT 6

#define	_QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_INDRDSRAMFULLMASK_MASK 0x1000UL

#define	_QSPI_IRQMASK_INDRDSRAMFULLMASK_SHIFT 12

#define	_QSPI_IRQMASK_MASK 0x00077FFFUL

#define	_QSPI_IRQMASK_MODEMFAILMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_MODEMFAILMASK_MASK 0x1UL

#define	_QSPI_IRQMASK_MODEMFAILMASK_SHIFT 0

#define	_QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_POLLEXPINTMASK_MASK 0x2000UL

#define	_QSPI_IRQMASK_POLLEXPINTMASK_SHIFT 13

#define	_QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_PROTWRATTEMPTMASK_MASK 0x10UL

#define	_QSPI_IRQMASK_PROTWRATTEMPTMASK_SHIFT 4

#define	_QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_RECVOVERFLOWMASK_MASK 0x80UL

#define	_QSPI_IRQMASK_RECVOVERFLOWMASK_SHIFT 7

#define	_QSPI_IRQMASK_RESETVALUE 0x00000000UL

#define	_QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_RXCRCDATAERRMASK_MASK 0x10000UL

#define	_QSPI_IRQMASK_RXCRCDATAERRMASK_SHIFT 16

#define	_QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_RXCRCDATAVALMASK_MASK 0x20000UL

#define	_QSPI_IRQMASK_RXCRCDATAVALMASK_SHIFT 17

#define	_QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_RXFIFOFULLMASK_MASK 0x800UL

#define	_QSPI_IRQMASK_RXFIFOFULLMASK_SHIFT 11

#define	_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_MASK 0x400UL

#define	_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_SHIFT 10

#define	_QSPI_IRQMASK_STIGREQMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_STIGREQMASK_MASK 0x4000UL

#define	_QSPI_IRQMASK_STIGREQMASK_SHIFT 14

#define	_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_MASK 0x40000UL

#define	_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_SHIFT 18

#define	_QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_TXFIFOFULLMASK_MASK 0x200UL

#define	_QSPI_IRQMASK_TXFIFOFULLMASK_SHIFT 9

#define	_QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_TXFIFONOTFULLMASK_MASK 0x100UL

#define	_QSPI_IRQMASK_TXFIFONOTFULLMASK_SHIFT 8

#define	_QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT 0x00000000UL

#define	_QSPI_IRQMASK_UNDERFLOWDETMASK_MASK 0x2UL

#define	_QSPI_IRQMASK_UNDERFLOWDETMASK_SHIFT 1

#define	_QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_ILLEGALACCESSDET_MASK 0x20UL

#define	_QSPI_IRQSTATUS_ILLEGALACCESSDET_SHIFT 5

#define	_QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_INDIRECTOPDONE_MASK 0x4UL

#define	_QSPI_IRQSTATUS_INDIRECTOPDONE_SHIFT 2

#define	_QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_INDIRECTREADREJECT_MASK 0x8UL

#define	_QSPI_IRQSTATUS_INDIRECTREADREJECT_SHIFT 3

#define	_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_MASK 0x40UL

#define	_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_SHIFT 6

#define	_QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_INDRDSRAMFULL_MASK 0x1000UL

#define	_QSPI_IRQSTATUS_INDRDSRAMFULL_SHIFT 12

#define	_QSPI_IRQSTATUS_MASK 0x00077FFFUL

#define	_QSPI_IRQSTATUS_MODEMFAIL_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_MODEMFAIL_MASK 0x1UL

#define	_QSPI_IRQSTATUS_MODEMFAIL_SHIFT 0

#define	_QSPI_IRQSTATUS_POLLEXPINT_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_POLLEXPINT_MASK 0x2000UL

#define	_QSPI_IRQSTATUS_POLLEXPINT_SHIFT 13

#define	_QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_PROTWRATTEMPT_MASK 0x10UL

#define	_QSPI_IRQSTATUS_PROTWRATTEMPT_SHIFT 4

#define	_QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_RECVOVERFLOW_MASK 0x80UL

#define	_QSPI_IRQSTATUS_RECVOVERFLOW_SHIFT 7

#define	_QSPI_IRQSTATUS_RESETVALUE 0x00000000UL

#define	_QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_RXCRCDATAERR_MASK 0x10000UL

#define	_QSPI_IRQSTATUS_RXCRCDATAERR_SHIFT 16

#define	_QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_RXCRCDATAVAL_MASK 0x20000UL

#define	_QSPI_IRQSTATUS_RXCRCDATAVAL_SHIFT 17

#define	_QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_RXFIFOFULL_MASK 0x800UL

#define	_QSPI_IRQSTATUS_RXFIFOFULL_SHIFT 11

#define	_QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_RXFIFONOTEMPTY_MASK 0x400UL

#define	_QSPI_IRQSTATUS_RXFIFONOTEMPTY_SHIFT 10

#define	_QSPI_IRQSTATUS_STIGREQINT_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_STIGREQINT_MASK 0x4000UL

#define	_QSPI_IRQSTATUS_STIGREQINT_SHIFT 14

#define	_QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_TXCRCCHUNKBRK_MASK 0x40000UL

#define	_QSPI_IRQSTATUS_TXCRCCHUNKBRK_SHIFT 18

#define	_QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_TXFIFOFULL_MASK 0x200UL

#define	_QSPI_IRQSTATUS_TXFIFOFULL_SHIFT 9

#define	_QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_TXFIFONOTFULL_MASK 0x100UL

#define	_QSPI_IRQSTATUS_TXFIFONOTFULL_SHIFT 8

#define	_QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT 0x00000000UL

#define	_QSPI_IRQSTATUS_UNDERFLOWDET_MASK 0x2UL

#define	_QSPI_IRQSTATUS_UNDERFLOWDET_SHIFT 1

#define	_QSPI_LOWERWRPROT_MASK 0xFFFFFFFFUL

#define	_QSPI_LOWERWRPROT_RESETVALUE 0x00000000UL

#define	_QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL

#define	_QSPI_LOWERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL

#define	_QSPI_LOWERWRPROT_SUBSECTOR_SHIFT 0

#define	_QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT 0x00000002UL

#define	_QSPI_MODEBITCONFIG_CHUNKSIZE_MASK 0x700UL

#define	_QSPI_MODEBITCONFIG_CHUNKSIZE_SHIFT 8

#define	_QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT 0x00000000UL

#define	_QSPI_MODEBITCONFIG_CRCOUTENABLE_MASK 0x8000UL

#define	_QSPI_MODEBITCONFIG_CRCOUTENABLE_SHIFT 15

#define	_QSPI_MODEBITCONFIG_MASK 0xFFFF87FFUL

#define	_QSPI_MODEBITCONFIG_MODE_DEFAULT 0x00000000UL

#define	_QSPI_MODEBITCONFIG_MODE_MASK 0xFFUL

#define	_QSPI_MODEBITCONFIG_MODE_SHIFT 0

#define	_QSPI_MODEBITCONFIG_RESETVALUE 0x00000200UL

#define	_QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT 0x00000000UL

#define	_QSPI_MODEBITCONFIG_RXCRCDATALOW_MASK 0xFF000000UL

#define	_QSPI_MODEBITCONFIG_RXCRCDATALOW_SHIFT 24

#define	_QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT 0x00000000UL

#define	_QSPI_MODEBITCONFIG_RXCRCDATAUP_MASK 0xFF0000UL

#define	_QSPI_MODEBITCONFIG_RXCRCDATAUP_SHIFT 16

#define	_QSPI_MODULEID_CONF_DEFAULT 0x00000000UL

#define	_QSPI_MODULEID_CONF_MASK 0x3UL

#define	_QSPI_MODULEID_CONF_SHIFT 0

#define	_QSPI_MODULEID_FIXPATCH_DEFAULT 0x00000000UL

#define	_QSPI_MODULEID_FIXPATCH_MASK 0xFF000000UL

#define	_QSPI_MODULEID_FIXPATCH_SHIFT 24

#define	_QSPI_MODULEID_MASK 0xFFFFFF03UL

#define	_QSPI_MODULEID_MODULEID_DEFAULT 0x00000002UL

#define	_QSPI_MODULEID_MODULEID_MASK 0xFFFF00UL

#define	_QSPI_MODULEID_MODULEID_SHIFT 8

#define	_QSPI_MODULEID_RESETVALUE 0x00000200UL

#define	_QSPI_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL

#define	_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT 0xFFFFFFFFUL

#define	_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL

#define	_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_SHIFT 0

#define	_QSPI_NOOFPOLLSBEFEXP_RESETVALUE 0xFFFFFFFFUL

#define	_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT 0x000000FAUL

#define	_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_MASK 0xFF00UL

#define	_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_SHIFT 8

#define	_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT 0x00000013UL

#define	_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_MASK 0xFF000000UL

#define	_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_SHIFT 24

#define	_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT 0x00000000UL

#define	_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_MASK 0xFFUL

#define	_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_SHIFT 0

#define	_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT 0x000000EDUL

#define	_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_MASK 0xFF0000UL

#define	_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_SHIFT 16

#define	_QSPI_OPCODEEXTLOWER_MASK 0xFFFFFFFFUL

#define	_QSPI_OPCODEEXTLOWER_RESETVALUE 0x13EDFA00UL

#define	_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT 0x000000F9UL

#define	_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_MASK 0xFF0000UL

#define	_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_SHIFT 16

#define	_QSPI_OPCODEEXTUPPER_MASK 0xFFFF0000UL

#define	_QSPI_OPCODEEXTUPPER_RESETVALUE 0x06F90000UL

#define	_QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT 0x00000006UL

#define	_QSPI_OPCODEEXTUPPER_WELOPCODE_MASK 0xFF000000UL

#define	_QSPI_OPCODEEXTUPPER_WELOPCODE_SHIFT 24

#define	_QSPI_PHYCONFIGURATION_MASK 0xE07F007FUL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRESET_DEFAULT 0x00000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRESET_MASK 0x40000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRESET_SHIFT 30

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT 0x00000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_MASK 0x80000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_SHIFT 31

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_DEFAULT 0x00000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_MASK 0x20000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_SHIFT 29

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT 0x00000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_MASK 0x7FUL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_SHIFT 0

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT 0x00000000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_MASK 0x7F0000UL

#define	_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_SHIFT 16

#define	_QSPI_PHYCONFIGURATION_RESETVALUE 0x00000000UL

#define	_QSPI_PHYMASTERCONTROL_MASK 0x01F7007FUL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_DEFAULT 0x00000001UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_MASK 0x800000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_SHIFT 23

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_DEFAULT 0x00000000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_MASK 0x7FUL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_SHIFT 0

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_DEFAULT 0x00000000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_MASK 0x1000000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_SHIFT 24

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_DEFAULT 0x00000000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_MASK 0x70000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_SHIFT 16

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_DEFAULT 0x00000000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_MASK 0x700000UL

#define	_QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_SHIFT 20

#define	_QSPI_PHYMASTERCONTROL_RESETVALUE 0x00800000UL

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT 0x00000000UL

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_MASK 0xFFUL

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_SHIFT 0

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT 0x00000000UL

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_MASK 0xF0000UL

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_SHIFT 16

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT 0x00000000UL

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_MASK 0x100UL

#define	_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_SHIFT 8

#define	_QSPI_POLLINGFLASHSTATUS_MASK 0x000F01FFUL

#define	_QSPI_POLLINGFLASHSTATUS_RESETVALUE 0x00000000UL

#define	_QSPI_RDDATACAPTURE_BYPASS_DEFAULT 0x00000001UL

#define	_QSPI_RDDATACAPTURE_BYPASS_MASK 0x1UL

#define	_QSPI_RDDATACAPTURE_BYPASS_SHIFT 0

#define	_QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT 0x00000000UL

#define	_QSPI_RDDATACAPTURE_DDRREADDELAY_MASK 0xF0000UL

#define	_QSPI_RDDATACAPTURE_DDRREADDELAY_SHIFT 16

#define	_QSPI_RDDATACAPTURE_DELAY_DEFAULT 0x00000000UL

#define	_QSPI_RDDATACAPTURE_DELAY_MASK 0x1EUL

#define	_QSPI_RDDATACAPTURE_DELAY_SHIFT 1

#define	_QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT 0x00000000UL

#define	_QSPI_RDDATACAPTURE_DQSENABLE_MASK 0x100UL

#define	_QSPI_RDDATACAPTURE_DQSENABLE_SHIFT 8

#define	_QSPI_RDDATACAPTURE_MASK 0x000F011FUL

#define	_QSPI_RDDATACAPTURE_RESETVALUE 0x00000001UL

#define	_QSPI_REMAPADDR_MASK 0xFFFFFFFFUL

#define	_QSPI_REMAPADDR_RESETVALUE 0x00000000UL

#define	_QSPI_REMAPADDR_VALUE_DEFAULT 0x00000000UL

#define	_QSPI_REMAPADDR_VALUE_MASK 0xFFFFFFFFUL

#define	_QSPI_REMAPADDR_VALUE_SHIFT 0

#define	_QSPI_ROUTELOC0_MASK 0x00000003UL

#define	_QSPI_ROUTELOC0_QSPILOC_DEFAULT 0x00000000UL

#define	_QSPI_ROUTELOC0_QSPILOC_LOC0 0x00000000UL

#define	_QSPI_ROUTELOC0_QSPILOC_LOC1 0x00000001UL

#define	_QSPI_ROUTELOC0_QSPILOC_LOC2 0x00000002UL

#define	_QSPI_ROUTELOC0_QSPILOC_MASK 0x3UL

#define	_QSPI_ROUTELOC0_QSPILOC_SHIFT 0

#define	_QSPI_ROUTELOC0_RESETVALUE 0x00000000UL

#define	_QSPI_ROUTEPEN_CS0PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_CS0PEN_MASK 0x2UL

#define	_QSPI_ROUTEPEN_CS0PEN_SHIFT 1

#define	_QSPI_ROUTEPEN_CS1PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_CS1PEN_MASK 0x4UL

#define	_QSPI_ROUTEPEN_CS1PEN_SHIFT 2

#define	_QSPI_ROUTEPEN_DQ0PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ0PEN_MASK 0x20UL

#define	_QSPI_ROUTEPEN_DQ0PEN_SHIFT 5

#define	_QSPI_ROUTEPEN_DQ1PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ1PEN_MASK 0x40UL

#define	_QSPI_ROUTEPEN_DQ1PEN_SHIFT 6

#define	_QSPI_ROUTEPEN_DQ2PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ2PEN_MASK 0x80UL

#define	_QSPI_ROUTEPEN_DQ2PEN_SHIFT 7

#define	_QSPI_ROUTEPEN_DQ3PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ3PEN_MASK 0x100UL

#define	_QSPI_ROUTEPEN_DQ3PEN_SHIFT 8

#define	_QSPI_ROUTEPEN_DQ4PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ4PEN_MASK 0x200UL

#define	_QSPI_ROUTEPEN_DQ4PEN_SHIFT 9

#define	_QSPI_ROUTEPEN_DQ5PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ5PEN_MASK 0x400UL

#define	_QSPI_ROUTEPEN_DQ5PEN_SHIFT 10

#define	_QSPI_ROUTEPEN_DQ6PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ6PEN_MASK 0x800UL

#define	_QSPI_ROUTEPEN_DQ6PEN_SHIFT 11

#define	_QSPI_ROUTEPEN_DQ7PEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQ7PEN_MASK 0x1000UL

#define	_QSPI_ROUTEPEN_DQ7PEN_SHIFT 12

#define	_QSPI_ROUTEPEN_DQSPEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_DQSPEN_MASK 0x2000UL

#define	_QSPI_ROUTEPEN_DQSPEN_SHIFT 13

#define	_QSPI_ROUTEPEN_MASK 0x00007FE7UL

#define	_QSPI_ROUTEPEN_RESETVALUE 0x00000000UL

#define	_QSPI_ROUTEPEN_SCLKINPEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_SCLKINPEN_MASK 0x4000UL

#define	_QSPI_ROUTEPEN_SCLKINPEN_SHIFT 14

#define	_QSPI_ROUTEPEN_SCLKPEN_DEFAULT 0x00000000UL

#define	_QSPI_ROUTEPEN_SCLKPEN_MASK 0x1UL

#define	_QSPI_ROUTEPEN_SCLKPEN_SHIFT 0

#define	_QSPI_RXTHRESH_LEVEL_DEFAULT 0x00000001UL

#define	_QSPI_RXTHRESH_LEVEL_MASK 0x1FUL

#define	_QSPI_RXTHRESH_LEVEL_SHIFT 0

#define	_QSPI_RXTHRESH_MASK 0x0000001FUL

#define	_QSPI_RXTHRESH_RESETVALUE 0x00000001UL

#define	_QSPI_SRAMFILL_MASK 0xFFFFFFFFUL

#define	_QSPI_SRAMFILL_RESETVALUE 0x00000000UL

#define	_QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT 0x00000000UL

#define	_QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK 0xFFFFUL

#define	_QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT 0

#define	_QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT 0x00000000UL

#define	_QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK 0xFFFF0000UL

#define	_QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT 16

#define	_QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT 0x00000080UL

#define	_QSPI_SRAMPARTITIONCFG_ADDR_MASK 0xFFUL

#define	_QSPI_SRAMPARTITIONCFG_ADDR_SHIFT 0

#define	_QSPI_SRAMPARTITIONCFG_MASK 0x000000FFUL

#define	_QSPI_SRAMPARTITIONCFG_RESETVALUE 0x00000080UL

#define	_QSPI_TXTHRESH_LEVEL_DEFAULT 0x00000001UL

#define	_QSPI_TXTHRESH_LEVEL_MASK 0x1FUL

#define	_QSPI_TXTHRESH_LEVEL_SHIFT 0

#define	_QSPI_TXTHRESH_MASK 0x0000001FUL

#define	_QSPI_TXTHRESH_RESETVALUE 0x00000001UL

#define	_QSPI_UPPERWRPROT_MASK 0xFFFFFFFFUL

#define	_QSPI_UPPERWRPROT_RESETVALUE 0x00000000UL

#define	_QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL

#define	_QSPI_UPPERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL

#define	_QSPI_UPPERWRPROT_SUBSECTOR_SHIFT 0

#define	_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT 0x00000000UL

#define	_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_MASK 0x4000UL

#define	_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_SHIFT 14

#define	_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT 0x00000000UL

#define	_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_MASK 0x8000UL

#define	_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_SHIFT 15

#define	_QSPI_WRITECOMPLETIONCTRL_MASK 0xFFFFE7FFUL

#define	_QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT 0x00000005UL

#define	_QSPI_WRITECOMPLETIONCTRL_OPCODE_MASK 0xFFUL

#define	_QSPI_WRITECOMPLETIONCTRL_OPCODE_SHIFT 0

#define	_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT 0x00000001UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_MASK 0xFF0000UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_SHIFT 16

#define	_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT 0x00000000UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_MASK 0x700UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_SHIFT 8

#define	_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT 0x00000000UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_MASK 0x2000UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_SHIFT 13

#define	_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT 0x00000000UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_MASK 0xFF000000UL

#define	_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_SHIFT 24

#define	_QSPI_WRITECOMPLETIONCTRL_RESETVALUE 0x00010005UL

#define	_QSPI_WRPROTCTRL_ENB_DEFAULT 0x00000000UL

#define	_QSPI_WRPROTCTRL_ENB_MASK 0x2UL

#define	_QSPI_WRPROTCTRL_ENB_SHIFT 1

#define	_QSPI_WRPROTCTRL_INV_DEFAULT 0x00000000UL

#define	_QSPI_WRPROTCTRL_INV_MASK 0x1UL

#define	_QSPI_WRPROTCTRL_INV_SHIFT 0

#define	_QSPI_WRPROTCTRL_MASK 0x00000003UL

#define	_QSPI_WRPROTCTRL_RESETVALUE 0x00000000UL

#define	QSPI_CONFIG_CRCENABLE (0x1UL << 29)

#define	QSPI_CONFIG_CRCENABLE_DEFAULT ( _QSPI_CONFIG_CRCENABLE_DEFAULT << 29)

#define	QSPI_CONFIG_DUALBYTEOPCODEEN (0x1UL << 30)

#define	QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT ( _QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT << 30)

#define	QSPI_CONFIG_ENABLEAHBDECODER (0x1UL << 23)

#define	QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT ( _QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT << 23)

#define	QSPI_CONFIG_ENABLEDTRPROTOCOL (0x1UL << 24)

#define	QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT ( _QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT << 24)

#define	QSPI_CONFIG_ENBAHBADDRREMAP (0x1UL << 16)

#define	QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT ( _QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT << 16)

#define	QSPI_CONFIG_ENBDIRACCCTLR (0x1UL << 7)

#define	QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT ( _QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT << 7)

#define	QSPI_CONFIG_ENBLEGACYIPMODE (0x1UL << 8)

#define	QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT ( _QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT << 8)

#define	QSPI_CONFIG_ENBSPI (0x1UL << 0)

#define	QSPI_CONFIG_ENBSPI_DEFAULT ( _QSPI_CONFIG_ENBSPI_DEFAULT << 0)

#define	QSPI_CONFIG_ENTERXIPMODE (0x1UL << 17)

#define	QSPI_CONFIG_ENTERXIPMODE_DEFAULT ( _QSPI_CONFIG_ENTERXIPMODE_DEFAULT << 17)

#define	QSPI_CONFIG_ENTERXIPMODEIMM (0x1UL << 18)

#define	QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT ( _QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT << 18)

#define	QSPI_CONFIG_IDLE (0x1UL << 31)

#define	QSPI_CONFIG_IDLE_DEFAULT ( _QSPI_CONFIG_IDLE_DEFAULT << 31)

#define	QSPI_CONFIG_MSTRBAUDDIV_DEFAULT ( _QSPI_CONFIG_MSTRBAUDDIV_DEFAULT << 19)

#define	QSPI_CONFIG_PERIPHCSLINES_DEFAULT ( _QSPI_CONFIG_PERIPHCSLINES_DEFAULT << 10)

#define	QSPI_CONFIG_PERIPHSELDEC (0x1UL << 9)

#define	QSPI_CONFIG_PERIPHSELDEC_DEFAULT ( _QSPI_CONFIG_PERIPHSELDEC_DEFAULT << 9)

#define	QSPI_CONFIG_PHYMODEENABLE (0x1UL << 3)

#define	QSPI_CONFIG_PHYMODEENABLE_DEFAULT ( _QSPI_CONFIG_PHYMODEENABLE_DEFAULT << 3)

#define	QSPI_CONFIG_PIPELINEPHY (0x1UL << 25)

#define	QSPI_CONFIG_PIPELINEPHY_DEFAULT ( _QSPI_CONFIG_PIPELINEPHY_DEFAULT << 25)

#define	QSPI_CONFIG_SELCLKPHASE (0x1UL << 2)

#define	QSPI_CONFIG_SELCLKPHASE_DEFAULT ( _QSPI_CONFIG_SELCLKPHASE_DEFAULT << 2)

#define	QSPI_CONFIG_SELCLKPOL (0x1UL << 1)

#define	QSPI_CONFIG_SELCLKPOL_DEFAULT ( _QSPI_CONFIG_SELCLKPOL_DEFAULT << 1)

#define	QSPI_CONFIG_WRPROTFLASH (0x1UL << 14)

#define	QSPI_CONFIG_WRPROTFLASH_DEFAULT ( _QSPI_CONFIG_WRPROTFLASH_DEFAULT << 14)

#define	QSPI_CTRL_TXDLYMUXSEL_DEFAULT ( _QSPI_CTRL_TXDLYMUXSEL_DEFAULT << 0)

#define	QSPI_CTRL_TXDLYMUXSEL_LARGE ( _QSPI_CTRL_TXDLYMUXSEL_LARGE << 0)

#define	QSPI_CTRL_TXDLYMUXSEL_MEDIUM ( _QSPI_CTRL_TXDLYMUXSEL_MEDIUM << 0)

#define	QSPI_CTRL_TXDLYMUXSEL_NONE ( _QSPI_CTRL_TXDLYMUXSEL_NONE << 0)

#define	QSPI_DEVDELAY_DAFTER_DEFAULT ( _QSPI_DEVDELAY_DAFTER_DEFAULT << 8)

#define	QSPI_DEVDELAY_DBTWN_DEFAULT ( _QSPI_DEVDELAY_DBTWN_DEFAULT << 16)

#define	QSPI_DEVDELAY_DINIT_DEFAULT ( _QSPI_DEVDELAY_DINIT_DEFAULT << 0)

#define	QSPI_DEVDELAY_DNSS_DEFAULT ( _QSPI_DEVDELAY_DNSS_DEFAULT << 24)

#define	QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT ( _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12)

#define	QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT ( _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16)

#define	QSPI_DEVINSTRRDCONFIG_DDREN (0x1UL << 10)

#define	QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT ( _QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT << 10)

#define	QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT ( _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT << 24)

#define	QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT ( _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT << 8)

#define	QSPI_DEVINSTRRDCONFIG_MODEBITENABLE (0x1UL << 20)

#define	QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT ( _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT << 20)

#define	QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT ( _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT << 0)

#define	QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT ( _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12)

#define	QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT ( _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16)

#define	QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT ( _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT << 24)

#define	QSPI_DEVINSTRWRCONFIG_WELDIS (0x1UL << 8)

#define	QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT ( _QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT << 8)

#define	QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT ( _QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT << 0)

#define	QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT ( _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT << 4)

#define	QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT ( _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT << 16)

#define	QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT ( _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT << 21)

#define	QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT ( _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT << 23)

#define	QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT ( _QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT << 0)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK (0x1UL << 0)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_DEFAULT ( _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_DEFAULT << 0)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_DEFAULT ( _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_DEFAULT << 16)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_DEFAULT ( _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_DEFAULT << 24)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_DEFAULT ( _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_DEFAULT << 1)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_DEFAULT ( _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_DEFAULT << 8)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK (0x1UL << 15)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_DEFAULT ( _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_DEFAULT << 15)

#define	QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_DEFAULT ( _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_DEFAULT << 3)

#define	QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_DEFAULT ( _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_DEFAULT << 0)

#define	QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_DEFAULT ( _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_DEFAULT << 16)

#define	QSPI_FLASHCMDADDR_ADDR_DEFAULT ( _QSPI_FLASHCMDADDR_ADDR_DEFAULT << 0)

#define	QSPI_FLASHCMDCTRL_CMDEXEC (0x1UL << 0)

#define	QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT ( _QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT << 0)

#define	QSPI_FLASHCMDCTRL_CMDEXECSTATUS (0x1UL << 1)

#define	QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT ( _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT << 1)

#define	QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT ( _QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT << 24)

#define	QSPI_FLASHCMDCTRL_ENBCOMDADDR (0x1UL << 19)

#define	QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT ( _QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT << 19)

#define	QSPI_FLASHCMDCTRL_ENBMODEBIT (0x1UL << 18)

#define	QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT ( _QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT << 18)

#define	QSPI_FLASHCMDCTRL_ENBREADDATA (0x1UL << 23)

#define	QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT ( _QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT << 23)

#define	QSPI_FLASHCMDCTRL_ENBWRITEDATA (0x1UL << 15)

#define	QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT ( _QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT << 15)

#define	QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT ( _QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT << 16)

#define	QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT ( _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT << 7)

#define	QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT ( _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT << 20)

#define	QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT ( _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT << 12)

#define	QSPI_FLASHCMDCTRL_STIGMEMBANKEN (0x1UL << 2)

#define	QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT ( _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT << 2)

#define	QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT ( _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT << 20)

#define	QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT ( _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT << 8)

#define	QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS (0x1UL << 1)

#define	QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT ( _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT << 1)

#define	QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT ( _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT << 16)

#define	QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ (0x1UL << 0)

#define	QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT ( _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT << 0)

#define	QSPI_FLASHRDDATALOWER_DATA_DEFAULT ( _QSPI_FLASHRDDATALOWER_DATA_DEFAULT << 0)

#define	QSPI_FLASHRDDATAUPPER_DATA_DEFAULT ( _QSPI_FLASHRDDATAUPPER_DATA_DEFAULT << 0)

#define	QSPI_FLASHWRDATALOWER_DATA_DEFAULT ( _QSPI_FLASHWRDATALOWER_DATA_DEFAULT << 0)

#define	QSPI_FLASHWRDATAUPPER_DATA_DEFAULT ( _QSPI_FLASHWRDATAUPPER_DATA_DEFAULT << 0)

#define	QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT ( _QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT << 0)

#define	QSPI_INDIRECTREADXFERCTRL_CANCEL (0x1UL << 1)

#define	QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT ( _QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT << 1)

#define	QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS (0x1UL << 5)

#define	QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT ( _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5)

#define	QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT ( _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT << 6)

#define	QSPI_INDIRECTREADXFERCTRL_RDQUEUED (0x1UL << 4)

#define	QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT ( _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT << 4)

#define	QSPI_INDIRECTREADXFERCTRL_RDSTATUS (0x1UL << 2)

#define	QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT ( _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT << 2)

#define	QSPI_INDIRECTREADXFERCTRL_SRAMFULL (0x1UL << 3)

#define	QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT ( _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT << 3)

#define	QSPI_INDIRECTREADXFERCTRL_START (0x1UL << 0)

#define	QSPI_INDIRECTREADXFERCTRL_START_DEFAULT ( _QSPI_INDIRECTREADXFERCTRL_START_DEFAULT << 0)

#define	QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT ( _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT << 0)

#define	QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT ( _QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT << 0)

#define	QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT ( _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT << 0)

#define	QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT ( _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT << 0)

#define	QSPI_INDIRECTWRITEXFERCTRL_CANCEL (0x1UL << 1)

#define	QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT ( _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT << 1)

#define	QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS (0x1UL << 5)

#define	QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT ( _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5)

#define	QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT ( _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT << 6)

#define	QSPI_INDIRECTWRITEXFERCTRL_START (0x1UL << 0)

#define	QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT ( _QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT << 0)

#define	QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED (0x1UL << 4)

#define	QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT ( _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT << 4)

#define	QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS (0x1UL << 2)

#define	QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT ( _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT << 2)

#define	QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT ( _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT << 0)

#define	QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT ( _QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT << 0)

#define	QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT ( _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT << 0)

#define	QSPI_IRQMASK_ILLEGALACCESSDETMASK (0x1UL << 5)

#define	QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT ( _QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT << 5)

#define	QSPI_IRQMASK_INDIRECTOPDONEMASK (0x1UL << 2)

#define	QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT ( _QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT << 2)

#define	QSPI_IRQMASK_INDIRECTREADREJECTMASK (0x1UL << 3)

#define	QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT ( _QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT << 3)

#define	QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK (0x1UL << 6)

#define	QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT ( _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT << 6)

#define	QSPI_IRQMASK_INDRDSRAMFULLMASK (0x1UL << 12)

#define	QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT ( _QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT << 12)

#define	QSPI_IRQMASK_MODEMFAILMASK (0x1UL << 0)

#define	QSPI_IRQMASK_MODEMFAILMASK_DEFAULT ( _QSPI_IRQMASK_MODEMFAILMASK_DEFAULT << 0)

#define	QSPI_IRQMASK_POLLEXPINTMASK (0x1UL << 13)

#define	QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT ( _QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT << 13)

#define	QSPI_IRQMASK_PROTWRATTEMPTMASK (0x1UL << 4)

#define	QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT ( _QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT << 4)

#define	QSPI_IRQMASK_RECVOVERFLOWMASK (0x1UL << 7)

#define	QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT ( _QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT << 7)

#define	QSPI_IRQMASK_RXCRCDATAERRMASK (0x1UL << 16)

#define	QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT ( _QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT << 16)

#define	QSPI_IRQMASK_RXCRCDATAVALMASK (0x1UL << 17)

#define	QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT ( _QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT << 17)

#define	QSPI_IRQMASK_RXFIFOFULLMASK (0x1UL << 11)

#define	QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT ( _QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT << 11)

#define	QSPI_IRQMASK_RXFIFONOTEMPTYMASK (0x1UL << 10)

#define	QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT ( _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT << 10)

#define	QSPI_IRQMASK_STIGREQMASK (0x1UL << 14)

#define	QSPI_IRQMASK_STIGREQMASK_DEFAULT ( _QSPI_IRQMASK_STIGREQMASK_DEFAULT << 14)

#define	QSPI_IRQMASK_TXCRCCHUNKBRKMASK (0x1UL << 18)

#define	QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT ( _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT << 18)

#define	QSPI_IRQMASK_TXFIFOFULLMASK (0x1UL << 9)

#define	QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT ( _QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT << 9)

#define	QSPI_IRQMASK_TXFIFONOTFULLMASK (0x1UL << 8)

#define	QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT ( _QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT << 8)

#define	QSPI_IRQMASK_UNDERFLOWDETMASK (0x1UL << 1)

#define	QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT ( _QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT << 1)

#define	QSPI_IRQSTATUS_ILLEGALACCESSDET (0x1UL << 5)

#define	QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT ( _QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT << 5)

#define	QSPI_IRQSTATUS_INDIRECTOPDONE (0x1UL << 2)

#define	QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT ( _QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT << 2)

#define	QSPI_IRQSTATUS_INDIRECTREADREJECT (0x1UL << 3)

#define	QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT ( _QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT << 3)

#define	QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH (0x1UL << 6)

#define	QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT ( _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT << 6)

#define	QSPI_IRQSTATUS_INDRDSRAMFULL (0x1UL << 12)

#define	QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT ( _QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT << 12)

#define	QSPI_IRQSTATUS_MODEMFAIL (0x1UL << 0)

#define	QSPI_IRQSTATUS_MODEMFAIL_DEFAULT ( _QSPI_IRQSTATUS_MODEMFAIL_DEFAULT << 0)

#define	QSPI_IRQSTATUS_POLLEXPINT (0x1UL << 13)

#define	QSPI_IRQSTATUS_POLLEXPINT_DEFAULT ( _QSPI_IRQSTATUS_POLLEXPINT_DEFAULT << 13)

#define	QSPI_IRQSTATUS_PROTWRATTEMPT (0x1UL << 4)

#define	QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT ( _QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT << 4)

#define	QSPI_IRQSTATUS_RECVOVERFLOW (0x1UL << 7)

#define	QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT ( _QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT << 7)

#define	QSPI_IRQSTATUS_RXCRCDATAERR (0x1UL << 16)

#define	QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT ( _QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT << 16)

#define	QSPI_IRQSTATUS_RXCRCDATAVAL (0x1UL << 17)

#define	QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT ( _QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT << 17)

#define	QSPI_IRQSTATUS_RXFIFOFULL (0x1UL << 11)

#define	QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT ( _QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT << 11)

#define	QSPI_IRQSTATUS_RXFIFONOTEMPTY (0x1UL << 10)

#define	QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT ( _QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT << 10)

#define	QSPI_IRQSTATUS_STIGREQINT (0x1UL << 14)

#define	QSPI_IRQSTATUS_STIGREQINT_DEFAULT ( _QSPI_IRQSTATUS_STIGREQINT_DEFAULT << 14)

#define	QSPI_IRQSTATUS_TXCRCCHUNKBRK (0x1UL << 18)

#define	QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT ( _QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT << 18)

#define	QSPI_IRQSTATUS_TXFIFOFULL (0x1UL << 9)

#define	QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT ( _QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT << 9)

#define	QSPI_IRQSTATUS_TXFIFONOTFULL (0x1UL << 8)

#define	QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT ( _QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT << 8)

#define	QSPI_IRQSTATUS_UNDERFLOWDET (0x1UL << 1)

#define	QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT ( _QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT << 1)

#define	QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT ( _QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT << 0)

#define	QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT ( _QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT << 8)

#define	QSPI_MODEBITCONFIG_CRCOUTENABLE (0x1UL << 15)

#define	QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT ( _QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT << 15)

#define	QSPI_MODEBITCONFIG_MODE_DEFAULT ( _QSPI_MODEBITCONFIG_MODE_DEFAULT << 0)

#define	QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT ( _QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT << 24)

#define	QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT ( _QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT << 16)

#define	QSPI_MODULEID_CONF_DEFAULT ( _QSPI_MODULEID_CONF_DEFAULT << 0)

#define	QSPI_MODULEID_FIXPATCH_DEFAULT ( _QSPI_MODULEID_FIXPATCH_DEFAULT << 24)

#define	QSPI_MODULEID_MODULEID_DEFAULT ( _QSPI_MODULEID_MODULEID_DEFAULT << 8)

#define	QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT ( _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT << 0)

#define	QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT ( _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT << 8)

#define	QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT ( _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT << 24)

#define	QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT ( _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT << 0)

#define	QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT ( _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT << 16)

#define	QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT ( _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT << 16)

#define	QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT ( _QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT << 24)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGRESET (0x1UL << 30)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGRESET_DEFAULT ( _QSPI_PHYCONFIGURATION_PHYCONFIGRESET_DEFAULT << 30)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC (0x1UL << 31)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT ( _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT << 31)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS (0x1UL << 29)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_DEFAULT ( _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_DEFAULT << 29)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT ( _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT << 0)

#define	QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT ( _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT << 16)

#define	QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE (0x1UL << 23)

#define	QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_DEFAULT ( _QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_DEFAULT << 23)

#define

QSPI Bit FieldsDevices > QSPI

Macros