|
#define
|
_SDIO_AC12ERRSTAT_AC12CRCERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12CRCERR_MASK
0x4UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12CRCERR_SHIFT
2
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12ENDBITERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12ENDBITERR_MASK
0x8UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12ENDBITERR_SHIFT
3
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12INDEXERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12INDEXERR_MASK
0x10UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12INDEXERR_SHIFT
4
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12NOTEXE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12NOTEXE_MASK
0x1UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12NOTEXE_SHIFT
0
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12TOE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12TOE_MASK
0x2UL
|
|
#define
|
_SDIO_AC12ERRSTAT_AC12TOE_SHIFT
1
|
|
#define
|
_SDIO_AC12ERRSTAT_ASYNCINTEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_ASYNCINTEN_MASK
0x40000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_ASYNCINTEN_SHIFT
30
|
|
#define
|
_SDIO_AC12ERRSTAT_CNIBAC12ERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_CNIBAC12ERR_MASK
0x80UL
|
|
#define
|
_SDIO_AC12ERRSTAT_CNIBAC12ERR_SHIFT
7
|
|
#define
|
_SDIO_AC12ERRSTAT_DRVSTNSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_DRVSTNSEL_MASK
0x300000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_DRVSTNSEL_SHIFT
20
|
|
#define
|
_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_AC12ERRSTAT_DRVSTNSEL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_AC12ERRSTAT_EXETUNING_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_EXETUNING_MASK
0x400000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_EXETUNING_SHIFT
22
|
|
#define
|
_SDIO_AC12ERRSTAT_MASK
0xC0FF009FUL
|
|
#define
|
_SDIO_AC12ERRSTAT_PRSTVALEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_PRSTVALEN_MASK
0x80000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_PRSTVALEN_SHIFT
31
|
|
#define
|
_SDIO_AC12ERRSTAT_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_SAMPCLKSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_SAMPCLKSEL_MASK
0x800000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_SAMPCLKSEL_SHIFT
23
|
|
#define
|
_SDIO_AC12ERRSTAT_SIGEN1P8V_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_SIGEN1P8V_MASK
0x80000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_SIGEN1P8V_SHIFT
19
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_DDR50
0x00000004UL
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_MASK
0x70000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_SDR104
0x00000003UL
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_SDR12
0x00000000UL
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_SDR25
0x00000001UL
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_SDR50
0x00000002UL
|
|
#define
|
_SDIO_AC12ERRSTAT_UHSMODESEL_SHIFT
16
|
|
#define
|
_SDIO_ADMAES_ADMAES_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_ADMAES_ADMAES_MASK
0x3UL
|
|
#define
|
_SDIO_ADMAES_ADMAES_SHIFT
0
|
|
#define
|
_SDIO_ADMAES_ADMALME_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_ADMAES_ADMALME_MASK
0x4UL
|
|
#define
|
_SDIO_ADMAES_ADMALME_SHIFT
2
|
|
#define
|
_SDIO_ADMAES_MASK
0x00000007UL
|
|
#define
|
_SDIO_ADMAES_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_ADSADDR_ADSADDR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_ADSADDR_ADSADDR_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_ADSADDR_ADSADDR_SHIFT
0
|
|
#define
|
_SDIO_ADSADDR_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_ADSADDR_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_MASK
0xFFFF0000UL
|
|
#define
|
_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_SHIFT
16
|
|
#define
|
_SDIO_BLKSIZE_BLKSCNTFORCURRTFR_STOPCNT
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_MASK
0x7000UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SHIFT
12
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE128
0x00000005UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE16
0x00000002UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE256
0x00000006UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE32
0x00000003UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE4
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE512
0x00000007UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE64
0x00000004UL
|
|
#define
|
_SDIO_BLKSIZE_HSTSDMABUFSIZE_SIZE8
0x00000001UL
|
|
#define
|
_SDIO_BLKSIZE_MASK
0xFFFF7FFFUL
|
|
#define
|
_SDIO_BLKSIZE_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_TFRBLKSIZE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_TFRBLKSIZE_MASK
0xFFFUL
|
|
#define
|
_SDIO_BLKSIZE_TFRBLKSIZE_NOXFER
0x00000000UL
|
|
#define
|
_SDIO_BLKSIZE_TFRBLKSIZE_SHIFT
0
|
|
#define
|
_SDIO_BOOTTOCTRL_BOOTDATTOCNT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_BOOTTOCTRL_BOOTDATTOCNT_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_BOOTTOCTRL_BOOTDATTOCNT_SHIFT
0
|
|
#define
|
_SDIO_BOOTTOCTRL_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_BOOTTOCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_BUFDATPORT_BUFDAT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_BUFDATPORT_BUFDAT_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_BUFDATPORT_BUFDAT_SHIFT
0
|
|
#define
|
_SDIO_BUFDATPORT_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_BUFDATPORT_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_ADMA2SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_ADMA2SUP_MASK
0x80000UL
|
|
#define
|
_SDIO_CAPAB0_ADMA2SUP_SHIFT
19
|
|
#define
|
_SDIO_CAPAB0_ASYNCINTSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_ASYNCINTSUP_MASK
0x20000000UL
|
|
#define
|
_SDIO_CAPAB0_ASYNCINTSUP_SHIFT
29
|
|
#define
|
_SDIO_CAPAB0_BASECLKFREQSD_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_BASECLKFREQSD_MASK
0xFF00UL
|
|
#define
|
_SDIO_CAPAB0_BASECLKFREQSD_SHIFT
8
|
|
#define
|
_SDIO_CAPAB0_EXTMEDIABUSSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_EXTMEDIABUSSUP_MASK
0x40000UL
|
|
#define
|
_SDIO_CAPAB0_EXTMEDIABUSSUP_SHIFT
18
|
|
#define
|
_SDIO_CAPAB0_HSSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_HSSUP_MASK
0x200000UL
|
|
#define
|
_SDIO_CAPAB0_HSSUP_SHIFT
21
|
|
#define
|
_SDIO_CAPAB0_IFSLOTTYPE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_IFSLOTTYPE_EMBEDDED
0x00000001UL
|
|
#define
|
_SDIO_CAPAB0_IFSLOTTYPE_MASK
0xC0000000UL
|
|
#define
|
_SDIO_CAPAB0_IFSLOTTYPE_REMOVABLE
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_IFSLOTTYPE_SHARED
0x00000002UL
|
|
#define
|
_SDIO_CAPAB0_IFSLOTTYPE_SHIFT
30
|
|
#define
|
_SDIO_CAPAB0_MASK
0xF7EFFFBFUL
|
|
#define
|
_SDIO_CAPAB0_MAXBLOCKLEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_MAXBLOCKLEN_MASK
0x30000UL
|
|
#define
|
_SDIO_CAPAB0_MAXBLOCKLEN_SHIFT
16
|
|
#define
|
_SDIO_CAPAB0_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_SDMASUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_SDMASUP_MASK
0x400000UL
|
|
#define
|
_SDIO_CAPAB0_SDMASUP_SHIFT
22
|
|
#define
|
_SDIO_CAPAB0_SUSRESSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_SUSRESSUP_MASK
0x800000UL
|
|
#define
|
_SDIO_CAPAB0_SUSRESSUP_SHIFT
23
|
|
#define
|
_SDIO_CAPAB0_SYSBUS64BSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_SYSBUS64BSUP_MASK
0x10000000UL
|
|
#define
|
_SDIO_CAPAB0_SYSBUS64BSUP_SHIFT
28
|
|
#define
|
_SDIO_CAPAB0_TMOUTCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_TMOUTCLKFREQ_MASK
0x3FUL
|
|
#define
|
_SDIO_CAPAB0_TMOUTCLKFREQ_SHIFT
0
|
|
#define
|
_SDIO_CAPAB0_TMOUTCLKUNIT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_TMOUTCLKUNIT_MASK
0x80UL
|
|
#define
|
_SDIO_CAPAB0_TMOUTCLKUNIT_SHIFT
7
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP1P8V_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP1P8V_MASK
0x4000000UL
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP1P8V_SHIFT
26
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP3P0V_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP3P0V_MASK
0x2000000UL
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP3P0V_SHIFT
25
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP3P3V_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP3P3V_MASK
0x1000000UL
|
|
#define
|
_SDIO_CAPAB0_VOLTSUP3P3V_SHIFT
24
|
|
#define
|
_SDIO_CAPAB2_CLOCKKMUL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_CLOCKKMUL_MASK
0xFF0000UL
|
|
#define
|
_SDIO_CAPAB2_CLOCKKMUL_SHIFT
16
|
|
#define
|
_SDIO_CAPAB2_DDR50SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_DDR50SUP_MASK
0x4UL
|
|
#define
|
_SDIO_CAPAB2_DDR50SUP_SHIFT
2
|
|
#define
|
_SDIO_CAPAB2_DRVTYPASUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_DRVTYPASUP_MASK
0x10UL
|
|
#define
|
_SDIO_CAPAB2_DRVTYPASUP_SHIFT
4
|
|
#define
|
_SDIO_CAPAB2_DRVTYPCSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_DRVTYPCSUP_MASK
0x20UL
|
|
#define
|
_SDIO_CAPAB2_DRVTYPCSUP_SHIFT
5
|
|
#define
|
_SDIO_CAPAB2_DRVTYPDSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_DRVTYPDSUP_MASK
0x40UL
|
|
#define
|
_SDIO_CAPAB2_DRVTYPDSUP_SHIFT
6
|
|
#define
|
_SDIO_CAPAB2_MASK
0x03FFEF77UL
|
|
#define
|
_SDIO_CAPAB2_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_RETUNEMODES_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_RETUNEMODES_MASK
0xC000UL
|
|
#define
|
_SDIO_CAPAB2_RETUNEMODES_SHIFT
14
|
|
#define
|
_SDIO_CAPAB2_SDR104SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_SDR104SUP_MASK
0x2UL
|
|
#define
|
_SDIO_CAPAB2_SDR104SUP_SHIFT
1
|
|
#define
|
_SDIO_CAPAB2_SDR50SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_SDR50SUP_MASK
0x1UL
|
|
#define
|
_SDIO_CAPAB2_SDR50SUP_SHIFT
0
|
|
#define
|
_SDIO_CAPAB2_SPIBLOCKMODE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_SPIBLOCKMODE_MASK
0x2000000UL
|
|
#define
|
_SDIO_CAPAB2_SPIBLOCKMODE_SHIFT
25
|
|
#define
|
_SDIO_CAPAB2_SPIMODE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_SPIMODE_MASK
0x1000000UL
|
|
#define
|
_SDIO_CAPAB2_SPIMODE_SHIFT
24
|
|
#define
|
_SDIO_CAPAB2_TIMCNTRETUN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_TIMCNTRETUN_MASK
0xF00UL
|
|
#define
|
_SDIO_CAPAB2_TIMCNTRETUN_SHIFT
8
|
|
#define
|
_SDIO_CAPAB2_USETUNSDR50_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CAPAB2_USETUNSDR50_MASK
0x2000UL
|
|
#define
|
_SDIO_CAPAB2_USETUNSDR50_SHIFT
13
|
|
#define
|
_SDIO_CFG0_BASECLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_BASECLKFREQ_MASK
0x1FE000UL
|
|
#define
|
_SDIO_CFG0_BASECLKFREQ_SHIFT
13
|
|
#define
|
_SDIO_CFG0_C1P8VSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_C1P8VSUP_MASK
0x40000000UL
|
|
#define
|
_SDIO_CFG0_C1P8VSUP_SHIFT
30
|
|
#define
|
_SDIO_CFG0_C3P0VSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_C3P0VSUP_MASK
0x20000000UL
|
|
#define
|
_SDIO_CFG0_C3P0VSUP_SHIFT
29
|
|
#define
|
_SDIO_CFG0_C3P3VSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_C3P3VSUP_MASK
0x10000000UL
|
|
#define
|
_SDIO_CFG0_C3P3VSUP_SHIFT
28
|
|
#define
|
_SDIO_CFG0_C8BITSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_C8BITSUP_MASK
0x800000UL
|
|
#define
|
_SDIO_CFG0_C8BITSUP_SHIFT
23
|
|
#define
|
_SDIO_CFG0_CADMA2SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_CADMA2SUP_MASK
0x1000000UL
|
|
#define
|
_SDIO_CFG0_CADMA2SUP_SHIFT
24
|
|
#define
|
_SDIO_CFG0_CHSSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_CHSSUP_MASK
0x2000000UL
|
|
#define
|
_SDIO_CFG0_CHSSUP_SHIFT
25
|
|
#define
|
_SDIO_CFG0_CSDMASUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_CSDMASUP_MASK
0x4000000UL
|
|
#define
|
_SDIO_CFG0_CSDMASUP_SHIFT
26
|
|
#define
|
_SDIO_CFG0_CSUSPRESSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_CSUSPRESSUP_MASK
0x8000000UL
|
|
#define
|
_SDIO_CFG0_CSUSPRESSUP_SHIFT
27
|
|
#define
|
_SDIO_CFG0_MASK
0x7FFFFFFFUL
|
|
#define
|
_SDIO_CFG0_MAXBLKLEN_1024B
0x00000001UL
|
|
#define
|
_SDIO_CFG0_MAXBLKLEN_2048B
0x00000002UL
|
|
#define
|
_SDIO_CFG0_MAXBLKLEN_512B
0x00000000UL
|
|
#define
|
_SDIO_CFG0_MAXBLKLEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_MAXBLKLEN_MASK
0x600000UL
|
|
#define
|
_SDIO_CFG0_MAXBLKLEN_SHIFT
21
|
|
#define
|
_SDIO_CFG0_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CFG0_TOUTCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_TOUTCLKFREQ_MASK
0xFC0UL
|
|
#define
|
_SDIO_CFG0_TOUTCLKFREQ_SHIFT
6
|
|
#define
|
_SDIO_CFG0_TOUTCLKUNIT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_TOUTCLKUNIT_MASK
0x1000UL
|
|
#define
|
_SDIO_CFG0_TOUTCLKUNIT_SHIFT
12
|
|
#define
|
_SDIO_CFG0_TUNINGCNT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG0_TUNINGCNT_MASK
0x3FUL
|
|
#define
|
_SDIO_CFG0_TUNINGCNT_SHIFT
0
|
|
#define
|
_SDIO_CFG1_ASYNCINTRSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_ASYNCINTRSUP_MASK
0x1UL
|
|
#define
|
_SDIO_CFG1_ASYNCINTRSUP_SHIFT
0
|
|
#define
|
_SDIO_CFG1_ASYNCWKUPEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_ASYNCWKUPEN_MASK
0x40000UL
|
|
#define
|
_SDIO_CFG1_ASYNCWKUPEN_SHIFT
18
|
|
#define
|
_SDIO_CFG1_CDDR50SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_CDDR50SUP_MASK
0x20UL
|
|
#define
|
_SDIO_CFG1_CDDR50SUP_SHIFT
5
|
|
#define
|
_SDIO_CFG1_CDRVASUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_CDRVASUP_MASK
0x40UL
|
|
#define
|
_SDIO_CFG1_CDRVASUP_SHIFT
6
|
|
#define
|
_SDIO_CFG1_CDRVCSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_CDRVCSUP_MASK
0x80UL
|
|
#define
|
_SDIO_CFG1_CDRVCSUP_SHIFT
7
|
|
#define
|
_SDIO_CFG1_CDRVDSUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_CDRVDSUP_MASK
0x100UL
|
|
#define
|
_SDIO_CFG1_CDRVDSUP_SHIFT
8
|
|
#define
|
_SDIO_CFG1_CSDR104SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_CSDR104SUP_MASK
0x10UL
|
|
#define
|
_SDIO_CFG1_CSDR104SUP_SHIFT
4
|
|
#define
|
_SDIO_CFG1_CSDR50SUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_CSDR50SUP_MASK
0x8UL
|
|
#define
|
_SDIO_CFG1_CSDR50SUP_SHIFT
3
|
|
#define
|
_SDIO_CFG1_MASK
0x0005FFFFUL
|
|
#define
|
_SDIO_CFG1_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CFG1_RETUNMODES_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_RETUNMODES_MASK
0xC000UL
|
|
#define
|
_SDIO_CFG1_RETUNMODES_SHIFT
14
|
|
#define
|
_SDIO_CFG1_RETUNTMRCTL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_RETUNTMRCTL_MASK
0x1E00UL
|
|
#define
|
_SDIO_CFG1_RETUNTMRCTL_SHIFT
9
|
|
#define
|
_SDIO_CFG1_SLOTTYPE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_SLOTTYPE_EMSDSLOT
0x00000001UL
|
|
#define
|
_SDIO_CFG1_SLOTTYPE_MASK
0x6UL
|
|
#define
|
_SDIO_CFG1_SLOTTYPE_RMSDSLOT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_SLOTTYPE_SHBUSSLOT
0x00000002UL
|
|
#define
|
_SDIO_CFG1_SLOTTYPE_SHIFT
1
|
|
#define
|
_SDIO_CFG1_SPISUP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_SPISUP_MASK
0x10000UL
|
|
#define
|
_SDIO_CFG1_SPISUP_SHIFT
16
|
|
#define
|
_SDIO_CFG1_TUNSDR50_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFG1_TUNSDR50_MASK
0x2000UL
|
|
#define
|
_SDIO_CFG1_TUNSDR50_SHIFT
13
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPCLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPCLKGENEN_MASK
0x4000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPCLKGENEN_SHIFT
26
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPDRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPDRVST_MASK
0x18000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPDRVST_SHIFT
27
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_DSPSDCLKFREQ_SHIFT
16
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITCLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITCLKGENEN_MASK
0x400UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITCLKGENEN_SHIFT
10
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITDRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITDRVST_MASK
0x1800UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITDRVST_SHIFT
11
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITSDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITSDCLKFREQ_MASK
0x3FFUL
|
|
#define
|
_SDIO_CFGPRESETVAL0_INITSDCLKFREQ_SHIFT
0
|
|
#define
|
_SDIO_CFGPRESETVAL0_MASK
0x1FFF1FFFUL
|
|
#define
|
_SDIO_CFGPRESETVAL0_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPCLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPCLKGENEN_MASK
0x400UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPCLKGENEN_SHIFT
10
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPDRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPDRVST_MASK
0x1800UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPDRVST_SHIFT
11
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_MASK
0x3FFUL
|
|
#define
|
_SDIO_CFGPRESETVAL1_HSPSDCLKFREQ_SHIFT
0
|
|
#define
|
_SDIO_CFGPRESETVAL1_MASK
0x1FFF1FFFUL
|
|
#define
|
_SDIO_CFGPRESETVAL1_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12CLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12CLKGENEN_MASK
0x4000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12CLKGENEN_SHIFT
26
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12DRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12DRVST_MASK
0x18000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12DRVST_SHIFT
27
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_CFGPRESETVAL1_SDR12SDCLKFREQ_SHIFT
16
|
|
#define
|
_SDIO_CFGPRESETVAL2_MASK
0x1FFF1FFFUL
|
|
#define
|
_SDIO_CFGPRESETVAL2_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25CLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25CLKGENEN_MASK
0x400UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25CLKGENEN_SHIFT
10
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25DRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25DRVST_MASK
0x1800UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25DRVST_SHIFT
11
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_MASK
0x3FFUL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR25SDCLKFREQ_SHIFT
0
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50CLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50CLKGENEN_MASK
0x4000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50CLKGENEN_SHIFT
26
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50DRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50DRVST_MASK
0x18000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50DRVST_SHIFT
27
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_CFGPRESETVAL2_SDR50SDCLKFREQ_SHIFT
16
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50CLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50CLKGENEN_MASK
0x4000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50CLKGENEN_SHIFT
26
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50DRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50DRVST_MASK
0x18000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50DRVST_SHIFT
27
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_DDR50SDCLKFREQ_SHIFT
16
|
|
#define
|
_SDIO_CFGPRESETVAL3_MASK
0x1FFF1FFFUL
|
|
#define
|
_SDIO_CFGPRESETVAL3_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104CLKGENEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104CLKGENEN_MASK
0x400UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104CLKGENEN_SHIFT
10
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104DRVST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104DRVST_MASK
0x1800UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104DRVST_SHIFT
11
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_MASK
0x3FFUL
|
|
#define
|
_SDIO_CFGPRESETVAL3_SDR104SDCLKFREQ_SHIFT
0
|
|
#define
|
_SDIO_CLOCKCTRL_CLKGENSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_CLKGENSEL_MASK
0x20UL
|
|
#define
|
_SDIO_CLOCKCTRL_CLKGENSEL_SHIFT
5
|
|
#define
|
_SDIO_CLOCKCTRL_DATTOUTCNTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_DATTOUTCNTVAL_MASK
0xF0000UL
|
|
#define
|
_SDIO_CLOCKCTRL_DATTOUTCNTVAL_SHIFT
16
|
|
#define
|
_SDIO_CLOCKCTRL_INTCLKEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_INTCLKEN_MASK
0x1UL
|
|
#define
|
_SDIO_CLOCKCTRL_INTCLKEN_SHIFT
0
|
|
#define
|
_SDIO_CLOCKCTRL_INTCLKSTABLE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_INTCLKSTABLE_MASK
0x2UL
|
|
#define
|
_SDIO_CLOCKCTRL_INTCLKSTABLE_SHIFT
1
|
|
#define
|
_SDIO_CLOCKCTRL_MASK
0x070FFFE7UL
|
|
#define
|
_SDIO_CLOCKCTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SDCLKEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SDCLKEN_MASK
0x4UL
|
|
#define
|
_SDIO_CLOCKCTRL_SDCLKEN_SHIFT
2
|
|
#define
|
_SDIO_CLOCKCTRL_SDCLKFREQSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SDCLKFREQSEL_MASK
0xFF00UL
|
|
#define
|
_SDIO_CLOCKCTRL_SDCLKFREQSEL_NODIVISION
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SDCLKFREQSEL_SHIFT
8
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTA_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTA_MASK
0x1000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTA_SHIFT
24
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTCMD_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTCMD_MASK
0x2000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTCMD_SHIFT
25
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTDAT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTDAT_MASK
0x4000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_SFTRSTDAT_SHIFT
26
|
|
#define
|
_SDIO_CLOCKCTRL_UPPSDCLKFRE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CLOCKCTRL_UPPSDCLKFRE_MASK
0xC0UL
|
|
#define
|
_SDIO_CLOCKCTRL_UPPSDCLKFRE_SHIFT
6
|
|
#define
|
_SDIO_CMDARG1_CMDARG1_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CMDARG1_CMDARG1_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_CMDARG1_CMDARG1_SHIFT
0
|
|
#define
|
_SDIO_CMDARG1_MASK
0xFFFFFFFFUL
|
|
#define
|
_SDIO_CMDARG1_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CTRL_ITAPCHGWIN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CTRL_ITAPCHGWIN_MASK
0x40UL
|
|
#define
|
_SDIO_CTRL_ITAPCHGWIN_SHIFT
6
|
|
#define
|
_SDIO_CTRL_ITAPDLYEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CTRL_ITAPDLYEN_MASK
0x1UL
|
|
#define
|
_SDIO_CTRL_ITAPDLYEN_SHIFT
0
|
|
#define
|
_SDIO_CTRL_ITAPDLYSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CTRL_ITAPDLYSEL_MASK
0x3EUL
|
|
#define
|
_SDIO_CTRL_ITAPDLYSEL_SHIFT
1
|
|
#define
|
_SDIO_CTRL_MASK
0x00030FFFUL
|
|
#define
|
_SDIO_CTRL_OTAPDLYEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CTRL_OTAPDLYEN_MASK
0x80UL
|
|
#define
|
_SDIO_CTRL_OTAPDLYEN_SHIFT
7
|
|
#define
|
_SDIO_CTRL_OTAPDLYSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CTRL_OTAPDLYSEL_MASK
0xF00UL
|
|
#define
|
_SDIO_CTRL_OTAPDLYSEL_SHIFT
8
|
|
#define
|
_SDIO_CTRL_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_CTRL_TXDLYMUXSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_CTRL_TXDLYMUXSEL_MASK
0x30000UL
|
|
#define
|
_SDIO_CTRL_TXDLYMUXSEL_SHIFT
16
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12CRCE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12CRCE_MASK
0x4UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12CRCE_SHIFT
2
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12E_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12E_MASK
0x1000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12E_SHIFT
24
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12EBE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12EBE_MASK
0x8UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12EBE_SHIFT
3
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12INDXE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12INDXE_MASK
0x10UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12INDXE_SHIFT
4
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12NEX_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12NEX_MASK
0x1UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12NEX_SHIFT
0
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12TOE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12TOE_MASK
0x2UL
|
|
#define
|
_SDIO_FEVTERRSTAT_AC12TOE_SHIFT
1
|
|
#define
|
_SDIO_FEVTERRSTAT_ADMAE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_ADMAE_MASK
0x2000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_ADMAE_SHIFT
25
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDCRCE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDCRCE_MASK
0x20000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDCRCE_SHIFT
17
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDEBE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDEBE_MASK
0x40000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDEBE_SHIFT
18
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDINDXE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDINDXE_MASK
0x80000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDINDXE_SHIFT
19
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDTOE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDTOE_MASK
0x10000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CMDTOE_SHIFT
16
|
|
#define
|
_SDIO_FEVTERRSTAT_CNIBAC12E_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CNIBAC12E_MASK
0x80UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CNIBAC12E_SHIFT
7
|
|
#define
|
_SDIO_FEVTERRSTAT_CURLIMITE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CURLIMITE_MASK
0x800000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_CURLIMITE_SHIFT
23
|
|
#define
|
_SDIO_FEVTERRSTAT_DATCRCE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_DATCRCE_MASK
0x200000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_DATCRCE_SHIFT
21
|
|
#define
|
_SDIO_FEVTERRSTAT_DATEBE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_DATEBE_MASK
0x400000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_DATEBE_SHIFT
22
|
|
#define
|
_SDIO_FEVTERRSTAT_DATTOE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_DATTOE_MASK
0x100000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_DATTOE_SHIFT
20
|
|
#define
|
_SDIO_FEVTERRSTAT_MASK
0xF7FF009FUL
|
|
#define
|
_SDIO_FEVTERRSTAT_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_TUNINGE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_TUNINGE_MASK
0x4000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_TUNINGE_SHIFT
26
|
|
#define
|
_SDIO_FEVTERRSTAT_VENSPECE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_VENSPECE_MASK
0xF0000000UL
|
|
#define
|
_SDIO_FEVTERRSTAT_VENSPECE_SHIFT
28
|
|
#define
|
_SDIO_HOSTCTRL1_ALTBOOTEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_ALTBOOTEN_MASK
0x400000UL
|
|
#define
|
_SDIO_HOSTCTRL1_ALTBOOTEN_SHIFT
22
|
|
#define
|
_SDIO_HOSTCTRL1_BOOTACKCHK_DEFAULT
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_BOOTACKCHK_MASK
0x800000UL
|
|
#define
|
_SDIO_HOSTCTRL1_BOOTACKCHK_SHIFT
23
|
|
#define
|
_SDIO_HOSTCTRL1_BOOTEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_BOOTEN_MASK
0x200000UL
|
|
#define
|
_SDIO_HOSTCTRL1_BOOTEN_SHIFT
21
|
|
#define
|
_SDIO_HOSTCTRL1_CDSIGDET_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDSIGDET_MASK
0x80UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDSIGDET_SDCD
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDSIGDET_SHIFT
7
|
|
#define
|
_SDIO_HOSTCTRL1_CDSIGDET_TSTLVL
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDTSTLVL_CARDIN
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDTSTLVL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDTSTLVL_MASK
0x40UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDTSTLVL_NOCARD
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_CDTSTLVL_SHIFT
6
|
|
#define
|
_SDIO_HOSTCTRL1_CONTINUEREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_CONTINUEREQ_MASK
0x20000UL
|
|
#define
|
_SDIO_HOSTCTRL1_CONTINUEREQ_SHIFT
17
|
|
#define
|
_SDIO_HOSTCTRL1_DATTRANWD_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_DATTRANWD_MASK
0x2UL
|
|
#define
|
_SDIO_HOSTCTRL1_DATTRANWD_SD1
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_DATTRANWD_SD4
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_DATTRANWD_SHIFT
1
|
|
#define
|
_SDIO_HOSTCTRL1_DMASEL_64BITADMA2
0x00000003UL
|
|
#define
|
_SDIO_HOSTCTRL1_DMASEL_ADMA1
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_DMASEL_ADMA2
0x00000002UL
|
|
#define
|
_SDIO_HOSTCTRL1_DMASEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_DMASEL_MASK
0x18UL
|
|
#define
|
_SDIO_HOSTCTRL1_DMASEL_SDMA
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_DMASEL_SHIFT
3
|
|
#define
|
_SDIO_HOSTCTRL1_EXTDATTRANWD_8BIT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_EXTDATTRANWD_DATXFR
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_EXTDATTRANWD_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_EXTDATTRANWD_MASK
0x20UL
|
|
#define
|
_SDIO_HOSTCTRL1_EXTDATTRANWD_SHIFT
5
|
|
#define
|
_SDIO_HOSTCTRL1_HRDRST_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_HRDRST_MASK
0x1000UL
|
|
#define
|
_SDIO_HOSTCTRL1_HRDRST_SHIFT
12
|
|
#define
|
_SDIO_HOSTCTRL1_HSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_HSEN_HS
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_HSEN_MASK
0x4UL
|
|
#define
|
_SDIO_HOSTCTRL1_HSEN_NS
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_HSEN_SHIFT
2
|
|
#define
|
_SDIO_HOSTCTRL1_INTATBLKGAP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_INTATBLKGAP_MASK
0x80000UL
|
|
#define
|
_SDIO_HOSTCTRL1_INTATBLKGAP_SHIFT
19
|
|
#define
|
_SDIO_HOSTCTRL1_LEDCTRL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_LEDCTRL_LEDOFF
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_LEDCTRL_LEDON
0x00000001UL
|
|
#define
|
_SDIO_HOSTCTRL1_LEDCTRL_MASK
0x1UL
|
|
#define
|
_SDIO_HOSTCTRL1_LEDCTRL_SHIFT
0
|
|
#define
|
_SDIO_HOSTCTRL1_MASK
0x07FF1FFFUL
|
|
#define
|
_SDIO_HOSTCTRL1_RDWAITCTRL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_RDWAITCTRL_MASK
0x40000UL
|
|
#define
|
_SDIO_HOSTCTRL1_RDWAITCTRL_SHIFT
18
|
|
#define
|
_SDIO_HOSTCTRL1_RESETVALUE
0x00800000UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSPOWER_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSPOWER_MASK
0x100UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSPOWER_SHIFT
8
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSVOLTSEL_1P8V
0x00000005UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P0V
0x00000006UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSVOLTSEL_3P3V
0x00000007UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSVOLTSEL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSVOLTSEL_MASK
0xE00UL
|
|
#define
|
_SDIO_HOSTCTRL1_SDBUSVOLTSEL_SHIFT
9
|
|
#define
|
_SDIO_HOSTCTRL1_SPIMODE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_SPIMODE_MASK
0x100000UL
|
|
#define
|
_SDIO_HOSTCTRL1_SPIMODE_SHIFT
20
|
|
#define
|
_SDIO_HOSTCTRL1_STOPATBLKGAPREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_STOPATBLKGAPREQ_MASK
0x10000UL
|
|
#define
|
_SDIO_HOSTCTRL1_STOPATBLKGAPREQ_SHIFT
16
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_MASK
0x1000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCARDINT_SHIFT
24
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCINS_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCINS_MASK
0x2000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCINS_SHIFT
25
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCRM_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCRM_MASK
0x4000000UL
|
|
#define
|
_SDIO_HOSTCTRL1_WKUPEVNTENONCRM_SHIFT
26
|
|
#define
|
_SDIO_IEN_ADMAERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_ADMAERRSEN_MASK
0x2000000UL
|
|
#define
|
_SDIO_IEN_ADMAERRSEN_SHIFT
25
|
|
#define
|
_SDIO_IEN_AUTOCMDERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_AUTOCMDERRSEN_MASK
0x1000000UL
|
|
#define
|
_SDIO_IEN_AUTOCMDERRSEN_SHIFT
24
|
|
#define
|
_SDIO_IEN_BLKGAPEVTSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_BLKGAPEVTSEN_MASK
0x4UL
|
|
#define
|
_SDIO_IEN_BLKGAPEVTSEN_SHIFT
2
|
|
#define
|
_SDIO_IEN_BOOTACKRCVSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_BOOTACKRCVSEN_MASK
0x2000UL
|
|
#define
|
_SDIO_IEN_BOOTACKRCVSEN_SHIFT
13
|
|
#define
|
_SDIO_IEN_BOOTTERMINATESEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_BOOTTERMINATESEN_MASK
0x4000UL
|
|
#define
|
_SDIO_IEN_BOOTTERMINATESEN_SHIFT
14
|
|
#define
|
_SDIO_IEN_BUFRDRDYSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_BUFRDRDYSEN_MASK
0x20UL
|
|
#define
|
_SDIO_IEN_BUFRDRDYSEN_SHIFT
5
|
|
#define
|
_SDIO_IEN_BUFWRRDYSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_BUFWRRDYSEN_MASK
0x10UL
|
|
#define
|
_SDIO_IEN_BUFWRRDYSEN_SHIFT
4
|
|
#define
|
_SDIO_IEN_CARDINSSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CARDINSSEN_MASK
0x40UL
|
|
#define
|
_SDIO_IEN_CARDINSSEN_SHIFT
6
|
|
#define
|
_SDIO_IEN_CARDINTSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CARDINTSEN_MASK
0x100UL
|
|
#define
|
_SDIO_IEN_CARDINTSEN_SHIFT
8
|
|
#define
|
_SDIO_IEN_CARDREMSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CARDREMSEN_MASK
0x80UL
|
|
#define
|
_SDIO_IEN_CARDREMSEN_SHIFT
7
|
|
#define
|
_SDIO_IEN_CMDCOMSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CMDCOMSEN_MASK
0x1UL
|
|
#define
|
_SDIO_IEN_CMDCOMSEN_SHIFT
0
|
|
#define
|
_SDIO_IEN_CMDCRCERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CMDCRCERRSEN_MASK
0x20000UL
|
|
#define
|
_SDIO_IEN_CMDCRCERRSEN_SHIFT
17
|
|
#define
|
_SDIO_IEN_CMDENDBITERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CMDENDBITERRSEN_MASK
0x40000UL
|
|
#define
|
_SDIO_IEN_CMDENDBITERRSEN_SHIFT
18
|
|
#define
|
_SDIO_IEN_CMDINDEXERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CMDINDEXERRSEN_MASK
0x80000UL
|
|
#define
|
_SDIO_IEN_CMDINDEXERRSEN_SHIFT
19
|
|
#define
|
_SDIO_IEN_CMDTOUTERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CMDTOUTERRSEN_MASK
0x10000UL
|
|
#define
|
_SDIO_IEN_CMDTOUTERRSEN_SHIFT
16
|
|
#define
|
_SDIO_IEN_CURRENTLIMITERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_CURRENTLIMITERRSEN_MASK
0x800000UL
|
|
#define
|
_SDIO_IEN_CURRENTLIMITERRSEN_SHIFT
23
|
|
#define
|
_SDIO_IEN_DATCRCERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_DATCRCERRSEN_MASK
0x200000UL
|
|
#define
|
_SDIO_IEN_DATCRCERRSEN_SHIFT
21
|
|
#define
|
_SDIO_IEN_DATENDBITERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_DATENDBITERRSEN_MASK
0x400000UL
|
|
#define
|
_SDIO_IEN_DATENDBITERRSEN_SHIFT
22
|
|
#define
|
_SDIO_IEN_DATTOUTERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_DATTOUTERRSEN_MASK
0x100000UL
|
|
#define
|
_SDIO_IEN_DATTOUTERRSEN_SHIFT
20
|
|
#define
|
_SDIO_IEN_DMAINTSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_DMAINTSEN_MASK
0x8UL
|
|
#define
|
_SDIO_IEN_DMAINTSEN_SHIFT
3
|
|
#define
|
_SDIO_IEN_MASK
0x17FF71FFUL
|
|
#define
|
_SDIO_IEN_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_IEN_RETUNINGEVTSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_RETUNINGEVTSEN_MASK
0x1000UL
|
|
#define
|
_SDIO_IEN_RETUNINGEVTSEN_SHIFT
12
|
|
#define
|
_SDIO_IEN_TARGETRESPERRSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_TARGETRESPERRSEN_MASK
0x10000000UL
|
|
#define
|
_SDIO_IEN_TARGETRESPERRSEN_SHIFT
28
|
|
#define
|
_SDIO_IEN_TRANCOMSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_TRANCOMSEN_MASK
0x2UL
|
|
#define
|
_SDIO_IEN_TRANCOMSEN_SHIFT
1
|
|
#define
|
_SDIO_IEN_TUNINGERRSIGNALENABLE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IEN_TUNINGERRSIGNALENABLE_MASK
0x4000000UL
|
|
#define
|
_SDIO_IEN_TUNINGERRSIGNALENABLE_SHIFT
26
|
|
#define
|
_SDIO_IFCR_ADMAERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_ADMAERR_MASK
0x2000000UL
|
|
#define
|
_SDIO_IFCR_ADMAERR_SHIFT
25
|
|
#define
|
_SDIO_IFCR_AUTOCMDERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_AUTOCMDERR_MASK
0x1000000UL
|
|
#define
|
_SDIO_IFCR_AUTOCMDERR_SHIFT
24
|
|
#define
|
_SDIO_IFCR_BFRRDRDY_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_BFRRDRDY_MASK
0x20UL
|
|
#define
|
_SDIO_IFCR_BFRRDRDY_SHIFT
5
|
|
#define
|
_SDIO_IFCR_BFRWRRDY_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_BFRWRRDY_MASK
0x10UL
|
|
#define
|
_SDIO_IFCR_BFRWRRDY_SHIFT
4
|
|
#define
|
_SDIO_IFCR_BLKGAPEVT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_BLKGAPEVT_MASK
0x4UL
|
|
#define
|
_SDIO_IFCR_BLKGAPEVT_SHIFT
2
|
|
#define
|
_SDIO_IFCR_BOOTACKRCV_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_BOOTACKRCV_MASK
0x2000UL
|
|
#define
|
_SDIO_IFCR_BOOTACKRCV_SHIFT
13
|
|
#define
|
_SDIO_IFCR_BOOTTERMINATE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_BOOTTERMINATE_MASK
0x4000UL
|
|
#define
|
_SDIO_IFCR_BOOTTERMINATE_SHIFT
14
|
|
#define
|
_SDIO_IFCR_CARDINS_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CARDINS_MASK
0x40UL
|
|
#define
|
_SDIO_IFCR_CARDINS_SHIFT
6
|
|
#define
|
_SDIO_IFCR_CARDINT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CARDINT_MASK
0x100UL
|
|
#define
|
_SDIO_IFCR_CARDINT_SHIFT
8
|
|
#define
|
_SDIO_IFCR_CARDRM_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CARDRM_MASK
0x80UL
|
|
#define
|
_SDIO_IFCR_CARDRM_SHIFT
7
|
|
#define
|
_SDIO_IFCR_CMDCOM_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CMDCOM_MASK
0x1UL
|
|
#define
|
_SDIO_IFCR_CMDCOM_SHIFT
0
|
|
#define
|
_SDIO_IFCR_CMDCRCERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CMDCRCERR_MASK
0x20000UL
|
|
#define
|
_SDIO_IFCR_CMDCRCERR_SHIFT
17
|
|
#define
|
_SDIO_IFCR_CMDENDBITERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CMDENDBITERR_MASK
0x40000UL
|
|
#define
|
_SDIO_IFCR_CMDENDBITERR_SHIFT
18
|
|
#define
|
_SDIO_IFCR_CMDINDEXERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CMDINDEXERR_MASK
0x80000UL
|
|
#define
|
_SDIO_IFCR_CMDINDEXERR_SHIFT
19
|
|
#define
|
_SDIO_IFCR_CMDTOUTERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CMDTOUTERR_MASK
0x10000UL
|
|
#define
|
_SDIO_IFCR_CMDTOUTERR_SHIFT
16
|
|
#define
|
_SDIO_IFCR_CURRENTLIMITERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_CURRENTLIMITERR_MASK
0x800000UL
|
|
#define
|
_SDIO_IFCR_CURRENTLIMITERR_SHIFT
23
|
|
#define
|
_SDIO_IFCR_DATCRCERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_DATCRCERR_MASK
0x200000UL
|
|
#define
|
_SDIO_IFCR_DATCRCERR_SHIFT
21
|
|
#define
|
_SDIO_IFCR_DATENDBITERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_DATENDBITERR_MASK
0x400000UL
|
|
#define
|
_SDIO_IFCR_DATENDBITERR_SHIFT
22
|
|
#define
|
_SDIO_IFCR_DATTOUTERR_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_DATTOUTERR_MASK
0x100000UL
|
|
#define
|
_SDIO_IFCR_DATTOUTERR_SHIFT
20
|
|
#define
|
_SDIO_IFCR_DMAINT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_DMAINT_MASK
0x8UL
|
|
#define
|
_SDIO_IFCR_DMAINT_SHIFT
3
|
|
#define
|
_SDIO_IFCR_ERRINT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_ERRINT_MASK
0x8000UL
|
|
#define
|
_SDIO_IFCR_ERRINT_SHIFT
15
|
|
#define
|
_SDIO_IFCR_MASK
0x13FFF1FFUL
|
|
#define
|
_SDIO_IFCR_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_IFCR_RETUNINGEVT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_RETUNINGEVT_MASK
0x1000UL
|
|
#define
|
_SDIO_IFCR_RETUNINGEVT_SHIFT
12
|
|
#define
|
_SDIO_IFCR_TARGETRESP_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_TARGETRESP_MASK
0x10000000UL
|
|
#define
|
_SDIO_IFCR_TARGETRESP_SHIFT
28
|
|
#define
|
_SDIO_IFCR_TRANCOM_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFCR_TRANCOM_MASK
0x2UL
|
|
#define
|
_SDIO_IFCR_TRANCOM_SHIFT
1
|
|
#define
|
_SDIO_IFENC_ADMAERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_ADMAERREN_MASK
0x2000000UL
|
|
#define
|
_SDIO_IFENC_ADMAERREN_SHIFT
25
|
|
#define
|
_SDIO_IFENC_AUTOCMDERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_AUTOCMDERREN_MASK
0x1000000UL
|
|
#define
|
_SDIO_IFENC_AUTOCMDERREN_SHIFT
24
|
|
#define
|
_SDIO_IFENC_BLKGAPEVTEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_BLKGAPEVTEN_MASK
0x4UL
|
|
#define
|
_SDIO_IFENC_BLKGAPEVTEN_SHIFT
2
|
|
#define
|
_SDIO_IFENC_BOOTACKRCVEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_BOOTACKRCVEN_MASK
0x2000UL
|
|
#define
|
_SDIO_IFENC_BOOTACKRCVEN_SHIFT
13
|
|
#define
|
_SDIO_IFENC_BOOTTERMINATEEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_BOOTTERMINATEEN_MASK
0x4000UL
|
|
#define
|
_SDIO_IFENC_BOOTTERMINATEEN_SHIFT
14
|
|
#define
|
_SDIO_IFENC_BUFRDRDYEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_BUFRDRDYEN_MASK
0x20UL
|
|
#define
|
_SDIO_IFENC_BUFRDRDYEN_SHIFT
5
|
|
#define
|
_SDIO_IFENC_BUFWRRDYEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_BUFWRRDYEN_MASK
0x10UL
|
|
#define
|
_SDIO_IFENC_BUFWRRDYEN_SHIFT
4
|
|
#define
|
_SDIO_IFENC_CARDINSEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CARDINSEN_MASK
0x40UL
|
|
#define
|
_SDIO_IFENC_CARDINSEN_SHIFT
6
|
|
#define
|
_SDIO_IFENC_CARDINTEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CARDINTEN_MASK
0x100UL
|
|
#define
|
_SDIO_IFENC_CARDINTEN_SHIFT
8
|
|
#define
|
_SDIO_IFENC_CARDRMEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CARDRMEN_MASK
0x80UL
|
|
#define
|
_SDIO_IFENC_CARDRMEN_SHIFT
7
|
|
#define
|
_SDIO_IFENC_CMDCOMEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CMDCOMEN_MASK
0x1UL
|
|
#define
|
_SDIO_IFENC_CMDCOMEN_SHIFT
0
|
|
#define
|
_SDIO_IFENC_CMDCRCERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CMDCRCERREN_MASK
0x20000UL
|
|
#define
|
_SDIO_IFENC_CMDCRCERREN_SHIFT
17
|
|
#define
|
_SDIO_IFENC_CMDENDBITERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CMDENDBITERREN_MASK
0x40000UL
|
|
#define
|
_SDIO_IFENC_CMDENDBITERREN_SHIFT
18
|
|
#define
|
_SDIO_IFENC_CMDINDEXERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CMDINDEXERREN_MASK
0x80000UL
|
|
#define
|
_SDIO_IFENC_CMDINDEXERREN_SHIFT
19
|
|
#define
|
_SDIO_IFENC_CMDTOUTERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CMDTOUTERREN_MASK
0x10000UL
|
|
#define
|
_SDIO_IFENC_CMDTOUTERREN_SHIFT
16
|
|
#define
|
_SDIO_IFENC_CURRENTLIMITERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_CURRENTLIMITERREN_MASK
0x800000UL
|
|
#define
|
_SDIO_IFENC_CURRENTLIMITERREN_SHIFT
23
|
|
#define
|
_SDIO_IFENC_DATCRCERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_DATCRCERREN_MASK
0x200000UL
|
|
#define
|
_SDIO_IFENC_DATCRCERREN_SHIFT
21
|
|
#define
|
_SDIO_IFENC_DATENDBITERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_DATENDBITERREN_MASK
0x400000UL
|
|
#define
|
_SDIO_IFENC_DATENDBITERREN_SHIFT
22
|
|
#define
|
_SDIO_IFENC_DATTOUTERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_DATTOUTERREN_MASK
0x100000UL
|
|
#define
|
_SDIO_IFENC_DATTOUTERREN_SHIFT
20
|
|
#define
|
_SDIO_IFENC_DMAINTEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_DMAINTEN_MASK
0x8UL
|
|
#define
|
_SDIO_IFENC_DMAINTEN_SHIFT
3
|
|
#define
|
_SDIO_IFENC_MASK
0x17FF71FFUL
|
|
#define
|
_SDIO_IFENC_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_IFENC_RETUNINGEVTEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_RETUNINGEVTEN_MASK
0x1000UL
|
|
#define
|
_SDIO_IFENC_RETUNINGEVTEN_SHIFT
12
|
|
#define
|
_SDIO_IFENC_TARGETRESPEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_TARGETRESPEN_MASK
0x10000000UL
|
|
#define
|
_SDIO_IFENC_TARGETRESPEN_SHIFT
28
|
|
#define
|
_SDIO_IFENC_TRANCOMEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_TRANCOMEN_MASK
0x2UL
|
|
#define
|
_SDIO_IFENC_TRANCOMEN_SHIFT
1
|
|
#define
|
_SDIO_IFENC_TUNINGERREN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_IFENC_TUNINGERREN_MASK
0x4000000UL
|
|
#define
|
_SDIO_IFENC_TUNINGERREN_SHIFT
26
|
|
#define
|
_SDIO_MAXCURCAPAB_MASK
0x00FFFFFFUL
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR1P8VAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR1P8VAL_MASK
0xFF0000UL
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR1P8VAL_SHIFT
16
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR3P0VAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR3P0VAL_MASK
0xFF00UL
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR3P0VAL_SHIFT
8
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR3P3VAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR3P3VAL_MASK
0xFFUL
|
|
#define
|
_SDIO_MAXCURCAPAB_MAXCUR3P3VAL_SHIFT
0
|
|
#define
|
_SDIO_MAXCURCAPAB_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_BUFFERWRITEENABLE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_BUFFERWRITEENABLE_MASK
0x400UL
|
|
#define
|
_SDIO_PRSSTAT_BUFFERWRITEENABLE_SHIFT
10
|
|
#define
|
_SDIO_PRSSTAT_BUFRDEN_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_BUFRDEN_MASK
0x800UL
|
|
#define
|
_SDIO_PRSSTAT_BUFRDEN_SHIFT
11
|
|
#define
|
_SDIO_PRSSTAT_CARDDETPINLVL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_CARDDETPINLVL_MASK
0x40000UL
|
|
#define
|
_SDIO_PRSSTAT_CARDDETPINLVL_SHIFT
18
|
|
#define
|
_SDIO_PRSSTAT_CARDINS_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_CARDINS_MASK
0x10000UL
|
|
#define
|
_SDIO_PRSSTAT_CARDINS_SHIFT
16
|
|
#define
|
_SDIO_PRSSTAT_CARDSTATESTABLE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_CARDSTATESTABLE_MASK
0x20000UL
|
|
#define
|
_SDIO_PRSSTAT_CARDSTATESTABLE_SHIFT
17
|
|
#define
|
_SDIO_PRSSTAT_CMDINHIBITCMD_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_CMDINHIBITCMD_MASK
0x1UL
|
|
#define
|
_SDIO_PRSSTAT_CMDINHIBITCMD_SHIFT
0
|
|
#define
|
_SDIO_PRSSTAT_CMDINHIBITDAT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_CMDINHIBITDAT_MASK
0x2UL
|
|
#define
|
_SDIO_PRSSTAT_CMDINHIBITDAT_SHIFT
1
|
|
#define
|
_SDIO_PRSSTAT_CMDSIGLVL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_CMDSIGLVL_MASK
0x1000000UL
|
|
#define
|
_SDIO_PRSSTAT_CMDSIGLVL_SHIFT
24
|
|
#define
|
_SDIO_PRSSTAT_DAT3TO0SIGLVL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_DAT3TO0SIGLVL_MASK
0xF00000UL
|
|
#define
|
_SDIO_PRSSTAT_DAT3TO0SIGLVL_SHIFT
20
|
|
#define
|
_SDIO_PRSSTAT_DAT7TO4SIGLVL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_DAT7TO4SIGLVL_MASK
0x1E000000UL
|
|
#define
|
_SDIO_PRSSTAT_DAT7TO4SIGLVL_SHIFT
25
|
|
#define
|
_SDIO_PRSSTAT_DATLINEACTIVE_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_DATLINEACTIVE_MASK
0x4UL
|
|
#define
|
_SDIO_PRSSTAT_DATLINEACTIVE_SHIFT
2
|
|
#define
|
_SDIO_PRSSTAT_MASK
0x1FFF0F0FUL
|
|
#define
|
_SDIO_PRSSTAT_RDTRANACT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_RDTRANACT_MASK
0x200UL
|
|
#define
|
_SDIO_PRSSTAT_RDTRANACT_SHIFT
9
|
|
#define
|
_SDIO_PRSSTAT_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_RETUNINGREQ_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_RETUNINGREQ_MASK
0x8UL
|
|
#define
|
_SDIO_PRSSTAT_RETUNINGREQ_SHIFT
3
|
|
#define
|
_SDIO_PRSSTAT_WRPROTSWPINLVL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_WRPROTSWPINLVL_MASK
0x80000UL
|
|
#define
|
_SDIO_PRSSTAT_WRPROTSWPINLVL_SHIFT
19
|
|
#define
|
_SDIO_PRSSTAT_WRTRANACT_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSSTAT_WRTRANACT_MASK
0x100UL
|
|
#define
|
_SDIO_PRSSTAT_WRTRANACT_SHIFT
8
|
|
#define
|
_SDIO_PRSTVAL0_DSPCLKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPCLKGENVAL_MASK
0x4000000UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPCLKGENVAL_SHIFT
26
|
|
#define
|
_SDIO_PRSTVAL0_DSPDRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPDRVSTVAL_MASK
0xC0000000UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPDRVSTVAL_SHIFT
30
|
|
#define
|
_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPDRVSTVAL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPSDCLKFREQVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPSDCLKFREQVAL_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_PRSTVAL0_DSPSDCLKFREQVAL_SHIFT
16
|
|
#define
|
_SDIO_PRSTVAL0_INITCLCKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_INITCLCKGENVAL_MASK
0x400UL
|
|
#define
|
_SDIO_PRSTVAL0_INITCLCKGENVAL_SHIFT
10
|
|
#define
|
_SDIO_PRSTVAL0_INITDRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_INITDRVSTVAL_MASK
0xC000UL
|
|
#define
|
_SDIO_PRSTVAL0_INITDRVSTVAL_SHIFT
14
|
|
#define
|
_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_INITDRVSTVAL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_PRSTVAL0_INITDRVSTVAL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_PRSTVAL0_INITSDCLKFREQVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL0_INITSDCLKFREQVAL_MASK
0x3FFUL
|
|
#define
|
_SDIO_PRSTVAL0_INITSDCLKFREQVAL_SHIFT
0
|
|
#define
|
_SDIO_PRSTVAL0_MASK
0xC7FFC7FFUL
|
|
#define
|
_SDIO_PRSTVAL0_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPCLKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPCLKGENVAL_MASK
0x400UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPCLKGENVAL_SHIFT
10
|
|
#define
|
_SDIO_PRSTVAL2_HSPDRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPDRVSTVAL_MASK
0xC000UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPDRVSTVAL_SHIFT
14
|
|
#define
|
_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPDRVSTVAL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPSDCLKFREQVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_HSPSDCLKFREQVAL_MASK
0x3FFUL
|
|
#define
|
_SDIO_PRSTVAL2_HSPSDCLKFREQVAL_SHIFT
0
|
|
#define
|
_SDIO_PRSTVAL2_MASK
0xC7FFC7FFUL
|
|
#define
|
_SDIO_PRSTVAL2_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12CLKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12CLKGENVAL_MASK
0x4000000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12CLKGENVAL_SHIFT
26
|
|
#define
|
_SDIO_PRSTVAL2_SDR12DRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12DRVSTVAL_MASK
0xC0000000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12DRVSTVAL_SHIFT
30
|
|
#define
|
_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12DRVSTVAL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_PRSTVAL2_SDR12SDCLKFREQVAL_SHIFT
16
|
|
#define
|
_SDIO_PRSTVAL4_MASK
0xC7FFC7FFUL
|
|
#define
|
_SDIO_PRSTVAL4_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25CLKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25CLKGENVAL_MASK
0x400UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25CLKGENVAL_SHIFT
10
|
|
#define
|
_SDIO_PRSTVAL4_SDR25DRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25DRVSTVAL_MASK
0xC000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25DRVSTVAL_SHIFT
14
|
|
#define
|
_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25DRVSTVAL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_MASK
0x3FFUL
|
|
#define
|
_SDIO_PRSTVAL4_SDR25SDCLKFREQVAL_SHIFT
0
|
|
#define
|
_SDIO_PRSTVAL4_SDR50CLCKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50CLCKGENVAL_MASK
0x4000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50CLCKGENVAL_SHIFT
26
|
|
#define
|
_SDIO_PRSTVAL4_SDR50DRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50DRVSTVAL_MASK
0xC0000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50DRVSTVAL_SHIFT
30
|
|
#define
|
_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50DRVSTVAL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_PRSTVAL4_SDR50SDCLKFREQVAL_SHIFT
16
|
|
#define
|
_SDIO_PRSTVAL6_DDR50CLKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50CLKGENVAL_MASK
0x4000000UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50CLKGENVAL_SHIFT
26
|
|
#define
|
_SDIO_PRSTVAL6_DDR50DRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50DRVSTVAL_MASK
0xC0000000UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50DRVSTVAL_SHIFT
30
|
|
#define
|
_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEA
0x00000001UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEB
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPEC
0x00000002UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50DRVSTVAL_TYPED
0x00000003UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_MASK
0x3FF0000UL
|
|
#define
|
_SDIO_PRSTVAL6_DDR50SDCLKFREQVAL_SHIFT
16
|
|
#define
|
_SDIO_PRSTVAL6_MASK
0xC7FFC7FFUL
|
|
#define
|
_SDIO_PRSTVAL6_RESETVALUE
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL6_SDR104CLKGENVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL6_SDR104CLKGENVAL_MASK
0x400UL
|
|
#define
|
_SDIO_PRSTVAL6_SDR104CLKGENVAL_SHIFT
10
|
|
#define
|
_SDIO_PRSTVAL6_SDR104DRVSTVAL_DEFAULT
0x00000000UL
|
|
#define
|
_SDIO_PRSTVAL6_SDR104DRVSTVAL_MASK
0xC000UL
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#define
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_SDIO_PRSTVAL6_SDR104DRVSTVAL_SHIFT
14
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#define
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_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEA
0x00000001UL
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#define
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_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEB
0x00000000UL
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#define
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_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPEC
0x00000002UL
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#define
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_SDIO_PRSTVAL6_SDR104DRVSTVAL_TYPED
0x00000003UL
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#define
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_SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_DEFAULT
0x00000000UL
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#define
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_SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_MASK
0x3FFUL
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#define
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_SDIO_PRSTVAL6_SDR104SDCLKFREQVAL_SHIFT
0
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#define
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_SDIO_RESP0_CMDRESP0_DEFAULT
0x00000000UL
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#define
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_SDIO_RESP0_CMDRESP0_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP0_CMDRESP0_SHIFT
0
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#define
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_SDIO_RESP0_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP0_RESETVALUE
0x00000000UL
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#define
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_SDIO_RESP2_CMDRESP1_DEFAULT
0x00000000UL
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#define
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_SDIO_RESP2_CMDRESP1_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP2_CMDRESP1_SHIFT
0
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#define
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_SDIO_RESP2_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP2_RESETVALUE
0x00000000UL
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#define
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_SDIO_RESP4_CMDRESP2_DEFAULT
0x00000000UL
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#define
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_SDIO_RESP4_CMDRESP2_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP4_CMDRESP2_SHIFT
0
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#define
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_SDIO_RESP4_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP4_RESETVALUE
0x00000000UL
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#define
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_SDIO_RESP6_CMDRESP3_DEFAULT
0x00000000UL
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#define
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_SDIO_RESP6_CMDRESP3_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP6_CMDRESP3_SHIFT
0
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#define
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_SDIO_RESP6_MASK
0xFFFFFFFFUL
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#define
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_SDIO_RESP6_RESETVALUE
0x00000000UL
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#define
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_SDIO_ROUTELOC0_CDLOC_DEFAULT
0x00000000UL
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#define
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_SDIO_ROUTELOC0_CDLOC_LOC0
0x00000000UL
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#define
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_SDIO_ROUTELOC0_CDLOC_LOC1
0x00000001UL
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#define
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_SDIO_ROUTELOC0_CDLOC_LOC2
0x00000002UL
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#define
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_SDIO_ROUTELOC0_CDLOC_LOC3
0x00000003UL
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#define
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_SDIO_ROUTELOC0_CDLOC_MASK
0x300UL
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#define
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_SDIO_ROUTELOC0_CDLOC_SHIFT
8
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#define
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_SDIO_ROUTELOC0_CLKLOC_DEFAULT
0x00000000UL
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#define
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_SDIO_ROUTELOC0_CLKLOC_LOC0
0x00000000UL
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#define
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_SDIO_ROUTELOC0_CLKLOC_LOC1
0x00000001UL
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#define
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_SDIO_ROUTELOC0_CLKLOC_MASK
0x1000000UL
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#define
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_SDIO_ROUTELOC0_CLKLOC_SHIFT
24
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#define
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_SDIO_ROUTELOC0_DATLOC_DEFAULT
0x00000000UL
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#define
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_SDIO_ROUTELOC0_DATLOC_LOC0
0x00000000UL
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#define
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_SDIO_ROUTELOC0_DATLOC_LOC1
0x00000001UL
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#define
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_SDIO_ROUTELOC0_DATLOC_MASK
0x1UL
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#define
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_SDIO_ROUTELOC0_DATLOC_SHIFT
0
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#define
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_SDIO_ROUTELOC0_MASK
0x01030301UL
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#define
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_SDIO_ROUTELOC0_RESETVALUE
0x00000000UL
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#define
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_SDIO_ROUTELOC0_WPLOC_DEFAULT
0x00000000UL
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#define
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_SDIO_ROUTELOC0_WPLOC_LOC0
0x00000000UL
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#define
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_SDIO_ROUTELOC0_WPLOC_LOC1
0x00000001UL
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#define
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_SDIO_ROUTELOC0_WPLOC_LOC2
0x00000002UL
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#define
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_SDIO_ROUTELOC0_WPLOC_LOC3
0x00000003UL
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#define
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_SDIO_ROUTELOC0_WPLOC_MASK
0x30000UL
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#define
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|