MSC Bit FieldsDevices > MSC

Macros

#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL
#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0
#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
#define _MSC_ADDRB_ADDRB_SHIFT 0
#define _MSC_ADDRB_MASK 0xFFFFFFFFUL
#define _MSC_ADDRB_RESETVALUE 0x00000000UL
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL
#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL
#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL
#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL
#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL
#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0
#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL
#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL
#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1
#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL
#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL
#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL
#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL
#define _MSC_CACHECMD_INVCACHE_SHIFT 0
#define _MSC_CACHECMD_MASK 0x00000007UL
#define _MSC_CACHECMD_RESETVALUE 0x00000000UL
#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL
#define _MSC_CACHECMD_STARTPC_MASK 0x2UL
#define _MSC_CACHECMD_STARTPC_SHIFT 1
#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL
#define _MSC_CACHECMD_STOPPC_MASK 0x4UL
#define _MSC_CACHECMD_STOPPC_SHIFT 2
#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL
#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL
#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL
#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL
#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL
#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0
#define _MSC_CACHECONFIG0_MASK 0x00000003UL
#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL
#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL
#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL
#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0
#define _MSC_CACHEHITS_MASK 0x000FFFFFUL
#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL
#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL
#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL
#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0
#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL
#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL
#define _MSC_CMD_MASK 0x00000003UL
#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL
#define _MSC_CMD_PWRUP_MASK 0x1UL
#define _MSC_CMD_PWRUP_SHIFT 0
#define _MSC_CMD_RESETVALUE 0x00000000UL
#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL
#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL
#define _MSC_CMD_SWITCHINGBANK_SHIFT 1
#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL
#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL
#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0
#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL
#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL
#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1
#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL
#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL
#define _MSC_CTRL_EBIFAULTEN_SHIFT 6
#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL
#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL
#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3
#define _MSC_CTRL_MASK 0x0000107FUL
#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL
#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL
#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2
#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL
#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL
#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5
#define _MSC_CTRL_RESETVALUE 0x00000021UL
#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL
#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL
#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4
#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL
#define _MSC_CTRL_WAITMODE_MASK 0x1000UL
#define _MSC_CTRL_WAITMODE_SHIFT 12
#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL
#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL
#define _MSC_ECCCTRL_MASK 0x0000000FUL
#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL
#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL
#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3
#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL
#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL
#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2
#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL
#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL
#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1
#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL
#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL
#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0
#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL
#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL
#define _MSC_IEN_CHOF_MASK 0x4UL
#define _MSC_IEN_CHOF_SHIFT 2
#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL
#define _MSC_IEN_CMOF_MASK 0x8UL
#define _MSC_IEN_CMOF_SHIFT 3
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
#define _MSC_IEN_ERASE_MASK 0x1UL
#define _MSC_IEN_ERASE_SHIFT 0
#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IEN_ICACHERR_MASK 0x20UL
#define _MSC_IEN_ICACHERR_SHIFT 5
#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL
#define _MSC_IEN_LVEWRITE_MASK 0x100UL
#define _MSC_IEN_LVEWRITE_SHIFT 8
#define _MSC_IEN_MASK 0x000F017FUL
#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IEN_PWRUPF_MASK 0x10UL
#define _MSC_IEN_PWRUPF_SHIFT 4
#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL
#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL
#define _MSC_IEN_RAM1ERR1B_SHIFT 18
#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL
#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL
#define _MSC_IEN_RAM1ERR2B_SHIFT 19
#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL
#define _MSC_IEN_RAMERR1B_MASK 0x10000UL
#define _MSC_IEN_RAMERR1B_SHIFT 16
#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL
#define _MSC_IEN_RAMERR2B_MASK 0x20000UL
#define _MSC_IEN_RAMERR2B_SHIFT 17
#define _MSC_IEN_RESETVALUE 0x00000000UL
#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL
#define _MSC_IEN_WDATAOV_MASK 0x40UL
#define _MSC_IEN_WDATAOV_SHIFT 6
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
#define _MSC_IEN_WRITE_MASK 0x2UL
#define _MSC_IEN_WRITE_SHIFT 1
#define _MSC_IF_CHOF_DEFAULT 0x00000000UL
#define _MSC_IF_CHOF_MASK 0x4UL
#define _MSC_IF_CHOF_SHIFT 2
#define _MSC_IF_CMOF_DEFAULT 0x00000000UL
#define _MSC_IF_CMOF_MASK 0x8UL
#define _MSC_IF_CMOF_SHIFT 3
#define _MSC_IF_ERASE_DEFAULT 0x00000000UL
#define _MSC_IF_ERASE_MASK 0x1UL
#define _MSC_IF_ERASE_SHIFT 0
#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IF_ICACHERR_MASK 0x20UL
#define _MSC_IF_ICACHERR_SHIFT 5
#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL
#define _MSC_IF_LVEWRITE_MASK 0x100UL
#define _MSC_IF_LVEWRITE_SHIFT 8
#define _MSC_IF_MASK 0x000F017FUL
#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IF_PWRUPF_MASK 0x10UL
#define _MSC_IF_PWRUPF_SHIFT 4
#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL
#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL
#define _MSC_IF_RAM1ERR1B_SHIFT 18
#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL
#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL
#define _MSC_IF_RAM1ERR2B_SHIFT 19
#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL
#define _MSC_IF_RAMERR1B_MASK 0x10000UL
#define _MSC_IF_RAMERR1B_SHIFT 16
#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL
#define _MSC_IF_RAMERR2B_MASK 0x20000UL
#define _MSC_IF_RAMERR2B_SHIFT 17
#define _MSC_IF_RESETVALUE 0x00000000UL
#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL
#define _MSC_IF_WDATAOV_MASK 0x40UL
#define _MSC_IF_WDATAOV_SHIFT 6
#define _MSC_IF_WRITE_DEFAULT 0x00000000UL
#define _MSC_IF_WRITE_MASK 0x2UL
#define _MSC_IF_WRITE_SHIFT 1
#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL
#define _MSC_IFC_CHOF_MASK 0x4UL
#define _MSC_IFC_CHOF_SHIFT 2
#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL
#define _MSC_IFC_CMOF_MASK 0x8UL
#define _MSC_IFC_CMOF_SHIFT 3
#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
#define _MSC_IFC_ERASE_MASK 0x1UL
#define _MSC_IFC_ERASE_SHIFT 0
#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IFC_ICACHERR_MASK 0x20UL
#define _MSC_IFC_ICACHERR_SHIFT 5
#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL
#define _MSC_IFC_LVEWRITE_MASK 0x100UL
#define _MSC_IFC_LVEWRITE_SHIFT 8
#define _MSC_IFC_MASK 0x000F017FUL
#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IFC_PWRUPF_MASK 0x10UL
#define _MSC_IFC_PWRUPF_SHIFT 4
#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL
#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL
#define _MSC_IFC_RAM1ERR1B_SHIFT 18
#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL
#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL
#define _MSC_IFC_RAM1ERR2B_SHIFT 19
#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL
#define _MSC_IFC_RAMERR1B_MASK 0x10000UL
#define _MSC_IFC_RAMERR1B_SHIFT 16
#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL
#define _MSC_IFC_RAMERR2B_MASK 0x20000UL
#define _MSC_IFC_RAMERR2B_SHIFT 17
#define _MSC_IFC_RESETVALUE 0x00000000UL
#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL
#define _MSC_IFC_WDATAOV_MASK 0x40UL
#define _MSC_IFC_WDATAOV_SHIFT 6
#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
#define _MSC_IFC_WRITE_MASK 0x2UL
#define _MSC_IFC_WRITE_SHIFT 1
#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL
#define _MSC_IFS_CHOF_MASK 0x4UL
#define _MSC_IFS_CHOF_SHIFT 2
#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL
#define _MSC_IFS_CMOF_MASK 0x8UL
#define _MSC_IFS_CMOF_SHIFT 3
#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
#define _MSC_IFS_ERASE_MASK 0x1UL
#define _MSC_IFS_ERASE_SHIFT 0
#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL
#define _MSC_IFS_ICACHERR_MASK 0x20UL
#define _MSC_IFS_ICACHERR_SHIFT 5
#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL
#define _MSC_IFS_LVEWRITE_MASK 0x100UL
#define _MSC_IFS_LVEWRITE_SHIFT 8
#define _MSC_IFS_MASK 0x000F017FUL
#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL
#define _MSC_IFS_PWRUPF_MASK 0x10UL
#define _MSC_IFS_PWRUPF_SHIFT 4
#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL
#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL
#define _MSC_IFS_RAM1ERR1B_SHIFT 18
#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL
#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL
#define _MSC_IFS_RAM1ERR2B_SHIFT 19
#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL
#define _MSC_IFS_RAMERR1B_MASK 0x10000UL
#define _MSC_IFS_RAMERR1B_SHIFT 16
#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL
#define _MSC_IFS_RAMERR2B_MASK 0x20000UL
#define _MSC_IFS_RAMERR2B_SHIFT 17
#define _MSC_IFS_RESETVALUE 0x00000000UL
#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL
#define _MSC_IFS_WDATAOV_MASK 0x40UL
#define _MSC_IFS_WDATAOV_SHIFT 6
#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
#define _MSC_IFS_WRITE_MASK 0x2UL
#define _MSC_IFS_WRITE_SHIFT 1
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
#define _MSC_LOCK_LOCKKEY_SHIFT 0
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define _MSC_LOCK_MASK 0x0000FFFFUL
#define _MSC_LOCK_RESETVALUE 0x00000000UL
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL
#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL
#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL
#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL
#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL
#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL
#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0
#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL
#define _MSC_RAMCTRL_MASK 0x00070707UL
#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL
#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8
#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL
#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10
#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL
#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9
#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL
#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16
#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL
#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18
#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL
#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17
#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL
#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0
#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL
#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2
#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL
#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL
#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1
#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL
#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL
#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL
#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL
#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0
#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL
#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_AIDIS_MASK 0x10UL
#define _MSC_READCTRL_AIDIS_SHIFT 4
#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_EBICDIS_MASK 0x40UL
#define _MSC_READCTRL_EBICDIS_SHIFT 6
#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_ICCDIS_MASK 0x20UL
#define _MSC_READCTRL_ICCDIS_SHIFT 5
#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_IFCDIS_MASK 0x8UL
#define _MSC_READCTRL_IFCDIS_SHIFT 3
#define _MSC_READCTRL_MASK 0x13000778UL
#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
#define _MSC_READCTRL_MODE_MASK 0x3000000UL
#define _MSC_READCTRL_MODE_SHIFT 24
#define _MSC_READCTRL_MODE_WS0 0x00000000UL
#define _MSC_READCTRL_MODE_WS1 0x00000001UL
#define _MSC_READCTRL_MODE_WS2 0x00000002UL
#define _MSC_READCTRL_MODE_WS3 0x00000003UL
#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL
#define _MSC_READCTRL_PREFETCH_MASK 0x100UL
#define _MSC_READCTRL_PREFETCH_SHIFT 8
#define _MSC_READCTRL_QSPICDIS_DEFAULT 0x00000000UL
#define _MSC_READCTRL_QSPICDIS_MASK 0x400UL
#define _MSC_READCTRL_QSPICDIS_SHIFT 10
#define _MSC_READCTRL_RESETVALUE 0x01000100UL
#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL
#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL
#define _MSC_READCTRL_SCBTP_SHIFT 28
#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL
#define _MSC_READCTRL_USEHPROT_MASK 0x200UL
#define _MSC_READCTRL_USEHPROT_SHIFT 9
#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL
#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL
#define _MSC_STARTUP_ASTWAIT_SHIFT 24
#define _MSC_STARTUP_MASK 0x773FF3FFUL
#define _MSC_STARTUP_RESETVALUE 0x13001054UL
#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL
#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL
#define _MSC_STARTUP_STDLY0_SHIFT 0
#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL
#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL
#define _MSC_STARTUP_STDLY1_SHIFT 12
#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL
#define _MSC_STARTUP_STWS_MASK 0x70000000UL
#define _MSC_STARTUP_STWS_SHIFT 28
#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL
#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL
#define _MSC_STARTUP_STWSAEN_SHIFT 26
#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL
#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL
#define _MSC_STARTUP_STWSEN_SHIFT 25
#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL
#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL
#define _MSC_STATUS_BANKSWITCHED_SHIFT 7
#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
#define _MSC_STATUS_BUSY_MASK 0x1UL
#define _MSC_STATUS_BUSY_SHIFT 0
#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
#define _MSC_STATUS_ERASEABORTED_SHIFT 5
#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
#define _MSC_STATUS_INVADDR_MASK 0x4UL
#define _MSC_STATUS_INVADDR_SHIFT 2
#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
#define _MSC_STATUS_LOCKED_MASK 0x2UL
#define _MSC_STATUS_LOCKED_SHIFT 1
#define _MSC_STATUS_MASK 0xFF0000FFUL
#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL
#define _MSC_STATUS_PCRUNNING_MASK 0x40UL
#define _MSC_STATUS_PCRUNNING_SHIFT 6
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28
#define _MSC_STATUS_RESETVALUE 0x00000008UL
#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
#define _MSC_STATUS_WDATAREADY_MASK 0x8UL
#define _MSC_STATUS_WDATAREADY_SHIFT 3
#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL
#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL
#define _MSC_STATUS_WDATAVALID_SHIFT 24
#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
#define _MSC_WDATA_MASK 0xFFFFFFFFUL
#define _MSC_WDATA_RESETVALUE 0x00000000UL
#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
#define _MSC_WDATA_WDATA_SHIFT 0
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8
#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL
#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9
#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
#define _MSC_WRITECMD_LADDRIM_SHIFT 0
#define _MSC_WRITECMD_MASK 0x0000133FUL
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
#define _MSC_WRITECMD_WRITEEND_SHIFT 2
#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
#define _MSC_WRITECMD_WRITEONCE_SHIFT 3
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
#define _MSC_WRITECMD_WRITETRIG_SHIFT 4
#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
#define _MSC_WRITECTRL_MASK 0x00000023UL
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL
#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL
#define _MSC_WRITECTRL_RWWEN_SHIFT 5
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
#define _MSC_WRITECTRL_WREN_MASK 0x1UL
#define _MSC_WRITECTRL_WREN_SHIFT 0
#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0)
#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT ( _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0)
#define MSC_ADDRB_ADDRB_DEFAULT ( _MSC_ADDRB_ADDRB_DEFAULT << 0)
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT ( _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0)
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK ( _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0)
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED ( _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0)
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK ( _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0)
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED ( _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0)
#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0)
#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT ( _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0)
#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1)
#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT ( _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1)
#define MSC_CACHECMD_INVCACHE (0x1UL << 0)
#define MSC_CACHECMD_INVCACHE_DEFAULT ( _MSC_CACHECMD_INVCACHE_DEFAULT << 0)
#define MSC_CACHECMD_STARTPC (0x1UL << 1)
#define MSC_CACHECMD_STARTPC_DEFAULT ( _MSC_CACHECMD_STARTPC_DEFAULT << 1)
#define MSC_CACHECMD_STOPPC (0x1UL << 2)
#define MSC_CACHECMD_STOPPC_DEFAULT ( _MSC_CACHECMD_STOPPC_DEFAULT << 2)
#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED ( _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0)
#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE ( _MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0)
#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT ( _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0)
#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY ( _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0)
#define MSC_CACHEHITS_CACHEHITS_DEFAULT ( _MSC_CACHEHITS_CACHEHITS_DEFAULT << 0)
#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT ( _MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0)
#define MSC_CMD_PWRUP (0x1UL << 0)
#define MSC_CMD_PWRUP_DEFAULT ( _MSC_CMD_PWRUP_DEFAULT << 0)
#define MSC_CMD_SWITCHINGBANK (0x1UL << 1)
#define MSC_CMD_SWITCHINGBANK_DEFAULT ( _MSC_CMD_SWITCHINGBANK_DEFAULT << 1)
#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0)
#define MSC_CTRL_ADDRFAULTEN_DEFAULT ( _MSC_CTRL_ADDRFAULTEN_DEFAULT << 0)
#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1)
#define MSC_CTRL_CLKDISFAULTEN_DEFAULT ( _MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1)
#define MSC_CTRL_EBIFAULTEN (0x1UL << 6)
#define MSC_CTRL_EBIFAULTEN_DEFAULT ( _MSC_CTRL_EBIFAULTEN_DEFAULT << 6)
#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3)
#define MSC_CTRL_IFCREADCLEAR_DEFAULT ( _MSC_CTRL_IFCREADCLEAR_DEFAULT << 3)
#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2)
#define MSC_CTRL_PWRUPONDEMAND_DEFAULT ( _MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2)
#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5)
#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT ( _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5)
#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4)
#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT ( _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4)
#define MSC_CTRL_WAITMODE (0x1UL << 12)
#define MSC_CTRL_WAITMODE_DEFAULT ( _MSC_CTRL_WAITMODE_DEFAULT << 12)
#define MSC_CTRL_WAITMODE_WS0 ( _MSC_CTRL_WAITMODE_WS0 << 12)
#define MSC_CTRL_WAITMODE_WS1 ( _MSC_CTRL_WAITMODE_WS1 << 12)
#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3)
#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT ( _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3)
#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2)
#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT ( _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2)
#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1)
#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT ( _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1)
#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0)
#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT ( _MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0)
#define MSC_IEN_CHOF (0x1UL << 2)
#define MSC_IEN_CHOF_DEFAULT ( _MSC_IEN_CHOF_DEFAULT << 2)
#define MSC_IEN_CMOF (0x1UL << 3)
#define MSC_IEN_CMOF_DEFAULT ( _MSC_IEN_CMOF_DEFAULT << 3)
#define MSC_IEN_ERASE (0x1UL << 0)
#define MSC_IEN_ERASE_DEFAULT ( _MSC_IEN_ERASE_DEFAULT << 0)
#define MSC_IEN_ICACHERR (0x1UL << 5)
#define MSC_IEN_ICACHERR_DEFAULT ( _MSC_IEN_ICACHERR_DEFAULT << 5)
#define MSC_IEN_LVEWRITE (0x1UL << 8)
#define MSC_IEN_LVEWRITE_DEFAULT ( _MSC_IEN_LVEWRITE_DEFAULT << 8)
#define MSC_IEN_PWRUPF (0x1UL << 4)
#define MSC_IEN_PWRUPF_DEFAULT ( _MSC_IEN_PWRUPF_DEFAULT << 4)
#define MSC_IEN_RAM1ERR1B (0x1UL << 18)
#define MSC_IEN_RAM1ERR1B_DEFAULT ( _MSC_IEN_RAM1ERR1B_DEFAULT << 18)
#define MSC_IEN_RAM1ERR2B (0x1UL << 19)
#define MSC_IEN_RAM1ERR2B_DEFAULT ( _MSC_IEN_RAM1ERR2B_DEFAULT << 19)
#define MSC_IEN_RAMERR1B (0x1UL << 16)
#define MSC_IEN_RAMERR1B_DEFAULT ( _MSC_IEN_RAMERR1B_DEFAULT << 16)
#define MSC_IEN_RAMERR2B (0x1UL << 17)
#define MSC_IEN_RAMERR2B_DEFAULT ( _MSC_IEN_RAMERR2B_DEFAULT << 17)
#define MSC_IEN_WDATAOV (0x1UL << 6)
#define MSC_IEN_WDATAOV_DEFAULT ( _MSC_IEN_WDATAOV_DEFAULT << 6)
#define MSC_IEN_WRITE (0x1UL << 1)
#define MSC_IEN_WRITE_DEFAULT ( _MSC_IEN_WRITE_DEFAULT << 1)
#define MSC_IF_CHOF (0x1UL << 2)
#define MSC_IF_CHOF_DEFAULT ( _MSC_IF_CHOF_DEFAULT << 2)
#define MSC_IF_CMOF (0x1UL << 3)
#define MSC_IF_CMOF_DEFAULT ( _MSC_IF_CMOF_DEFAULT << 3)
#define MSC_IF_ERASE (0x1UL << 0)
#define MSC_IF_ERASE_DEFAULT ( _MSC_IF_ERASE_DEFAULT << 0)
#define MSC_IF_ICACHERR (0x1UL << 5)
#define MSC_IF_ICACHERR_DEFAULT ( _MSC_IF_ICACHERR_DEFAULT << 5)
#define MSC_IF_LVEWRITE (0x1UL << 8)
#define MSC_IF_LVEWRITE_DEFAULT ( _MSC_IF_LVEWRITE_DEFAULT << 8)
#define MSC_IF_PWRUPF (0x1UL << 4)
#define MSC_IF_PWRUPF_DEFAULT ( _MSC_IF_PWRUPF_DEFAULT << 4)
#define MSC_IF_RAM1ERR1B (0x1UL << 18)
#define MSC_IF_RAM1ERR1B_DEFAULT ( _MSC_IF_RAM1ERR1B_DEFAULT << 18)
#define MSC_IF_RAM1ERR2B (0x1UL << 19)
#define MSC_IF_RAM1ERR2B_DEFAULT ( _MSC_IF_RAM1ERR2B_DEFAULT << 19)
#define MSC_IF_RAMERR1B (0x1UL << 16)
#define MSC_IF_RAMERR1B_DEFAULT ( _MSC_IF_RAMERR1B_DEFAULT << 16)
#define MSC_IF_RAMERR2B (0x1UL << 17)
#define MSC_IF_RAMERR2B_DEFAULT ( _MSC_IF_RAMERR2B_DEFAULT << 17)
#define MSC_IF_WDATAOV (0x1UL << 6)
#define MSC_IF_WDATAOV_DEFAULT ( _MSC_IF_WDATAOV_DEFAULT << 6)
#define MSC_IF_WRITE (0x1UL << 1)
#define MSC_IF_WRITE_DEFAULT ( _MSC_IF_WRITE_DEFAULT << 1)
#define MSC_IFC_CHOF (0x1UL << 2)
#define MSC_IFC_CHOF_DEFAULT ( _MSC_IFC_CHOF_DEFAULT << 2)
#define MSC_IFC_CMOF (0x1UL << 3)
#define MSC_IFC_CMOF_DEFAULT ( _MSC_IFC_CMOF_DEFAULT << 3)
#define MSC_IFC_ERASE (0x1UL << 0)
#define MSC_IFC_ERASE_DEFAULT ( _MSC_IFC_ERASE_DEFAULT << 0)
#define MSC_IFC_ICACHERR (0x1UL << 5)
#define MSC_IFC_ICACHERR_DEFAULT ( _MSC_IFC_ICACHERR_DEFAULT << 5)
#define MSC_IFC_LVEWRITE (0x1UL << 8)
#define MSC_IFC_LVEWRITE_DEFAULT ( _MSC_IFC_LVEWRITE_DEFAULT << 8)
#define MSC_IFC_PWRUPF (0x1UL << 4)
#define MSC_IFC_PWRUPF_DEFAULT ( _MSC_IFC_PWRUPF_DEFAULT << 4)
#define MSC_IFC_RAM1ERR1B (0x1UL << 18)
#define MSC_IFC_RAM1ERR1B_DEFAULT ( _MSC_IFC_RAM1ERR1B_DEFAULT << 18)
#define MSC_IFC_RAM1ERR2B (0x1UL << 19)
#define MSC_IFC_RAM1ERR2B_DEFAULT ( _MSC_IFC_RAM1ERR2B_DEFAULT << 19)
#define MSC_IFC_RAMERR1B (0x1UL << 16)
#define MSC_IFC_RAMERR1B_DEFAULT ( _MSC_IFC_RAMERR1B_DEFAULT << 16)
#define MSC_IFC_RAMERR2B (0x1UL << 17)
#define MSC_IFC_RAMERR2B_DEFAULT ( _MSC_IFC_RAMERR2B_DEFAULT << 17)
#define MSC_IFC_WDATAOV (0x1UL << 6)
#define MSC_IFC_WDATAOV_DEFAULT ( _MSC_IFC_WDATAOV_DEFAULT << 6)
#define MSC_IFC_WRITE (0x1UL << 1)
#define MSC_IFC_WRITE_DEFAULT ( _MSC_IFC_WRITE_DEFAULT << 1)
#define MSC_IFS_CHOF (0x1UL << 2)
#define MSC_IFS_CHOF_DEFAULT ( _MSC_IFS_CHOF_DEFAULT << 2)
#define MSC_IFS_CMOF (0x1UL << 3)
#define MSC_IFS_CMOF_DEFAULT ( _MSC_IFS_CMOF_DEFAULT << 3)
#define MSC_IFS_ERASE (0x1UL << 0)
#define MSC_IFS_ERASE_DEFAULT ( _MSC_IFS_ERASE_DEFAULT << 0)
#define MSC_IFS_ICACHERR (0x1UL << 5)
#define MSC_IFS_ICACHERR_DEFAULT ( _MSC_IFS_ICACHERR_DEFAULT << 5)
#define MSC_IFS_LVEWRITE (0x1UL << 8)
#define MSC_IFS_LVEWRITE_DEFAULT ( _MSC_IFS_LVEWRITE_DEFAULT << 8)
#define MSC_IFS_PWRUPF (0x1UL << 4)
#define MSC_IFS_PWRUPF_DEFAULT ( _MSC_IFS_PWRUPF_DEFAULT << 4)
#define MSC_IFS_RAM1ERR1B (0x1UL << 18)
#define MSC_IFS_RAM1ERR1B_DEFAULT ( _MSC_IFS_RAM1ERR1B_DEFAULT << 18)
#define MSC_IFS_RAM1ERR2B (0x1UL << 19)
#define MSC_IFS_RAM1ERR2B_DEFAULT ( _MSC_IFS_RAM1ERR2B_DEFAULT << 19)
#define MSC_IFS_RAMERR1B (0x1UL << 16)
#define MSC_IFS_RAMERR1B_DEFAULT ( _MSC_IFS_RAMERR1B_DEFAULT << 16)
#define MSC_IFS_RAMERR2B (0x1UL << 17)
#define MSC_IFS_RAMERR2B_DEFAULT ( _MSC_IFS_RAMERR2B_DEFAULT << 17)
#define MSC_IFS_WDATAOV (0x1UL << 6)
#define MSC_IFS_WDATAOV_DEFAULT ( _MSC_IFS_WDATAOV_DEFAULT << 6)
#define MSC_IFS_WRITE (0x1UL << 1)
#define MSC_IFS_WRITE_DEFAULT ( _MSC_IFS_WRITE_DEFAULT << 1)
#define MSC_LOCK_LOCKKEY_DEFAULT ( _MSC_LOCK_LOCKKEY_DEFAULT << 0)
#define MSC_LOCK_LOCKKEY_LOCK ( _MSC_LOCK_LOCKKEY_LOCK << 0)
#define MSC_LOCK_LOCKKEY_LOCKED ( _MSC_LOCK_LOCKKEY_LOCKED << 0)
#define MSC_LOCK_LOCKKEY_UNLOCK ( _MSC_LOCK_LOCKKEY_UNLOCK << 0)
#define MSC_LOCK_LOCKKEY_UNLOCKED ( _MSC_LOCK_LOCKKEY_UNLOCKED << 0)
#define MSC_MASSLOCK_LOCKKEY_DEFAULT ( _MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)
#define MSC_MASSLOCK_LOCKKEY_LOCK ( _MSC_MASSLOCK_LOCKKEY_LOCK << 0)
#define MSC_MASSLOCK_LOCKKEY_LOCKED ( _MSC_MASSLOCK_LOCKKEY_LOCKED << 0)
#define MSC_MASSLOCK_LOCKKEY_UNLOCK ( _MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED ( _MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0)
#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT ( _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0)
#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8)
#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT ( _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8)
#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10)
#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT ( _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10)
#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9)
#define MSC_RAMCTRL_RAM1WSEN_DEFAULT ( _MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9)
#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16)
#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT ( _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16)
#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18)
#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT ( _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18)
#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17)
#define MSC_RAMCTRL_RAM2WSEN_DEFAULT ( _MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17)
#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0)
#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT ( _MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0)
#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2)
#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT ( _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2)
#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1)
#define MSC_RAMCTRL_RAMWSEN_DEFAULT ( _MSC_RAMCTRL_RAMWSEN_DEFAULT << 1)
#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT ( _MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0)
#define MSC_READCTRL_AIDIS (0x1UL << 4)
#define MSC_READCTRL_AIDIS_DEFAULT ( _MSC_READCTRL_AIDIS_DEFAULT << 4)
#define MSC_READCTRL_EBICDIS (0x1UL << 6)
#define MSC_READCTRL_EBICDIS_DEFAULT ( _MSC_READCTRL_EBICDIS_DEFAULT << 6)
#define MSC_READCTRL_ICCDIS (0x1UL << 5)
#define MSC_READCTRL_ICCDIS_DEFAULT ( _MSC_READCTRL_ICCDIS_DEFAULT << 5)
#define MSC_READCTRL_IFCDIS (0x1UL << 3)
#define MSC_READCTRL_IFCDIS_DEFAULT ( _MSC_READCTRL_IFCDIS_DEFAULT << 3)
#define MSC_READCTRL_MODE_DEFAULT ( _MSC_READCTRL_MODE_DEFAULT << 24)
#define MSC_READCTRL_MODE_WS0 ( _MSC_READCTRL_MODE_WS0 << 24)
#define MSC_READCTRL_MODE_WS1 ( _MSC_READCTRL_MODE_WS1 << 24)
#define MSC_READCTRL_MODE_WS2 ( _MSC_READCTRL_MODE_WS2 << 24)
#define MSC_READCTRL_MODE_WS3 ( _MSC_READCTRL_MODE_WS3 << 24)
#define MSC_READCTRL_PREFETCH (0x1UL << 8)
#define MSC_READCTRL_PREFETCH_DEFAULT ( _MSC_READCTRL_PREFETCH_DEFAULT << 8)
#define MSC_READCTRL_QSPICDIS (0x1UL << 10)
#define MSC_READCTRL_QSPICDIS_DEFAULT ( _MSC_READCTRL_QSPICDIS_DEFAULT << 10)
#define MSC_READCTRL_SCBTP (0x1UL << 28)
#define MSC_READCTRL_SCBTP_DEFAULT ( _MSC_READCTRL_SCBTP_DEFAULT << 28)
#define MSC_READCTRL_USEHPROT (0x1UL << 9)
#define MSC_READCTRL_USEHPROT_DEFAULT ( _MSC_READCTRL_USEHPROT_DEFAULT << 9)
#define MSC_STARTUP_ASTWAIT (0x1UL << 24)
#define MSC_STARTUP_ASTWAIT_DEFAULT ( _MSC_STARTUP_ASTWAIT_DEFAULT << 24)
#define MSC_STARTUP_STDLY0_DEFAULT ( _MSC_STARTUP_STDLY0_DEFAULT << 0)
#define MSC_STARTUP_STDLY1_DEFAULT ( _MSC_STARTUP_STDLY1_DEFAULT << 12)
#define MSC_STARTUP_STWS_DEFAULT ( _MSC_STARTUP_STWS_DEFAULT << 28)
#define MSC_STARTUP_STWSAEN (0x1UL << 26)
#define MSC_STARTUP_STWSAEN_DEFAULT ( _MSC_STARTUP_STWSAEN_DEFAULT << 26)
#define MSC_STARTUP_STWSEN (0x1UL << 25)
#define MSC_STARTUP_STWSEN_DEFAULT ( _MSC_STARTUP_STWSEN_DEFAULT << 25)
#define MSC_STATUS_BANKSWITCHED (0x1UL << 7)
#define MSC_STATUS_BANKSWITCHED_DEFAULT ( _MSC_STATUS_BANKSWITCHED_DEFAULT << 7)
#define MSC_STATUS_BUSY (0x1UL << 0)
#define MSC_STATUS_BUSY_DEFAULT ( _MSC_STATUS_BUSY_DEFAULT << 0)
#define MSC_STATUS_ERASEABORTED (0x1UL << 5)
#define MSC_STATUS_ERASEABORTED_DEFAULT ( _MSC_STATUS_ERASEABORTED_DEFAULT << 5)
#define MSC_STATUS_INVADDR (0x1UL << 2)
#define MSC_STATUS_INVADDR_DEFAULT ( _MSC_STATUS_INVADDR_DEFAULT << 2)
#define MSC_STATUS_LOCKED (0x1UL << 1)
#define MSC_STATUS_LOCKED_DEFAULT ( _MSC_STATUS_LOCKED_DEFAULT << 1)
#define MSC_STATUS_PCRUNNING (0x1UL << 6)
#define MSC_STATUS_PCRUNNING_DEFAULT ( _MSC_STATUS_PCRUNNING_DEFAULT << 6)
#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT ( _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28)
#define MSC_STATUS_WDATAREADY (0x1UL << 3)
#define MSC_STATUS_WDATAREADY_DEFAULT ( _MSC_STATUS_WDATAREADY_DEFAULT << 3)
#define MSC_STATUS_WDATAVALID_DEFAULT ( _MSC_STATUS_WDATAVALID_DEFAULT << 24)
#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
#define MSC_STATUS_WORDTIMEOUT_DEFAULT ( _MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
#define MSC_WDATA_WDATA_DEFAULT ( _MSC_WDATA_WDATA_DEFAULT << 0)
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12)
#define MSC_WRITECMD_CLEARWDATA_DEFAULT ( _MSC_WRITECMD_CLEARWDATA_DEFAULT << 12)
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5)
#define MSC_WRITECMD_ERASEABORT_DEFAULT ( _MSC_WRITECMD_ERASEABORT_DEFAULT << 5)
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8)
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT ( _MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)
#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9)
#define MSC_WRITECMD_ERASEMAIN1_DEFAULT ( _MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9)
#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
#define MSC_WRITECMD_ERASEPAGE_DEFAULT ( _MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
#define MSC_WRITECMD_LADDRIM (0x1UL << 0)
#define MSC_WRITECMD_LADDRIM_DEFAULT ( _MSC_WRITECMD_LADDRIM_DEFAULT << 0)
#define MSC_WRITECMD_WRITEEND (0x1UL << 2)
#define MSC_WRITECMD_WRITEEND_DEFAULT ( _MSC_WRITECMD_WRITEEND_DEFAULT << 2)
#define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
#define MSC_WRITECMD_WRITEONCE_DEFAULT ( _MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
#define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
#define MSC_WRITECMD_WRITETRIG_DEFAULT ( _MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT ( _MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
#define MSC_WRITECTRL_RWWEN (0x1UL << 5)
#define MSC_WRITECTRL_RWWEN_DEFAULT ( _MSC_WRITECTRL_RWWEN_DEFAULT << 5)
#define MSC_WRITECTRL_WREN (0x1UL << 0)
#define MSC_WRITECTRL_WREN_DEFAULT ( _MSC_WRITECTRL_WREN_DEFAULT << 0)

Macro Definition Documentation

#define _MSC_AAPUNLOCKCMD_MASK   0x00000001UL

Mask for MSC_AAPUNLOCKCMD

Definition at line 738 of file efm32gg11b_msc.h .

#define _MSC_AAPUNLOCKCMD_RESETVALUE   0x00000000UL

Default value for MSC_AAPUNLOCKCMD

Definition at line 737 of file efm32gg11b_msc.h .

#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_AAPUNLOCKCMD

Definition at line 742 of file efm32gg11b_msc.h .

#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK   0x1UL

Bit mask for MSC_UNLOCKAAP

Definition at line 741 of file efm32gg11b_msc.h .

#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT   0

Shift value for MSC_UNLOCKAAP

Definition at line 740 of file efm32gg11b_msc.h .

#define _MSC_ADDRB_ADDRB_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_ADDRB

Definition at line 275 of file efm32gg11b_msc.h .

#define _MSC_ADDRB_ADDRB_MASK   0xFFFFFFFFUL

Bit mask for MSC_ADDRB

Definition at line 274 of file efm32gg11b_msc.h .

#define _MSC_ADDRB_ADDRB_SHIFT   0

Shift value for MSC_ADDRB

Definition at line 273 of file efm32gg11b_msc.h .

#define _MSC_ADDRB_MASK   0xFFFFFFFFUL

Mask for MSC_ADDRB

Definition at line 272 of file efm32gg11b_msc.h .

#define _MSC_ADDRB_RESETVALUE   0x00000000UL

Default value for MSC_ADDRB

Definition at line 271 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_BANKSWITCHLOCK

Definition at line 699 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK   0x00000000UL

Mode LOCK for MSC_BANKSWITCHLOCK

Definition at line 697 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED   0x00000001UL

Mode LOCKED for MSC_BANKSWITCHLOCK

Definition at line 700 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK   0xFFFFUL

Bit mask for MSC_BANKSWITCHLOCKKEY

Definition at line 696 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT   0

Shift value for MSC_BANKSWITCHLOCKKEY

Definition at line 695 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK   0x00007C2BUL

Mode UNLOCK for MSC_BANKSWITCHLOCK

Definition at line 701 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED   0x00000000UL

Mode UNLOCKED for MSC_BANKSWITCHLOCK

Definition at line 698 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_MASK   0x0000FFFFUL

Mask for MSC_BANKSWITCHLOCK

Definition at line 694 of file efm32gg11b_msc.h .

#define _MSC_BANKSWITCHLOCK_RESETVALUE   0x00000001UL

Default value for MSC_BANKSWITCHLOCK

Definition at line 693 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_BOOTLOADERCTRL

Definition at line 728 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK   0x1UL

Bit mask for MSC_BLRDIS

Definition at line 727 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT   0

Shift value for MSC_BLRDIS

Definition at line 726 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_BOOTLOADERCTRL

Definition at line 733 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK   0x2UL

Bit mask for MSC_BLWDIS

Definition at line 732 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT   1

Shift value for MSC_BLWDIS

Definition at line 731 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_MASK   0x00000003UL

Mask for MSC_BOOTLOADERCTRL

Definition at line 724 of file efm32gg11b_msc.h .

#define _MSC_BOOTLOADERCTRL_RESETVALUE   0x00000000UL

Default value for MSC_BOOTLOADERCTRL

Definition at line 723 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_INVCACHE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHECMD

Definition at line 616 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_INVCACHE_MASK   0x1UL

Bit mask for MSC_INVCACHE

Definition at line 615 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_INVCACHE_SHIFT   0

Shift value for MSC_INVCACHE

Definition at line 614 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_MASK   0x00000007UL

Mask for MSC_CACHECMD

Definition at line 612 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_RESETVALUE   0x00000000UL

Default value for MSC_CACHECMD

Definition at line 611 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_STARTPC_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHECMD

Definition at line 621 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_STARTPC_MASK   0x2UL

Bit mask for MSC_STARTPC

Definition at line 620 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_STARTPC_SHIFT   1

Shift value for MSC_STARTPC

Definition at line 619 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_STOPPC_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHECMD

Definition at line 626 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_STOPPC_MASK   0x4UL

Bit mask for MSC_STOPPC

Definition at line 625 of file efm32gg11b_msc.h .

#define _MSC_CACHECMD_STOPPC_SHIFT   2

Shift value for MSC_STOPPC

Definition at line 624 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED   0x00000001UL

Mode ADVANCED for MSC_CACHECONFIG0

Definition at line 751 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE   0x00000000UL

Mode BASE for MSC_CACHECONFIG0

Definition at line 750 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT   0x00000003UL

Mode DEFAULT for MSC_CACHECONFIG0

Definition at line 752 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK   0x3UL

Bit mask for MSC_CACHELPLEVEL

Definition at line 749 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY   0x00000003UL

Mode MINACTIVITY for MSC_CACHECONFIG0

Definition at line 753 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT   0

Shift value for MSC_CACHELPLEVEL

Definition at line 748 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_MASK   0x00000003UL

Mask for MSC_CACHECONFIG0

Definition at line 747 of file efm32gg11b_msc.h .

#define _MSC_CACHECONFIG0_RESETVALUE   0x00000003UL

Default value for MSC_CACHECONFIG0

Definition at line 746 of file efm32gg11b_msc.h .

#define _MSC_CACHEHITS_CACHEHITS_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHEHITS

Definition at line 634 of file efm32gg11b_msc.h .

#define _MSC_CACHEHITS_CACHEHITS_MASK   0xFFFFFUL

Bit mask for MSC_CACHEHITS

Definition at line 633 of file efm32gg11b_msc.h .

#define _MSC_CACHEHITS_CACHEHITS_SHIFT   0

Shift value for MSC_CACHEHITS

Definition at line 632 of file efm32gg11b_msc.h .

#define _MSC_CACHEHITS_MASK   0x000FFFFFUL

Mask for MSC_CACHEHITS

Definition at line 631 of file efm32gg11b_msc.h .

#define _MSC_CACHEHITS_RESETVALUE   0x00000000UL

Default value for MSC_CACHEHITS

Definition at line 630 of file efm32gg11b_msc.h .

#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CACHEMISSES

Definition at line 642 of file efm32gg11b_msc.h .

#define _MSC_CACHEMISSES_CACHEMISSES_MASK   0xFFFFFUL

Bit mask for MSC_CACHEMISSES

Definition at line 641 of file efm32gg11b_msc.h .

#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT   0

Shift value for MSC_CACHEMISSES

Definition at line 640 of file efm32gg11b_msc.h .

#define _MSC_CACHEMISSES_MASK   0x000FFFFFUL

Mask for MSC_CACHEMISSES

Definition at line 639 of file efm32gg11b_msc.h .

#define _MSC_CACHEMISSES_RESETVALUE   0x00000000UL

Default value for MSC_CACHEMISSES

Definition at line 638 of file efm32gg11b_msc.h .

#define _MSC_CMD_MASK   0x00000003UL

Mask for MSC_CMD

Definition at line 710 of file efm32gg11b_msc.h .

#define _MSC_CMD_PWRUP_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CMD

Definition at line 714 of file efm32gg11b_msc.h .

#define _MSC_CMD_PWRUP_MASK   0x1UL

Bit mask for MSC_PWRUP

Definition at line 713 of file efm32gg11b_msc.h .

#define _MSC_CMD_PWRUP_SHIFT   0

Shift value for MSC_PWRUP

Definition at line 712 of file efm32gg11b_msc.h .

#define _MSC_CMD_RESETVALUE   0x00000000UL

Default value for MSC_CMD

Definition at line 709 of file efm32gg11b_msc.h .

#define _MSC_CMD_SWITCHINGBANK_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CMD

Definition at line 719 of file efm32gg11b_msc.h .

#define _MSC_CMD_SWITCHINGBANK_MASK   0x2UL

Bit mask for MSC_SWITCHINGBANK

Definition at line 718 of file efm32gg11b_msc.h .

#define _MSC_CMD_SWITCHINGBANK_SHIFT   1

Shift value for MSC_SWITCHINGBANK

Definition at line 717 of file efm32gg11b_msc.h .

#define _MSC_CTRL_ADDRFAULTEN_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_CTRL

Definition at line 104 of file efm32gg11b_msc.h .

#define _MSC_CTRL_ADDRFAULTEN_MASK   0x1UL

Bit mask for MSC_ADDRFAULTEN

Definition at line 103 of file efm32gg11b_msc.h .

#define _MSC_CTRL_ADDRFAULTEN_SHIFT   0

Shift value for MSC_ADDRFAULTEN

Definition at line 102 of file efm32gg11b_msc.h .

#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 109 of file efm32gg11b_msc.h .

#define _MSC_CTRL_CLKDISFAULTEN_MASK   0x2UL

Bit mask for MSC_CLKDISFAULTEN

Definition at line 108 of file efm32gg11b_msc.h .

#define _MSC_CTRL_CLKDISFAULTEN_SHIFT   1

Shift value for MSC_CLKDISFAULTEN

Definition at line 107 of file efm32gg11b_msc.h .

#define _MSC_CTRL_EBIFAULTEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 134 of file efm32gg11b_msc.h .

#define _MSC_CTRL_EBIFAULTEN_MASK   0x40UL

Bit mask for MSC_EBIFAULTEN

Definition at line 133 of file efm32gg11b_msc.h .

#define _MSC_CTRL_EBIFAULTEN_SHIFT   6

Shift value for MSC_EBIFAULTEN

Definition at line 132 of file efm32gg11b_msc.h .

#define _MSC_CTRL_IFCREADCLEAR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 119 of file efm32gg11b_msc.h .

#define _MSC_CTRL_IFCREADCLEAR_MASK   0x8UL

Bit mask for MSC_IFCREADCLEAR

Definition at line 118 of file efm32gg11b_msc.h .

#define _MSC_CTRL_IFCREADCLEAR_SHIFT   3

Shift value for MSC_IFCREADCLEAR

Definition at line 117 of file efm32gg11b_msc.h .

#define _MSC_CTRL_MASK   0x0000107FUL

Mask for MSC_CTRL

Definition at line 100 of file efm32gg11b_msc.h .

#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 114 of file efm32gg11b_msc.h .

#define _MSC_CTRL_PWRUPONDEMAND_MASK   0x4UL

Bit mask for MSC_PWRUPONDEMAND

Definition at line 113 of file efm32gg11b_msc.h .

#define _MSC_CTRL_PWRUPONDEMAND_SHIFT   2

Shift value for MSC_PWRUPONDEMAND

Definition at line 112 of file efm32gg11b_msc.h .

#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT   0x00000001UL

Mode DEFAULT for MSC_CTRL

Definition at line 129 of file efm32gg11b_msc.h .

#define _MSC_CTRL_RAMECCERRFAULTEN_MASK   0x20UL

Bit mask for MSC_RAMECCERRFAULTEN

Definition at line 128 of file efm32gg11b_msc.h .

#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT   5

Shift value for MSC_RAMECCERRFAULTEN

Definition at line 127 of file efm32gg11b_msc.h .

#define _MSC_CTRL_RESETVALUE   0x00000021UL

Default value for MSC_CTRL

Definition at line 99 of file efm32gg11b_msc.h .

#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 124 of file efm32gg11b_msc.h .

#define _MSC_CTRL_TIMEOUTFAULTEN_MASK   0x10UL

Bit mask for MSC_TIMEOUTFAULTEN

Definition at line 123 of file efm32gg11b_msc.h .

#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT   4

Shift value for MSC_TIMEOUTFAULTEN

Definition at line 122 of file efm32gg11b_msc.h .

#define _MSC_CTRL_WAITMODE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_CTRL

Definition at line 139 of file efm32gg11b_msc.h .

#define _MSC_CTRL_WAITMODE_MASK   0x1000UL

Bit mask for MSC_WAITMODE

Definition at line 138 of file efm32gg11b_msc.h .

#define _MSC_CTRL_WAITMODE_SHIFT   12

Shift value for MSC_WAITMODE

Definition at line 137 of file efm32gg11b_msc.h .

#define _MSC_CTRL_WAITMODE_WS0   0x00000000UL

Mode WS0 for MSC_CTRL

Definition at line 140 of file efm32gg11b_msc.h .

#define _MSC_CTRL_WAITMODE_WS1   0x00000001UL

Mode WS1 for MSC_CTRL

Definition at line 141 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_MASK   0x0000000FUL

Mask for MSC_ECCCTRL

Definition at line 810 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_ECCCTRL

Definition at line 829 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK   0x8UL

Bit mask for MSC_RAM1ECCCHKEN

Definition at line 828 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT   3

Shift value for MSC_RAM1ECCCHKEN

Definition at line 827 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_ECCCTRL

Definition at line 824 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK   0x4UL

Bit mask for MSC_RAM1ECCEWEN

Definition at line 823 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT   2

Shift value for MSC_RAM1ECCEWEN

Definition at line 822 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_ECCCTRL

Definition at line 819 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAMECCCHKEN_MASK   0x2UL

Bit mask for MSC_RAMECCCHKEN

Definition at line 818 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT   1

Shift value for MSC_RAMECCCHKEN

Definition at line 817 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_ECCCTRL

Definition at line 814 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAMECCEWEN_MASK   0x1UL

Bit mask for MSC_RAMECCEWEN

Definition at line 813 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT   0

Shift value for MSC_RAMECCEWEN

Definition at line 812 of file efm32gg11b_msc.h .

#define _MSC_ECCCTRL_RESETVALUE   0x00000000UL

Default value for MSC_ECCCTRL

Definition at line 809 of file efm32gg11b_msc.h .

#define _MSC_IEN_CHOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 546 of file efm32gg11b_msc.h .

#define _MSC_IEN_CHOF_MASK   0x4UL

Bit mask for MSC_CHOF

Definition at line 545 of file efm32gg11b_msc.h .

#define _MSC_IEN_CHOF_SHIFT   2

Shift value for MSC_CHOF

Definition at line 544 of file efm32gg11b_msc.h .

#define _MSC_IEN_CMOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 551 of file efm32gg11b_msc.h .

#define _MSC_IEN_CMOF_MASK   0x8UL

Bit mask for MSC_CMOF

Definition at line 550 of file efm32gg11b_msc.h .

#define _MSC_IEN_CMOF_SHIFT   3

Shift value for MSC_CMOF

Definition at line 549 of file efm32gg11b_msc.h .

#define _MSC_IEN_ERASE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 536 of file efm32gg11b_msc.h .

#define _MSC_IEN_ERASE_MASK   0x1UL

Bit mask for MSC_ERASE

Definition at line 535 of file efm32gg11b_msc.h .

#define _MSC_IEN_ERASE_SHIFT   0

Shift value for MSC_ERASE

Definition at line 534 of file efm32gg11b_msc.h .

#define _MSC_IEN_ICACHERR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 561 of file efm32gg11b_msc.h .

#define _MSC_IEN_ICACHERR_MASK   0x20UL

Bit mask for MSC_ICACHERR

Definition at line 560 of file efm32gg11b_msc.h .

#define _MSC_IEN_ICACHERR_SHIFT   5

Shift value for MSC_ICACHERR

Definition at line 559 of file efm32gg11b_msc.h .

#define _MSC_IEN_LVEWRITE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 571 of file efm32gg11b_msc.h .

#define _MSC_IEN_LVEWRITE_MASK   0x100UL

Bit mask for MSC_LVEWRITE

Definition at line 570 of file efm32gg11b_msc.h .

#define _MSC_IEN_LVEWRITE_SHIFT   8

Shift value for MSC_LVEWRITE

Definition at line 569 of file efm32gg11b_msc.h .

#define _MSC_IEN_MASK   0x000F017FUL

Mask for MSC_IEN

Definition at line 532 of file efm32gg11b_msc.h .

#define _MSC_IEN_PWRUPF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 556 of file efm32gg11b_msc.h .

#define _MSC_IEN_PWRUPF_MASK   0x10UL

Bit mask for MSC_PWRUPF

Definition at line 555 of file efm32gg11b_msc.h .

#define _MSC_IEN_PWRUPF_SHIFT   4

Shift value for MSC_PWRUPF

Definition at line 554 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAM1ERR1B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 586 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAM1ERR1B_MASK   0x40000UL

Bit mask for MSC_RAM1ERR1B

Definition at line 585 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAM1ERR1B_SHIFT   18

Shift value for MSC_RAM1ERR1B

Definition at line 584 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAM1ERR2B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 591 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAM1ERR2B_MASK   0x80000UL

Bit mask for MSC_RAM1ERR2B

Definition at line 590 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAM1ERR2B_SHIFT   19

Shift value for MSC_RAM1ERR2B

Definition at line 589 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAMERR1B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 576 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAMERR1B_MASK   0x10000UL

Bit mask for MSC_RAMERR1B

Definition at line 575 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAMERR1B_SHIFT   16

Shift value for MSC_RAMERR1B

Definition at line 574 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAMERR2B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 581 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAMERR2B_MASK   0x20000UL

Bit mask for MSC_RAMERR2B

Definition at line 580 of file efm32gg11b_msc.h .

#define _MSC_IEN_RAMERR2B_SHIFT   17

Shift value for MSC_RAMERR2B

Definition at line 579 of file efm32gg11b_msc.h .

#define _MSC_IEN_RESETVALUE   0x00000000UL

Default value for MSC_IEN

Definition at line 531 of file efm32gg11b_msc.h .

#define _MSC_IEN_WDATAOV_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 566 of file efm32gg11b_msc.h .

#define _MSC_IEN_WDATAOV_MASK   0x40UL

Bit mask for MSC_WDATAOV

Definition at line 565 of file efm32gg11b_msc.h .

#define _MSC_IEN_WDATAOV_SHIFT   6

Shift value for MSC_WDATAOV

Definition at line 564 of file efm32gg11b_msc.h .

#define _MSC_IEN_WRITE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IEN

Definition at line 541 of file efm32gg11b_msc.h .

#define _MSC_IEN_WRITE_MASK   0x2UL

Bit mask for MSC_WRITE

Definition at line 540 of file efm32gg11b_msc.h .

#define _MSC_IEN_WRITE_SHIFT   1

Shift value for MSC_WRITE

Definition at line 539 of file efm32gg11b_msc.h .

#define _MSC_IF_CHOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 354 of file efm32gg11b_msc.h .

#define _MSC_IF_CHOF_MASK   0x4UL

Bit mask for MSC_CHOF

Definition at line 353 of file efm32gg11b_msc.h .

#define _MSC_IF_CHOF_SHIFT   2

Shift value for MSC_CHOF

Definition at line 352 of file efm32gg11b_msc.h .

#define _MSC_IF_CMOF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 359 of file efm32gg11b_msc.h .

#define _MSC_IF_CMOF_MASK   0x8UL

Bit mask for MSC_CMOF

Definition at line 358 of file efm32gg11b_msc.h .

#define _MSC_IF_CMOF_SHIFT   3

Shift value for MSC_CMOF

Definition at line 357 of file efm32gg11b_msc.h .

#define _MSC_IF_ERASE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 344 of file efm32gg11b_msc.h .

#define _MSC_IF_ERASE_MASK   0x1UL

Bit mask for MSC_ERASE

Definition at line 343 of file efm32gg11b_msc.h .

#define _MSC_IF_ERASE_SHIFT   0

Shift value for MSC_ERASE

Definition at line 342 of file efm32gg11b_msc.h .

#define _MSC_IF_ICACHERR_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 369 of file efm32gg11b_msc.h .

#define _MSC_IF_ICACHERR_MASK   0x20UL

Bit mask for MSC_ICACHERR

Definition at line 368 of file efm32gg11b_msc.h .

#define _MSC_IF_ICACHERR_SHIFT   5

Shift value for MSC_ICACHERR

Definition at line 367 of file efm32gg11b_msc.h .

#define _MSC_IF_LVEWRITE_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 379 of file efm32gg11b_msc.h .

#define _MSC_IF_LVEWRITE_MASK   0x100UL

Bit mask for MSC_LVEWRITE

Definition at line 378 of file efm32gg11b_msc.h .

#define _MSC_IF_LVEWRITE_SHIFT   8

Shift value for MSC_LVEWRITE

Definition at line 377 of file efm32gg11b_msc.h .

#define _MSC_IF_MASK   0x000F017FUL

Mask for MSC_IF

Definition at line 340 of file efm32gg11b_msc.h .

#define _MSC_IF_PWRUPF_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 364 of file efm32gg11b_msc.h .

#define _MSC_IF_PWRUPF_MASK   0x10UL

Bit mask for MSC_PWRUPF

Definition at line 363 of file efm32gg11b_msc.h .

#define _MSC_IF_PWRUPF_SHIFT   4

Shift value for MSC_PWRUPF

Definition at line 362 of file efm32gg11b_msc.h .

#define _MSC_IF_RAM1ERR1B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 394 of file efm32gg11b_msc.h .

#define _MSC_IF_RAM1ERR1B_MASK   0x40000UL

Bit mask for MSC_RAM1ERR1B

Definition at line 393 of file efm32gg11b_msc.h .

#define _MSC_IF_RAM1ERR1B_SHIFT   18

Shift value for MSC_RAM1ERR1B

Definition at line 392 of file efm32gg11b_msc.h .

#define _MSC_IF_RAM1ERR2B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 399 of file efm32gg11b_msc.h .

#define _MSC_IF_RAM1ERR2B_MASK   0x80000UL

Bit mask for MSC_RAM1ERR2B

Definition at line 398 of file efm32gg11b_msc.h .

#define _MSC_IF_RAM1ERR2B_SHIFT   19

Shift value for MSC_RAM1ERR2B

Definition at line 397 of file efm32gg11b_msc.h .

#define _MSC_IF_RAMERR1B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 384 of file efm32gg11b_msc.h .

#define _MSC_IF_RAMERR1B_MASK   0x10000UL

Bit mask for MSC_RAMERR1B

Definition at line 383 of file efm32gg11b_msc.h .

#define _MSC_IF_RAMERR1B_SHIFT   16

Shift value for MSC_RAMERR1B

Definition at line 382 of file efm32gg11b_msc.h .

#define _MSC_IF_RAMERR2B_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 389 of file efm32gg11b_msc.h .

#define _MSC_IF_RAMERR2B_MASK   0x20000UL

Bit mask for MSC_RAMERR2B

Definition at line 388 of file efm32gg11b_msc.h .

#define _MSC_IF_RAMERR2B_SHIFT   17

Shift value for MSC_RAMERR2B

Definition at line 387 of file efm32gg11b_msc.h .

#define _MSC_IF_RESETVALUE   0x00000000UL

Default value for MSC_IF

Definition at line 339 of file efm32gg11b_msc.h .

#define _MSC_IF_WDATAOV_DEFAULT   0x00000000UL

Mode DEFAULT for MSC_IF

Definition at line 374 of file efm32gg11b_msc.h .

#define _MSC_IF_WDATAOV_MASK   0x40UL

Bit mask for MSC_WDATAOV

Definition at line 373 of file efm32gg11b_msc.h .