Macros
#define	_EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL

#define	_EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL

#define	_EMU_BOD3SENSE_AVDDBODEN_SHIFT 0

#define	_EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT 0x00000000UL

#define	_EMU_BOD3SENSE_IOVDD0BODEN_MASK 0x2UL

#define	_EMU_BOD3SENSE_IOVDD0BODEN_SHIFT 1

#define	_EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT 0x00000000UL

#define	_EMU_BOD3SENSE_IOVDD1BODEN_MASK 0x4UL

#define	_EMU_BOD3SENSE_IOVDD1BODEN_SHIFT 2

#define	_EMU_BOD3SENSE_MASK 0x00000077UL

#define	_EMU_BOD3SENSE_RESETVALUE 0x00000000UL

#define	_EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL

#define	_EMU_CMD_EM4UNLATCH_MASK 0x2UL

#define	_EMU_CMD_EM4UNLATCH_SHIFT 1

#define	_EMU_CMD_MASK 0x00020E02UL

#define	_EMU_CMD_RESETVALUE 0x00000000UL

#define	_EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL

#define	_EMU_CMD_RSTCAUSECLR_MASK 0x20000UL

#define	_EMU_CMD_RSTCAUSECLR_SHIFT 17

#define	_EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM2DBGEN_MASK 0x1UL

#define	_EMU_CTRL_EM2DBGEN_SHIFT 0

#define	_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL

#define	_EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL

#define	_EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16

#define	_EMU_CTRL_MASK 0x0001F303UL

#define	_EMU_CTRL_RESETVALUE 0x0000A200UL

#define	_EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL

#define	_EMU_DECBOD_DECBODEN_MASK 0x1UL

#define	_EMU_DECBOD_DECBODEN_SHIFT 0

#define	_EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL

#define	_EMU_DECBOD_DECBODMASK_MASK 0x2UL

#define	_EMU_DECBOD_DECBODMASK_SHIFT 1

#define	_EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL

#define	_EMU_DECBOD_DECOVMBODEN_MASK 0x10UL

#define	_EMU_DECBOD_DECOVMBODEN_SHIFT 4

#define	_EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL

#define	_EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL

#define	_EMU_DECBOD_DECOVMBODMASK_SHIFT 5

#define	_EMU_DECBOD_MASK 0x00000033UL

#define	_EMU_DECBOD_RESETVALUE 0x00000022UL

#define	_EMU_DGIEN_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_DGIEN_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_DGIEN_EM23WAKEUP_SHIFT 24

#define	_EMU_DGIEN_MASK 0xE1000000UL

#define	_EMU_DGIEN_RESETVALUE 0x00000000UL

#define	_EMU_DGIEN_TEMP_DEFAULT 0x00000000UL

#define	_EMU_DGIEN_TEMP_MASK 0x20000000UL

#define	_EMU_DGIEN_TEMP_SHIFT 29

#define	_EMU_DGIEN_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_DGIEN_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_DGIEN_TEMPHIGH_SHIFT 31

#define	_EMU_DGIEN_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_DGIEN_TEMPLOW_MASK 0x40000000UL

#define	_EMU_DGIEN_TEMPLOW_SHIFT 30

#define	_EMU_DGIF_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_DGIF_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_DGIF_EM23WAKEUP_SHIFT 24

#define	_EMU_DGIF_MASK 0xE1000000UL

#define	_EMU_DGIF_RESETVALUE 0x00000000UL

#define	_EMU_DGIF_TEMP_DEFAULT 0x00000000UL

#define	_EMU_DGIF_TEMP_MASK 0x20000000UL

#define	_EMU_DGIF_TEMP_SHIFT 29

#define	_EMU_DGIF_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_DGIF_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_DGIF_TEMPHIGH_SHIFT 31

#define	_EMU_DGIF_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_DGIF_TEMPLOW_MASK 0x40000000UL

#define	_EMU_DGIF_TEMPLOW_SHIFT 30

#define	_EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL

#define	_EMU_EM4CTRL_EM4ENTRY_SHIFT 0

#define	_EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL

#define	_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL

#define	_EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL

#define	_EMU_EM4CTRL_EM4IORETMODE_SHIFT 4

#define	_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL

#define	_EMU_EM4CTRL_MASK 0x00000033UL

#define	_EMU_EM4CTRL_RESETVALUE 0x00000000UL

#define	_EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL

#define	_EMU_IEN_AVDDBOD_MASK 0x10000UL

#define	_EMU_IEN_AVDDBOD_SHIFT 16

#define	_EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IEN_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IEN_EM23WAKEUP_SHIFT 24

#define	_EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL

#define	_EMU_IEN_IOVDD0BOD_MASK 0x20000UL

#define	_EMU_IEN_IOVDD0BOD_SHIFT 17

#define	_EMU_IEN_MASK 0xE3070000UL

#define	_EMU_IEN_RESETVALUE 0x00000000UL

#define	_EMU_IEN_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMP_MASK 0x20000000UL

#define	_EMU_IEN_TEMP_SHIFT 29

#define	_EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IEN_TEMPHIGH_SHIFT 31

#define	_EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IEN_TEMPLOW_SHIFT 30

#define	_EMU_IF_AVDDBOD_DEFAULT 0x00000000UL

#define	_EMU_IF_AVDDBOD_MASK 0x10000UL

#define	_EMU_IF_AVDDBOD_SHIFT 16

#define	_EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IF_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IF_EM23WAKEUP_SHIFT 24

#define	_EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL

#define	_EMU_IF_IOVDD0BOD_MASK 0x20000UL

#define	_EMU_IF_IOVDD0BOD_SHIFT 17

#define	_EMU_IF_MASK 0xE3070000UL

#define	_EMU_IF_RESETVALUE 0x00000000UL

#define	_EMU_IF_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMP_MASK 0x20000000UL

#define	_EMU_IF_TEMP_SHIFT 29

#define	_EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IF_TEMPHIGH_SHIFT 31

#define	_EMU_IF_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IF_TEMPLOW_SHIFT 30

#define	_EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL

#define	_EMU_LOCK_LOCKKEY_MASK 0xFFFFUL

#define	_EMU_LOCK_LOCKKEY_SHIFT 0

#define	_EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL

#define	_EMU_LOCK_MASK 0x0000FFFFUL

#define	_EMU_LOCK_RESETVALUE 0x0000ADE8UL

#define	_EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL

#define	_EMU_RSTCAUSE_AVDDBOD_SHIFT 10

#define	_EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_DECBOD_MASK 0x200UL

#define	_EMU_RSTCAUSE_DECBOD_SHIFT 9

#define	_EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL

#define	_EMU_RSTCAUSE_DVDDBOD_SHIFT 7

#define	_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL

#define	_EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8

#define	_EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_EM4_MASK 0x4UL

#define	_EMU_RSTCAUSE_EM4_SHIFT 2

#define	_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL

#define	_EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11

#define	_EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_LOCKUP_MASK 0x20UL

#define	_EMU_RSTCAUSE_LOCKUP_SHIFT 5

#define	_EMU_RSTCAUSE_MASK 0x0000FFFFUL

#define	_EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_PIN_MASK 0x2UL

#define	_EMU_RSTCAUSE_PIN_SHIFT 1

#define	_EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_POR_MASK 0x1UL

#define	_EMU_RSTCAUSE_POR_SHIFT 0

#define	_EMU_RSTCAUSE_RESETVALUE 0x00000000UL

#define	_EMU_RSTCAUSE_SELOCKUP_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_SELOCKUP_MASK 0x8000UL

#define	_EMU_RSTCAUSE_SELOCKUP_SHIFT 15

#define	_EMU_RSTCAUSE_SESYSREQ_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_SESYSREQ_MASK 0x4000UL

#define	_EMU_RSTCAUSE_SESYSREQ_SHIFT 14

#define	_EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL

#define	_EMU_RSTCAUSE_SETAMPER_SHIFT 13

#define	_EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_SYSREQ_MASK 0x40UL

#define	_EMU_RSTCAUSE_SYSREQ_SHIFT 6

#define	_EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_WDOG0_MASK 0x8UL

#define	_EMU_RSTCAUSE_WDOG0_SHIFT 3

#define	_EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL

#define	_EMU_RSTCAUSE_WDOG1_MASK 0x10UL

#define	_EMU_RSTCAUSE_WDOG1_SHIFT 4

#define	_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL

#define	_EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL

#define	_EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6

#define	_EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL

#define	_EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL

#define	_EMU_RSTCTRL_DECBODRMODE_SHIFT 10

#define	_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL

#define	_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL

#define	_EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7

#define	_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL

#define	_EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL

#define	_EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3

#define	_EMU_RSTCTRL_MASK 0x0000C5CFUL

#define	_EMU_RSTCTRL_RESETVALUE 0x00004407UL

#define	_EMU_RSTCTRL_SELOCKUPRMODE_DEFAULT 0x00000000UL

#define	_EMU_RSTCTRL_SELOCKUPRMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_SELOCKUPRMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_SELOCKUPRMODE_MASK 0x8000UL

#define	_EMU_RSTCTRL_SELOCKUPRMODE_SHIFT 15

#define	_EMU_RSTCTRL_SESYSRMODE_DEFAULT 0x00000001UL

#define	_EMU_RSTCTRL_SESYSRMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_SESYSRMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_SESYSRMODE_MASK 0x4000UL

#define	_EMU_RSTCTRL_SESYSRMODE_SHIFT 14

#define	_EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL

#define	_EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_SYSRMODE_MASK 0x4UL

#define	_EMU_RSTCTRL_SYSRMODE_SHIFT 2

#define	_EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL

#define	_EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL

#define	_EMU_RSTCTRL_WDOG0RMODE_SHIFT 0

#define	_EMU_RSTCTRL_WDOG1RMODE_DEFAULT 0x00000001UL

#define	_EMU_RSTCTRL_WDOG1RMODE_DISABLED 0x00000000UL

#define	_EMU_RSTCTRL_WDOG1RMODE_ENABLED 0x00000001UL

#define	_EMU_RSTCTRL_WDOG1RMODE_MASK 0x2UL

#define	_EMU_RSTCTRL_WDOG1RMODE_SHIFT 1

#define	_EMU_SEIEN_MASK 0xE0000000UL

#define	_EMU_SEIEN_RESETVALUE 0x00000000UL

#define	_EMU_SEIEN_TEMP_DEFAULT 0x00000000UL

#define	_EMU_SEIEN_TEMP_MASK 0x20000000UL

#define	_EMU_SEIEN_TEMP_SHIFT 29

#define	_EMU_SEIEN_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_SEIEN_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_SEIEN_TEMPHIGH_SHIFT 31

#define	_EMU_SEIEN_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_SEIEN_TEMPLOW_MASK 0x40000000UL

#define	_EMU_SEIEN_TEMPLOW_SHIFT 30

#define	_EMU_SEIF_MASK 0xE0000000UL

#define	_EMU_SEIF_RESETVALUE 0x00000000UL

#define	_EMU_SEIF_TEMP_DEFAULT 0x00000000UL

#define	_EMU_SEIF_TEMP_MASK 0x20000000UL

#define	_EMU_SEIF_TEMP_SHIFT 29

#define	_EMU_SEIF_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_SEIF_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_SEIF_TEMPHIGH_SHIFT 31

#define	_EMU_SEIF_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_SEIF_TEMPLOW_MASK 0x40000000UL

#define	_EMU_SEIF_TEMPLOW_SHIFT 30

#define	_EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL

#define	_EMU_STATUS_EM2ENTERED_MASK 0x4000UL

#define	_EMU_STATUS_EM2ENTERED_SHIFT 14

#define	_EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL

#define	_EMU_STATUS_EM4IORET_MASK 0x1000UL

#define	_EMU_STATUS_EM4IORET_SHIFT 12

#define	_EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL

#define	_EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL

#define	_EMU_STATUS_FIRSTTEMPDONE_SHIFT 1

#define	_EMU_STATUS_LOCK_DEFAULT 0x00000000UL

#define	_EMU_STATUS_LOCK_LOCKED 0x00000001UL

#define	_EMU_STATUS_LOCK_MASK 0x1UL

#define	_EMU_STATUS_LOCK_SHIFT 0

#define	_EMU_STATUS_LOCK_UNLOCKED 0x00000000UL

#define	_EMU_STATUS_MASK 0x000054F7UL

#define	_EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL

#define	_EMU_STATUS_RACACTIVE_MASK 0x400UL

#define	_EMU_STATUS_RACACTIVE_SHIFT 10

#define	_EMU_STATUS_RESETVALUE 0x00000080UL

#define	_EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL

#define	_EMU_STATUS_TEMPACTIVE_MASK 0x4UL

#define	_EMU_STATUS_TEMPACTIVE_SHIFT 2

#define	_EMU_TEMP_MASK 0x000007FFUL

#define	_EMU_TEMP_RESETVALUE 0x00000000UL

#define	_EMU_TEMP_TEMP_DEFAULT 0x00000000UL

#define	_EMU_TEMP_TEMP_MASK 0x7FCUL

#define	_EMU_TEMP_TEMP_SHIFT 2

#define	_EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL

#define	_EMU_TEMP_TEMPLSB_MASK 0x3UL

#define	_EMU_TEMP_TEMPLSB_SHIFT 0

#define	_EMU_TEMPLIMITS_MASK 0x01FF01FFUL

#define	_EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL

#define	_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL

#define	_EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL

#define	_EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16

#define	_EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL

#define	_EMU_TEMPLIMITS_TEMPLOW_SHIFT 0

#define	EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0)

#define	EMU_BOD3SENSE_AVDDBODEN_DEFAULT ( _EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0)

#define	EMU_BOD3SENSE_IOVDD0BODEN (0x1UL << 1)

#define	EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT ( _EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT << 1)

#define	EMU_BOD3SENSE_IOVDD1BODEN (0x1UL << 2)

#define	EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT ( _EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT << 2)

#define	EMU_CMD_EM4UNLATCH (0x1UL << 1)

#define	EMU_CMD_EM4UNLATCH_DEFAULT ( _EMU_CMD_EM4UNLATCH_DEFAULT << 1)

#define	EMU_CMD_RSTCAUSECLR (0x1UL << 17)

#define	EMU_CMD_RSTCAUSECLR_DEFAULT ( _EMU_CMD_RSTCAUSECLR_DEFAULT << 17)

#define	EMU_CTRL_EM2DBGEN (0x1UL << 0)

#define	EMU_CTRL_EM2DBGEN_DEFAULT ( _EMU_CTRL_EM2DBGEN_DEFAULT << 0)

#define	EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16)

#define	EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT ( _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16)

#define	EMU_DECBOD_DECBODEN (0x1UL << 0)

#define	EMU_DECBOD_DECBODEN_DEFAULT ( _EMU_DECBOD_DECBODEN_DEFAULT << 0)

#define	EMU_DECBOD_DECBODMASK (0x1UL << 1)

#define	EMU_DECBOD_DECBODMASK_DEFAULT ( _EMU_DECBOD_DECBODMASK_DEFAULT << 1)

#define	EMU_DECBOD_DECOVMBODEN (0x1UL << 4)

#define	EMU_DECBOD_DECOVMBODEN_DEFAULT ( _EMU_DECBOD_DECOVMBODEN_DEFAULT << 4)

#define	EMU_DECBOD_DECOVMBODMASK (0x1UL << 5)

#define	EMU_DECBOD_DECOVMBODMASK_DEFAULT ( _EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5)

#define	EMU_DGIEN_EM23WAKEUP (0x1UL << 24)

#define	EMU_DGIEN_EM23WAKEUP_DEFAULT ( _EMU_DGIEN_EM23WAKEUP_DEFAULT << 24)

#define	EMU_DGIEN_TEMP (0x1UL << 29)

#define	EMU_DGIEN_TEMP_DEFAULT ( _EMU_DGIEN_TEMP_DEFAULT << 29)

#define	EMU_DGIEN_TEMPHIGH (0x1UL << 31)

#define	EMU_DGIEN_TEMPHIGH_DEFAULT ( _EMU_DGIEN_TEMPHIGH_DEFAULT << 31)

#define	EMU_DGIEN_TEMPLOW (0x1UL << 30)

#define	EMU_DGIEN_TEMPLOW_DEFAULT ( _EMU_DGIEN_TEMPLOW_DEFAULT << 30)

#define	EMU_DGIF_EM23WAKEUP (0x1UL << 24)

#define	EMU_DGIF_EM23WAKEUP_DEFAULT ( _EMU_DGIF_EM23WAKEUP_DEFAULT << 24)

#define	EMU_DGIF_TEMP (0x1UL << 29)

#define	EMU_DGIF_TEMP_DEFAULT ( _EMU_DGIF_TEMP_DEFAULT << 29)

#define	EMU_DGIF_TEMPHIGH (0x1UL << 31)

#define	EMU_DGIF_TEMPHIGH_DEFAULT ( _EMU_DGIF_TEMPHIGH_DEFAULT << 31)

#define	EMU_DGIF_TEMPLOW (0x1UL << 30)

#define	EMU_DGIF_TEMPLOW_DEFAULT ( _EMU_DGIF_TEMPLOW_DEFAULT << 30)

#define	EMU_EM4CTRL_EM4ENTRY_DEFAULT ( _EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0)

#define	EMU_EM4CTRL_EM4IORETMODE_DEFAULT ( _EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_DISABLE ( _EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_EM4EXIT ( _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH ( _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)

#define	EMU_IEN_AVDDBOD (0x1UL << 16)

#define	EMU_IEN_AVDDBOD_DEFAULT ( _EMU_IEN_AVDDBOD_DEFAULT << 16)

#define	EMU_IEN_EM23WAKEUP (0x1UL << 24)

#define	EMU_IEN_EM23WAKEUP_DEFAULT ( _EMU_IEN_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IEN_IOVDD0BOD (0x1UL << 17)

#define	EMU_IEN_IOVDD0BOD_DEFAULT ( _EMU_IEN_IOVDD0BOD_DEFAULT << 17)

#define	EMU_IEN_TEMP (0x1UL << 29)

#define	EMU_IEN_TEMP_DEFAULT ( _EMU_IEN_TEMP_DEFAULT << 29)

#define	EMU_IEN_TEMPHIGH (0x1UL << 31)

#define	EMU_IEN_TEMPHIGH_DEFAULT ( _EMU_IEN_TEMPHIGH_DEFAULT << 31)

#define	EMU_IEN_TEMPLOW (0x1UL << 30)

#define	EMU_IEN_TEMPLOW_DEFAULT ( _EMU_IEN_TEMPLOW_DEFAULT << 30)

#define	EMU_IF_AVDDBOD (0x1UL << 16)

#define	EMU_IF_AVDDBOD_DEFAULT ( _EMU_IF_AVDDBOD_DEFAULT << 16)

#define	EMU_IF_EM23WAKEUP (0x1UL << 24)

#define	EMU_IF_EM23WAKEUP_DEFAULT ( _EMU_IF_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IF_IOVDD0BOD (0x1UL << 17)

#define	EMU_IF_IOVDD0BOD_DEFAULT ( _EMU_IF_IOVDD0BOD_DEFAULT << 17)

#define	EMU_IF_TEMP (0x1UL << 29)

#define	EMU_IF_TEMP_DEFAULT ( _EMU_IF_TEMP_DEFAULT << 29)

#define	EMU_IF_TEMPHIGH (0x1UL << 31)

#define	EMU_IF_TEMPHIGH_DEFAULT ( _EMU_IF_TEMPHIGH_DEFAULT << 31)

#define	EMU_IF_TEMPLOW (0x1UL << 30)

#define	EMU_IF_TEMPLOW_DEFAULT ( _EMU_IF_TEMPLOW_DEFAULT << 30)

#define	EMU_LOCK_LOCKKEY_DEFAULT ( _EMU_LOCK_LOCKKEY_DEFAULT << 0)

#define	EMU_LOCK_LOCKKEY_UNLOCK ( _EMU_LOCK_LOCKKEY_UNLOCK << 0)

#define	EMU_RSTCAUSE_AVDDBOD (0x1UL << 10)

#define	EMU_RSTCAUSE_AVDDBOD_DEFAULT ( _EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10)

#define	EMU_RSTCAUSE_DECBOD (0x1UL << 9)

#define	EMU_RSTCAUSE_DECBOD_DEFAULT ( _EMU_RSTCAUSE_DECBOD_DEFAULT << 9)

#define	EMU_RSTCAUSE_DVDDBOD (0x1UL << 7)

#define	EMU_RSTCAUSE_DVDDBOD_DEFAULT ( _EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7)

#define	EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8)

#define	EMU_RSTCAUSE_DVDDLEBOD_DEFAULT ( _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8)

#define	EMU_RSTCAUSE_EM4 (0x1UL << 2)

#define	EMU_RSTCAUSE_EM4_DEFAULT ( _EMU_RSTCAUSE_EM4_DEFAULT << 2)

#define	EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11)

#define	EMU_RSTCAUSE_IOVDD0BOD_DEFAULT ( _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11)

#define	EMU_RSTCAUSE_LOCKUP (0x1UL << 5)

#define	EMU_RSTCAUSE_LOCKUP_DEFAULT ( _EMU_RSTCAUSE_LOCKUP_DEFAULT << 5)

#define	EMU_RSTCAUSE_PIN (0x1UL << 1)

#define	EMU_RSTCAUSE_PIN_DEFAULT ( _EMU_RSTCAUSE_PIN_DEFAULT << 1)

#define	EMU_RSTCAUSE_POR (0x1UL << 0)

#define	EMU_RSTCAUSE_POR_DEFAULT ( _EMU_RSTCAUSE_POR_DEFAULT << 0)

#define	EMU_RSTCAUSE_SELOCKUP (0x1UL << 15)

#define	EMU_RSTCAUSE_SELOCKUP_DEFAULT ( _EMU_RSTCAUSE_SELOCKUP_DEFAULT << 15)

#define	EMU_RSTCAUSE_SESYSREQ (0x1UL << 14)

#define	EMU_RSTCAUSE_SESYSREQ_DEFAULT ( _EMU_RSTCAUSE_SESYSREQ_DEFAULT << 14)

#define	EMU_RSTCAUSE_SETAMPER (0x1UL << 13)

#define	EMU_RSTCAUSE_SETAMPER_DEFAULT ( _EMU_RSTCAUSE_SETAMPER_DEFAULT << 13)

#define	EMU_RSTCAUSE_SYSREQ (0x1UL << 6)

#define	EMU_RSTCAUSE_SYSREQ_DEFAULT ( _EMU_RSTCAUSE_SYSREQ_DEFAULT << 6)

#define	EMU_RSTCAUSE_WDOG0 (0x1UL << 3)

#define	EMU_RSTCAUSE_WDOG0_DEFAULT ( _EMU_RSTCAUSE_WDOG0_DEFAULT << 3)

#define	EMU_RSTCAUSE_WDOG1 (0x1UL << 4)

#define	EMU_RSTCAUSE_WDOG1_DEFAULT ( _EMU_RSTCAUSE_WDOG1_DEFAULT << 4)

#define	EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6)

#define	EMU_RSTCTRL_AVDDBODRMODE_DEFAULT ( _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6)

#define	EMU_RSTCTRL_AVDDBODRMODE_DISABLED ( _EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6)

#define	EMU_RSTCTRL_AVDDBODRMODE_ENABLED ( _EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6)

#define	EMU_RSTCTRL_DECBODRMODE (0x1UL << 10)

#define	EMU_RSTCTRL_DECBODRMODE_DEFAULT ( _EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10)

#define	EMU_RSTCTRL_DECBODRMODE_DISABLED ( _EMU_RSTCTRL_DECBODRMODE_DISABLED << 10)

#define	EMU_RSTCTRL_DECBODRMODE_ENABLED ( _EMU_RSTCTRL_DECBODRMODE_ENABLED << 10)

#define	EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7)

#define	EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT ( _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7)

#define	EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED ( _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7)

#define	EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED ( _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7)

#define	EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3)

#define	EMU_RSTCTRL_LOCKUPRMODE_DEFAULT ( _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3)

#define	EMU_RSTCTRL_LOCKUPRMODE_DISABLED ( _EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3)

#define	EMU_RSTCTRL_LOCKUPRMODE_ENABLED ( _EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3)

#define	EMU_RSTCTRL_SELOCKUPRMODE (0x1UL << 15)

#define	EMU_RSTCTRL_SELOCKUPRMODE_DEFAULT ( _EMU_RSTCTRL_SELOCKUPRMODE_DEFAULT << 15)

#define	EMU_RSTCTRL_SELOCKUPRMODE_DISABLED ( _EMU_RSTCTRL_SELOCKUPRMODE_DISABLED << 15)

#define	EMU_RSTCTRL_SELOCKUPRMODE_ENABLED ( _EMU_RSTCTRL_SELOCKUPRMODE_ENABLED << 15)

#define	EMU_RSTCTRL_SESYSRMODE (0x1UL << 14)

#define	EMU_RSTCTRL_SESYSRMODE_DEFAULT ( _EMU_RSTCTRL_SESYSRMODE_DEFAULT << 14)

#define	EMU_RSTCTRL_SESYSRMODE_DISABLED ( _EMU_RSTCTRL_SESYSRMODE_DISABLED << 14)

#define	EMU_RSTCTRL_SESYSRMODE_ENABLED ( _EMU_RSTCTRL_SESYSRMODE_ENABLED << 14)

#define	EMU_RSTCTRL_SYSRMODE (0x1UL << 2)

#define	EMU_RSTCTRL_SYSRMODE_DEFAULT ( _EMU_RSTCTRL_SYSRMODE_DEFAULT << 2)

#define	EMU_RSTCTRL_SYSRMODE_DISABLED ( _EMU_RSTCTRL_SYSRMODE_DISABLED << 2)

#define	EMU_RSTCTRL_SYSRMODE_ENABLED ( _EMU_RSTCTRL_SYSRMODE_ENABLED << 2)

#define	EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0)

#define	EMU_RSTCTRL_WDOG0RMODE_DEFAULT ( _EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0)

#define	EMU_RSTCTRL_WDOG0RMODE_DISABLED ( _EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0)

#define	EMU_RSTCTRL_WDOG0RMODE_ENABLED ( _EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0)

#define	EMU_RSTCTRL_WDOG1RMODE (0x1UL << 1)

#define	EMU_RSTCTRL_WDOG1RMODE_DEFAULT ( _EMU_RSTCTRL_WDOG1RMODE_DEFAULT << 1)

#define	EMU_RSTCTRL_WDOG1RMODE_DISABLED ( _EMU_RSTCTRL_WDOG1RMODE_DISABLED << 1)

#define	EMU_RSTCTRL_WDOG1RMODE_ENABLED ( _EMU_RSTCTRL_WDOG1RMODE_ENABLED << 1)

#define	EMU_SEIEN_TEMP (0x1UL << 29)

#define	EMU_SEIEN_TEMP_DEFAULT ( _EMU_SEIEN_TEMP_DEFAULT << 29)

#define	EMU_SEIEN_TEMPHIGH (0x1UL << 31)

#define	EMU_SEIEN_TEMPHIGH_DEFAULT ( _EMU_SEIEN_TEMPHIGH_DEFAULT << 31)

#define	EMU_SEIEN_TEMPLOW (0x1UL << 30)

#define	EMU_SEIEN_TEMPLOW_DEFAULT ( _EMU_SEIEN_TEMPLOW_DEFAULT << 30)

#define	EMU_SEIF_TEMP (0x1UL << 29)

#define	EMU_SEIF_TEMP_DEFAULT ( _EMU_SEIF_TEMP_DEFAULT << 29)

#define	EMU_SEIF_TEMPHIGH (0x1UL << 31)

#define	EMU_SEIF_TEMPHIGH_DEFAULT ( _EMU_SEIF_TEMPHIGH_DEFAULT << 31)

#define	EMU_SEIF_TEMPLOW (0x1UL << 30)

#define	EMU_SEIF_TEMPLOW_DEFAULT ( _EMU_SEIF_TEMPLOW_DEFAULT << 30)

#define	EMU_STATUS_EM2ENTERED (0x1UL << 14)

#define	EMU_STATUS_EM2ENTERED_DEFAULT ( _EMU_STATUS_EM2ENTERED_DEFAULT << 14)

#define	EMU_STATUS_EM4IORET (0x1UL << 12)

#define	EMU_STATUS_EM4IORET_DEFAULT ( _EMU_STATUS_EM4IORET_DEFAULT << 12)

#define	EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1)

#define	EMU_STATUS_FIRSTTEMPDONE_DEFAULT ( _EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1)

#define	EMU_STATUS_LOCK (0x1UL << 0)

#define	EMU_STATUS_LOCK_DEFAULT ( _EMU_STATUS_LOCK_DEFAULT << 0)

#define	EMU_STATUS_LOCK_LOCKED ( _EMU_STATUS_LOCK_LOCKED << 0)

#define	EMU_STATUS_LOCK_UNLOCKED ( _EMU_STATUS_LOCK_UNLOCKED << 0)

#define	EMU_STATUS_RACACTIVE (0x1UL << 10)

#define	EMU_STATUS_RACACTIVE_DEFAULT ( _EMU_STATUS_RACACTIVE_DEFAULT << 10)

#define	EMU_STATUS_TEMPACTIVE (0x1UL << 2)

#define	EMU_STATUS_TEMPACTIVE_DEFAULT ( _EMU_STATUS_TEMPACTIVE_DEFAULT << 2)

#define	EMU_TEMP_TEMP_DEFAULT ( _EMU_TEMP_TEMP_DEFAULT << 2)

#define	EMU_TEMP_TEMPLSB_DEFAULT ( _EMU_TEMP_TEMPLSB_DEFAULT << 0)

#define	EMU_TEMPLIMITS_TEMPHIGH_DEFAULT ( _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16)

#define	EMU_TEMPLIMITS_TEMPLOW_DEFAULT ( _EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)

Macro Definition Documentation

#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_BOD3SENSE

Definition at line 192 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL

Bit mask for EMU_AVDDBODEN

Definition at line 191 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0

Shift value for EMU_AVDDBODEN

Definition at line 190 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_BOD3SENSE

Definition at line 197 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_IOVDD0BODEN_MASK 0x2UL

Bit mask for EMU_IOVDD0BODEN

Definition at line 196 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_IOVDD0BODEN_SHIFT 1

Shift value for EMU_IOVDD0BODEN

Definition at line 195 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_BOD3SENSE

Definition at line 202 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_IOVDD1BODEN_MASK 0x4UL

Bit mask for EMU_IOVDD1BODEN

Definition at line 201 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_IOVDD1BODEN_SHIFT 2

Shift value for EMU_IOVDD1BODEN

Definition at line 200 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_MASK 0x00000077UL

Mask for EMU_BOD3SENSE

Definition at line 188 of file efr32mg21_emu.h .

#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL

Default value for EMU_BOD3SENSE

Definition at line 187 of file efr32mg21_emu.h .

#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 307 of file efr32mg21_emu.h .

#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL

Bit mask for EMU_EM4UNLATCH

Definition at line 306 of file efr32mg21_emu.h .

#define _EMU_CMD_EM4UNLATCH_SHIFT 1

Shift value for EMU_EM4UNLATCH

Definition at line 305 of file efr32mg21_emu.h .

#define _EMU_CMD_MASK 0x00020E02UL

Mask for EMU_CMD

Definition at line 303 of file efr32mg21_emu.h .

#define _EMU_CMD_RESETVALUE 0x00000000UL

Default value for EMU_CMD

Definition at line 302 of file efr32mg21_emu.h .

#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_CMD

Definition at line 312 of file efr32mg21_emu.h .

#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL

Bit mask for EMU_RSTCAUSECLR

Definition at line 311 of file efr32mg21_emu.h .

#define _EMU_CMD_RSTCAUSECLR_SHIFT 17

Shift value for EMU_RSTCAUSECLR

Definition at line 310 of file efr32mg21_emu.h .

#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 321 of file efr32mg21_emu.h .

#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL

Bit mask for EMU_EM2DBGEN

Definition at line 320 of file efr32mg21_emu.h .

#define _EMU_CTRL_EM2DBGEN_SHIFT 0

Shift value for EMU_EM2DBGEN

Definition at line 319 of file efr32mg21_emu.h .

#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_CTRL

Definition at line 326 of file efr32mg21_emu.h .

#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL

Bit mask for EMU_FLASHPWRUPONDEMAND

Definition at line 325 of file efr32mg21_emu.h .

#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16

Shift value for EMU_FLASHPWRUPONDEMAND

Definition at line 324 of file efr32mg21_emu.h .

#define _EMU_CTRL_MASK 0x0001F303UL

Mask for EMU_CTRL

Definition at line 317 of file efr32mg21_emu.h .

#define _EMU_CTRL_RESETVALUE 0x0000A200UL

Default value for EMU_CTRL

Definition at line 316 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DECBOD

Definition at line 168 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECBODEN_MASK 0x1UL

Bit mask for EMU_DECBODEN

Definition at line 167 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECBODEN_SHIFT 0

Shift value for EMU_DECBODEN

Definition at line 166 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_DECBOD

Definition at line 173 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL

Bit mask for EMU_DECBODMASK

Definition at line 172 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECBODMASK_SHIFT 1

Shift value for EMU_DECBODMASK

Definition at line 171 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DECBOD

Definition at line 178 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL

Bit mask for EMU_DECOVMBODEN

Definition at line 177 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4

Shift value for EMU_DECOVMBODEN

Definition at line 176 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_DECBOD

Definition at line 183 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL

Bit mask for EMU_DECOVMBODMASK

Definition at line 182 of file efr32mg21_emu.h .

#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5

Shift value for EMU_DECOVMBODMASK

Definition at line 181 of file efr32mg21_emu.h .

#define _EMU_DECBOD_MASK 0x00000033UL

Mask for EMU_DECBOD

Definition at line 164 of file efr32mg21_emu.h .

#define _EMU_DECBOD_RESETVALUE 0x00000022UL

Default value for EMU_DECBOD

Definition at line 163 of file efr32mg21_emu.h .

#define _EMU_DGIEN_EM23WAKEUP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIEN

Definition at line 585 of file efr32mg21_emu.h .

#define _EMU_DGIEN_EM23WAKEUP_MASK 0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 584 of file efr32mg21_emu.h .

#define _EMU_DGIEN_EM23WAKEUP_SHIFT 24

Shift value for EMU_EM23WAKEUP

Definition at line 583 of file efr32mg21_emu.h .

#define _EMU_DGIEN_MASK 0xE1000000UL

Mask for EMU_DGIEN

Definition at line 581 of file efr32mg21_emu.h .

#define _EMU_DGIEN_RESETVALUE 0x00000000UL

Default value for EMU_DGIEN

Definition at line 580 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIEN

Definition at line 590 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMP_MASK 0x20000000UL

Bit mask for EMU_TEMP

Definition at line 589 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMP_SHIFT 29

Shift value for EMU_TEMP

Definition at line 588 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMPHIGH_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIEN

Definition at line 600 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMPHIGH_MASK 0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 599 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMPHIGH_SHIFT 31

Shift value for EMU_TEMPHIGH

Definition at line 598 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMPLOW_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIEN

Definition at line 595 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMPLOW_MASK 0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 594 of file efr32mg21_emu.h .

#define _EMU_DGIEN_TEMPLOW_SHIFT 30

Shift value for EMU_TEMPLOW

Definition at line 593 of file efr32mg21_emu.h .

#define _EMU_DGIF_EM23WAKEUP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIF

Definition at line 561 of file efr32mg21_emu.h .

#define _EMU_DGIF_EM23WAKEUP_MASK 0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 560 of file efr32mg21_emu.h .

#define _EMU_DGIF_EM23WAKEUP_SHIFT 24

Shift value for EMU_EM23WAKEUP

Definition at line 559 of file efr32mg21_emu.h .

#define _EMU_DGIF_MASK 0xE1000000UL

Mask for EMU_DGIF

Definition at line 557 of file efr32mg21_emu.h .

#define _EMU_DGIF_RESETVALUE 0x00000000UL

Default value for EMU_DGIF

Definition at line 556 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIF

Definition at line 566 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMP_MASK 0x20000000UL

Bit mask for EMU_TEMP

Definition at line 565 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMP_SHIFT 29

Shift value for EMU_TEMP

Definition at line 564 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMPHIGH_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIF

Definition at line 576 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMPHIGH_MASK 0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 575 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMPHIGH_SHIFT 31

Shift value for EMU_TEMPHIGH

Definition at line 574 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMPLOW_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_DGIF

Definition at line 571 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMPLOW_MASK 0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 570 of file efr32mg21_emu.h .

#define _EMU_DGIF_TEMPLOW_SHIFT 30

Shift value for EMU_TEMPLOW

Definition at line 569 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 288 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL

Bit mask for EMU_EM4ENTRY

Definition at line 287 of file efr32mg21_emu.h .

Referenced by EMU_EnterEM4() .

#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0

Shift value for EMU_EM4ENTRY

Definition at line 286 of file efr32mg21_emu.h .

Referenced by EMU_EnterEM4() .

#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_EM4CTRL

Definition at line 292 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL

Mode DISABLE for EMU_EM4CTRL

Definition at line 293 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL

Mode EM4EXIT for EMU_EM4CTRL

Definition at line 294 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL

Bit mask for EMU_EM4IORETMODE

Definition at line 291 of file efr32mg21_emu.h .

Referenced by EMU_EM4Init() , and GPIO_EM4SetPinRetention() .

#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4

Shift value for EMU_EM4IORETMODE

Definition at line 290 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL

Mode SWUNLATCH for EMU_EM4CTRL

Definition at line 295 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_MASK 0x00000033UL

Mask for EMU_EM4CTRL

Definition at line 285 of file efr32mg21_emu.h .

#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL

Default value for EMU_EM4CTRL

Definition at line 284 of file efr32mg21_emu.h .

#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 255 of file efr32mg21_emu.h .

#define _EMU_IEN_AVDDBOD_MASK 0x10000UL

Bit mask for EMU_AVDDBOD

Definition at line 254 of file efr32mg21_emu.h .

#define _EMU_IEN_AVDDBOD_SHIFT 16

Shift value for EMU_AVDDBOD

Definition at line 253 of file efr32mg21_emu.h .

#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 265 of file efr32mg21_emu.h .

#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 264 of file efr32mg21_emu.h .

#define _EMU_IEN_EM23WAKEUP_SHIFT 24

Shift value for EMU_EM23WAKEUP

Definition at line 263 of file efr32mg21_emu.h .

#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 260 of file efr32mg21_emu.h .

#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL

Bit mask for EMU_IOVDD0BOD

Definition at line 259 of file efr32mg21_emu.h .

#define _EMU_IEN_IOVDD0BOD_SHIFT 17

Shift value for EMU_IOVDD0BOD

Definition at line 258 of file efr32mg21_emu.h .

#define _EMU_IEN_MASK 0xE3070000UL

Mask for EMU_IEN

Definition at line 251 of file efr32mg21_emu.h .

#define _EMU_IEN_RESETVALUE 0x00000000UL

Default value for EMU_IEN

Definition at line 250 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 270 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMP_MASK 0x20000000UL

Bit mask for EMU_TEMP

Definition at line 269 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMP_SHIFT 29

Shift value for EMU_TEMP

Definition at line 268 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 280 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 279 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMPHIGH_SHIFT 31

Shift value for EMU_TEMPHIGH

Definition at line 278 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IEN

Definition at line 275 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 274 of file efr32mg21_emu.h .

#define _EMU_IEN_TEMPLOW_SHIFT 30

Shift value for EMU_TEMPLOW

Definition at line 273 of file efr32mg21_emu.h .

#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 221 of file efr32mg21_emu.h .

#define _EMU_IF_AVDDBOD_MASK 0x10000UL

Bit mask for EMU_AVDDBOD

Definition at line 220 of file efr32mg21_emu.h .

#define _EMU_IF_AVDDBOD_SHIFT 16

Shift value for EMU_AVDDBOD

Definition at line 219 of file efr32mg21_emu.h .

#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 231 of file efr32mg21_emu.h .

#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL

Bit mask for EMU_EM23WAKEUP

Definition at line 230 of file efr32mg21_emu.h .

#define _EMU_IF_EM23WAKEUP_SHIFT 24

Shift value for EMU_EM23WAKEUP

Definition at line 229 of file efr32mg21_emu.h .

#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 226 of file efr32mg21_emu.h .

#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL

Bit mask for EMU_IOVDD0BOD

Definition at line 225 of file efr32mg21_emu.h .

#define _EMU_IF_IOVDD0BOD_SHIFT 17

Shift value for EMU_IOVDD0BOD

Definition at line 224 of file efr32mg21_emu.h .

#define _EMU_IF_MASK 0xE3070000UL

Mask for EMU_IF

Definition at line 217 of file efr32mg21_emu.h .

#define _EMU_IF_RESETVALUE 0x00000000UL

Default value for EMU_IF

Definition at line 216 of file efr32mg21_emu.h .

#define _EMU_IF_TEMP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 236 of file efr32mg21_emu.h .

#define _EMU_IF_TEMP_MASK 0x20000000UL

Bit mask for EMU_TEMP

Definition at line 235 of file efr32mg21_emu.h .

#define _EMU_IF_TEMP_SHIFT 29

Shift value for EMU_TEMP

Definition at line 234 of file efr32mg21_emu.h .

#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 246 of file efr32mg21_emu.h .

#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 245 of file efr32mg21_emu.h .

#define _EMU_IF_TEMPHIGH_SHIFT 31

Shift value for EMU_TEMPHIGH

Definition at line 244 of file efr32mg21_emu.h .

#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_IF

Definition at line 241 of file efr32mg21_emu.h .

#define _EMU_IF_TEMPLOW_MASK 0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 240 of file efr32mg21_emu.h .

#define _EMU_IF_TEMPLOW_SHIFT 30

Shift value for EMU_TEMPLOW

Definition at line 239 of file efr32mg21_emu.h .

#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL

Mode DEFAULT for EMU_LOCK

Definition at line 210 of file efr32mg21_emu.h .

#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL

Bit mask for EMU_LOCKKEY

Definition at line 209 of file efr32mg21_emu.h .

#define _EMU_LOCK_LOCKKEY_SHIFT 0

Shift value for EMU_LOCKKEY

Definition at line 208 of file efr32mg21_emu.h .

#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL

Mode UNLOCK for EMU_LOCK

Definition at line 211 of file efr32mg21_emu.h .

#define _EMU_LOCK_MASK 0x0000FFFFUL

Mask for EMU_LOCK

Definition at line 207 of file efr32mg21_emu.h .

#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL

Default value for EMU_LOCK

Definition at line 206 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 532 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL

Bit mask for EMU_AVDDBOD

Definition at line 531 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10

Shift value for EMU_AVDDBOD

Definition at line 530 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 527 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL

Bit mask for EMU_DECBOD

Definition at line 526 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DECBOD_SHIFT 9

Shift value for EMU_DECBOD

Definition at line 525 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 517 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL

Bit mask for EMU_DVDDBOD

Definition at line 516 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7

Shift value for EMU_DVDDBOD

Definition at line 515 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 522 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL

Bit mask for EMU_DVDDLEBOD

Definition at line 521 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8

Shift value for EMU_DVDDLEBOD

Definition at line 520 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 492 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_EM4_MASK 0x4UL

Bit mask for EMU_EM4

Definition at line 491 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_EM4_SHIFT 2

Shift value for EMU_EM4

Definition at line 490 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 537 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL

Bit mask for EMU_IOVDD0BOD

Definition at line 536 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11

Shift value for EMU_IOVDD0BOD

Definition at line 535 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 507 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL

Bit mask for EMU_LOCKUP

Definition at line 506 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5

Shift value for EMU_LOCKUP

Definition at line 505 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_MASK 0x0000FFFFUL

Mask for EMU_RSTCAUSE

Definition at line 478 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 487 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_PIN_MASK 0x2UL

Bit mask for EMU_PIN

Definition at line 486 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_PIN_SHIFT 1

Shift value for EMU_PIN

Definition at line 485 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 482 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_POR_MASK 0x1UL

Bit mask for EMU_POR

Definition at line 481 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_POR_SHIFT 0

Shift value for EMU_POR

Definition at line 480 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL

Default value for EMU_RSTCAUSE

Definition at line 477 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SELOCKUP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 552 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SELOCKUP_MASK 0x8000UL

Bit mask for EMU_SELOCKUP

Definition at line 551 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SELOCKUP_SHIFT 15

Shift value for EMU_SELOCKUP

Definition at line 550 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SESYSREQ_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 547 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SESYSREQ_MASK 0x4000UL

Bit mask for EMU_SESYSREQ

Definition at line 546 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SESYSREQ_SHIFT 14

Shift value for EMU_SESYSREQ

Definition at line 545 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 542 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL

Bit mask for EMU_SETAMPER

Definition at line 541 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13

Shift value for EMU_SETAMPER

Definition at line 540 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 512 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL

Bit mask for EMU_SYSREQ

Definition at line 511 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6

Shift value for EMU_SYSREQ

Definition at line 510 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 497 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL

Bit mask for EMU_WDOG0

Definition at line 496 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_WDOG0_SHIFT 3

Shift value for EMU_WDOG0

Definition at line 495 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCAUSE

Definition at line 502 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL

Bit mask for EMU_WDOG1

Definition at line 501 of file efr32mg21_emu.h .

#define _EMU_RSTCAUSE_WDOG1_SHIFT 4

Shift value for EMU_WDOG1

Definition at line 500 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 433 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 434 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 435 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL

Bit mask for EMU_AVDDBODRMODE

Definition at line 432 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6

Shift value for EMU_AVDDBODRMODE

Definition at line 431 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 451 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 452 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 453 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL

Bit mask for EMU_DECBODRMODE

Definition at line 450 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10

Shift value for EMU_DECBODRMODE

Definition at line 449 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 442 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 443 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 444 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL

Bit mask for EMU_IOVDD0BODRMODE

Definition at line 441 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7

Shift value for EMU_IOVDD0BODRMODE

Definition at line 440 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 424 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 425 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 426 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL

Bit mask for EMU_LOCKUPRMODE

Definition at line 423 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3

Shift value for EMU_LOCKUPRMODE

Definition at line 422 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_MASK 0x0000C5CFUL

Mask for EMU_RSTCTRL

Definition at line 393 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_RESETVALUE 0x00004407UL

Default value for EMU_RSTCTRL

Definition at line 392 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SELOCKUPRMODE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 469 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SELOCKUPRMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 470 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SELOCKUPRMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 471 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SELOCKUPRMODE_MASK 0x8000UL

Bit mask for EMU_SELOCKUPRMODE

Definition at line 468 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SELOCKUPRMODE_SHIFT 15

Shift value for EMU_SELOCKUPRMODE

Definition at line 467 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SESYSRMODE_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 460 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SESYSRMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 461 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SESYSRMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 462 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SESYSRMODE_MASK 0x4000UL

Bit mask for EMU_SESYSRMODE

Definition at line 459 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SESYSRMODE_SHIFT 14

Shift value for EMU_SESYSRMODE

Definition at line 458 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 415 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 416 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 417 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL

Bit mask for EMU_SYSRMODE

Definition at line 414 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2

Shift value for EMU_SYSRMODE

Definition at line 413 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 397 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 398 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 399 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL

Bit mask for EMU_WDOG0RMODE

Definition at line 396 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0

Shift value for EMU_WDOG0RMODE

Definition at line 395 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG1RMODE_DEFAULT 0x00000001UL

Mode DEFAULT for EMU_RSTCTRL

Definition at line 406 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG1RMODE_DISABLED 0x00000000UL

Mode DISABLED for EMU_RSTCTRL

Definition at line 407 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG1RMODE_ENABLED 0x00000001UL

Mode ENABLED for EMU_RSTCTRL

Definition at line 408 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG1RMODE_MASK 0x2UL

Bit mask for EMU_WDOG1RMODE

Definition at line 405 of file efr32mg21_emu.h .

#define _EMU_RSTCTRL_WDOG1RMODE_SHIFT 1

Shift value for EMU_WDOG1RMODE

Definition at line 404 of file efr32mg21_emu.h .

#define _EMU_SEIEN_MASK 0xE0000000UL

Mask for EMU_SEIEN

Definition at line 624 of file efr32mg21_emu.h .

#define _EMU_SEIEN_RESETVALUE 0x00000000UL

Default value for EMU_SEIEN

Definition at line 623 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_SEIEN

Definition at line 628 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMP_MASK 0x20000000UL

Bit mask for EMU_TEMP

Definition at line 627 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMP_SHIFT 29

Shift value for EMU_TEMP

Definition at line 626 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMPHIGH_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_SEIEN

Definition at line 638 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMPHIGH_MASK 0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 637 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMPHIGH_SHIFT 31

Shift value for EMU_TEMPHIGH

Definition at line 636 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMPLOW_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_SEIEN

Definition at line 633 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMPLOW_MASK 0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 632 of file efr32mg21_emu.h .

#define _EMU_SEIEN_TEMPLOW_SHIFT 30

Shift value for EMU_TEMPLOW

Definition at line 631 of file efr32mg21_emu.h .

#define _EMU_SEIF_MASK 0xE0000000UL

Mask for EMU_SEIF

Definition at line 605 of file efr32mg21_emu.h .

#define _EMU_SEIF_RESETVALUE 0x00000000UL

Default value for EMU_SEIF

Definition at line 604 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_SEIF

Definition at line 609 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMP_MASK 0x20000000UL

Bit mask for EMU_TEMP

Definition at line 608 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMP_SHIFT 29

Shift value for EMU_TEMP

Definition at line 607 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMPHIGH_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_SEIF

Definition at line 619 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMPHIGH_MASK 0x80000000UL

Bit mask for EMU_TEMPHIGH

Definition at line 618 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMPHIGH_SHIFT 31

Shift value for EMU_TEMPHIGH

Definition at line 617 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMPLOW_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_SEIF

Definition at line 614 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMPLOW_MASK 0x40000000UL

Bit mask for EMU_TEMPLOW

Definition at line 613 of file efr32mg21_emu.h .

#define _EMU_SEIF_TEMPLOW_SHIFT 30

Shift value for EMU_TEMPLOW

Definition at line 612 of file efr32mg21_emu.h .

#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 376 of file efr32mg21_emu.h .

#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL

Bit mask for EMU_EM2ENTERED

Definition at line 375 of file efr32mg21_emu.h .

#define _EMU_STATUS_EM2ENTERED_SHIFT 14

Shift value for EMU_EM2ENTERED

Definition at line 374 of file efr32mg21_emu.h .

#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 371 of file efr32mg21_emu.h .

#define _EMU_STATUS_EM4IORET_MASK 0x1000UL

Bit mask for EMU_EM4IORET

Definition at line 370 of file efr32mg21_emu.h .

#define _EMU_STATUS_EM4IORET_SHIFT 12

Shift value for EMU_EM4IORET

Definition at line 369 of file efr32mg21_emu.h .

#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 356 of file efr32mg21_emu.h .

#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL

Bit mask for EMU_FIRSTTEMPDONE

Definition at line 355 of file efr32mg21_emu.h .

#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1

Shift value for EMU_FIRSTTEMPDONE

Definition at line 354 of file efr32mg21_emu.h .

#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 347 of file efr32mg21_emu.h .

#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL

Mode LOCKED for EMU_STATUS

Definition at line 349 of file efr32mg21_emu.h .

#define _EMU_STATUS_LOCK_MASK 0x1UL

Bit mask for EMU_LOCK

Definition at line 346 of file efr32mg21_emu.h .

#define _EMU_STATUS_LOCK_SHIFT 0

Shift value for EMU_LOCK

Definition at line 345 of file efr32mg21_emu.h .

#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL

Mode UNLOCKED for EMU_STATUS

Definition at line 348 of file efr32mg21_emu.h .

#define _EMU_STATUS_MASK 0x000054F7UL

Mask for EMU_STATUS

Definition at line 343 of file efr32mg21_emu.h .

#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 366 of file efr32mg21_emu.h .

#define _EMU_STATUS_RACACTIVE_MASK 0x400UL

Bit mask for EMU_RACACTIVE

Definition at line 365 of file efr32mg21_emu.h .

#define _EMU_STATUS_RACACTIVE_SHIFT 10

Shift value for EMU_RACACTIVE

Definition at line 364 of file efr32mg21_emu.h .

#define _EMU_STATUS_RESETVALUE 0x00000080UL

Default value for EMU_STATUS

Definition at line 342 of file efr32mg21_emu.h .

#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_STATUS

Definition at line 361 of file efr32mg21_emu.h .

#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL

Bit mask for EMU_TEMPACTIVE

Definition at line 360 of file efr32mg21_emu.h .

#define _EMU_STATUS_TEMPACTIVE_SHIFT 2

Shift value for EMU_TEMPACTIVE

Definition at line 359 of file efr32mg21_emu.h .

#define _EMU_TEMP_MASK 0x000007FFUL

Mask for EMU_TEMP

Definition at line 381 of file efr32mg21_emu.h .

#define _EMU_TEMP_RESETVALUE 0x00000000UL

Default value for EMU_TEMP

Definition at line 380 of file efr32mg21_emu.h .

#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_TEMP

Definition at line 388 of file efr32mg21_emu.h .

#define _EMU_TEMP_TEMP_MASK 0x7FCUL

Bit mask for EMU_TEMP

Definition at line 387 of file efr32mg21_emu.h .

Referenced by TEMPDRV_GetTemp() .

#define _EMU_TEMP_TEMP_SHIFT 2

Shift value for EMU_TEMP

Definition at line 386 of file efr32mg21_emu.h .

Referenced by TEMPDRV_GetTemp() .

#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_TEMP

Definition at line 384 of file efr32mg21_emu.h .

#define _EMU_TEMP_TEMPLSB_MASK 0x3UL

Bit mask for EMU_TEMPLSB

Definition at line 383 of file efr32mg21_emu.h .

#define _EMU_TEMP_TEMPLSB_SHIFT 0

Shift value for EMU_TEMPLSB

Definition at line 382 of file efr32mg21_emu.h .

#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL

Mask for EMU_TEMPLIMITS

Definition at line 331 of file efr32mg21_emu.h .

#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL

Default value for EMU_TEMPLIMITS

Definition at line 330 of file efr32mg21_emu.h .

#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL

Mode DEFAULT for EMU_TEMPLIMITS

Definition at line 338 of file efr32mg21_emu.h .

#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL

Bit mask for EMU_TEMPHIGH

Definition at line 337 of file efr32mg21_emu.h .

Referenced by updateInterrupts() .

#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16

Shift value for EMU_TEMPHIGH

Definition at line 336 of file efr32mg21_emu.h .

Referenced by updateInterrupts() .

#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL

Mode DEFAULT for EMU_TEMPLIMITS

Definition at line 334 of file efr32mg21_emu.h .

#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL

Bit mask for EMU_TEMPLOW

Definition at line 333 of file efr32mg21_emu.h .

Referenced by updateInterrupts() .

#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0

Shift value for EMU_TEMPLOW

Definition at line 332 of file efr32mg21_emu.h .

Referenced by updateInterrupts() .

#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0)

AVDD BOD enable

Definition at line 189 of file efr32mg21_emu.h .

#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT ( _EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0)

Shifted mode DEFAULT for EMU_BOD3SENSE

Definition at line 193 of file efr32mg21_emu.h .

#define EMU_BOD3SENSE_IOVDD0BODEN (0x1UL << 1)

VDDIO0 BOD enable

Definition at line 194 of file efr32mg21_emu.h .

#define EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT ( _EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT << 1)

Shifted mode DEFAULT for EMU_BOD3SENSE

Definition at line 198 of file efr32mg21_emu.h .

#define EMU_BOD3SENSE_IOVDD1BODEN (0x1UL << 2)

VDDIO1 BOD enable

Definition at line 199 of file efr32mg21_emu.h .

#define EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT ( _EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT << 2)

Shifted mode DEFAULT for EMU_BOD3SENSE

Definition at line 203 of file efr32mg21_emu.h .

#define EMU_CMD_EM4UNLATCH (0x1UL << 1)

EM4 unlatch

Definition at line 304 of file efr32mg21_emu.h .

Referenced by EMU_UnlatchPinRetention() .

#define EMU_CMD_EM4UNLATCH_DEFAULT ( _EMU_CMD_EM4UNLATCH_DEFAULT << 1)

Shifted mode DEFAULT for EMU_CMD

Definition at line 308 of file efr32mg21_emu.h .

#define EMU_CMD_RSTCAUSECLR (0x1UL << 17)

Reset Cause Clear

Definition at line 309 of file efr32mg21_emu.h .

Referenced by RMU_ResetCauseClear() .

#define EMU_CMD_RSTCAUSECLR_DEFAULT ( _EMU_CMD_RSTCAUSECLR_DEFAULT << 17)

Shifted mode DEFAULT for EMU_CMD

Definition at line 313 of file efr32mg21_emu.h .

#define EMU_CTRL_EM2DBGEN (0x1UL << 0)

Enable debugging in EM2

Definition at line 318 of file efr32mg21_emu.h .

#define EMU_CTRL_EM2DBGEN_DEFAULT ( _EMU_CTRL_EM2DBGEN_DEFAULT << 0)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 322 of file efr32mg21_emu.h .

#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16)

Enable flash on demand wakeup

Definition at line 323 of file efr32mg21_emu.h .

#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT ( _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16)

Shifted mode DEFAULT for EMU_CTRL

Definition at line 327 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECBODEN (0x1UL << 0)

DECBOD enable

Definition at line 165 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECBODEN_DEFAULT ( _EMU_DECBOD_DECBODEN_DEFAULT << 0)

Shifted mode DEFAULT for EMU_DECBOD

Definition at line 169 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECBODMASK (0x1UL << 1)

DECBOD Mask

Definition at line 170 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECBODMASK_DEFAULT ( _EMU_DECBOD_DECBODMASK_DEFAULT << 1)

Shifted mode DEFAULT for EMU_DECBOD

Definition at line 174 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4)

Over Voltage Monitor enable

Definition at line 175 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECOVMBODEN_DEFAULT ( _EMU_DECBOD_DECOVMBODEN_DEFAULT << 4)

Shifted mode DEFAULT for EMU_DECBOD

Definition at line 179 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5)

Over Voltage Monitor Mask

Definition at line 180 of file efr32mg21_emu.h .

#define EMU_DECBOD_DECOVMBODMASK_DEFAULT ( _EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5)

Shifted mode DEFAULT for EMU_DECBOD

Definition at line 184 of file efr32mg21_emu.h .

#define EMU_DGIEN_EM23WAKEUP (0x1UL << 24)

EM23 Wake up Interrupt enable

Definition at line 582 of file efr32mg21_emu.h .

#define EMU_DGIEN_EM23WAKEUP_DEFAULT ( _EMU_DGIEN_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_DGIEN

Definition at line 586 of file efr32mg21_emu.h .

#define EMU_DGIEN_TEMP (0x1UL << 29)

Temperature Interrupt enable

Definition at line 587 of file efr32mg21_emu.h .

#define EMU_DGIEN_TEMP_DEFAULT ( _EMU_DGIEN_TEMP_DEFAULT << 29)

Shifted mode DEFAULT for EMU_DGIEN

Definition at line 591 of file efr32mg21_emu.h .

#define EMU_DGIEN_TEMPHIGH (0x1UL << 31)

Temperature high Interrupt enable

Definition at line 597 of file efr32mg21_emu.h .

#define EMU_DGIEN_TEMPHIGH_DEFAULT ( _EMU_DGIEN_TEMPHIGH_DEFAULT << 31)

Shifted mode DEFAULT for EMU_DGIEN

Definition at line 601 of file efr32mg21_emu.h .

#define EMU_DGIEN_TEMPLOW (0x1UL << 30)

Temperature low Interrupt enable

Definition at line 592 of file efr32mg21_emu.h .

#define EMU_DGIEN_TEMPLOW_DEFAULT ( _EMU_DGIEN_TEMPLOW_DEFAULT << 30)

Shifted mode DEFAULT for EMU_DGIEN

Definition at line 596 of file efr32mg21_emu.h .

#define EMU_DGIF_EM23WAKEUP (0x1UL << 24)

EM23 Wake up Interrupt flag

Definition at line 558 of file efr32mg21_emu.h .

#define EMU_DGIF_EM23WAKEUP_DEFAULT ( _EMU_DGIF_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_DGIF

Definition at line 562 of file efr32mg21_emu.h .

#define EMU_DGIF_TEMP (0x1UL << 29)

Temperature Interrupt flag

Definition at line 563 of file efr32mg21_emu.h .

#define EMU_DGIF_TEMP_DEFAULT ( _EMU_DGIF_TEMP_DEFAULT << 29)

Shifted mode DEFAULT for EMU_DGIF

Definition at line 567 of file efr32mg21_emu.h .

#define EMU_DGIF_TEMPHIGH (0x1UL << 31)

Temperature high Interrupt flag

Definition at line 573 of file efr32mg21_emu.h .

#define EMU_DGIF_TEMPHIGH_DEFAULT ( _EMU_DGIF_TEMPHIGH_DEFAULT << 31)

Shifted mode DEFAULT for EMU_DGIF

Definition at line 577 of file efr32mg21_emu.h .

#define EMU_DGIF_TEMPLOW (0x1UL << 30)

Temperature low Interrupt flag

Definition at line 568 of file efr32mg21_emu.h .

#define EMU_DGIF_TEMPLOW_DEFAULT ( _EMU_DGIF_TEMPLOW_DEFAULT << 30)

Shifted mode DEFAULT for EMU_DGIF

Definition at line 572 of file efr32mg21_emu.h .

#define EMU_EM4CTRL_EM4ENTRY_DEFAULT ( _EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 289 of file efr32mg21_emu.h .

#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT ( _EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)

Shifted mode DEFAULT for EMU_EM4CTRL

Definition at line 296 of file efr32mg21_emu.h .

#define EMU_EM4CTRL_EM4IORETMODE_DISABLE ( _EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)

Shifted mode DISABLE for EMU_EM4CTRL

Definition at line 297 of file efr32mg21_emu.h .

Referenced by GPIO_EM4SetPinRetention() .

#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT ( _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)

Shifted mode EM4EXIT for EMU_EM4CTRL

Definition at line 298 of file efr32mg21_emu.h .

Referenced by GPIO_EM4SetPinRetention() .

#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH ( _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)

Shifted mode SWUNLATCH for EMU_EM4CTRL

Definition at line 299 of file efr32mg21_emu.h .

Referenced by GPIO_EM4SetPinRetention() .

#define EMU_IEN_AVDDBOD (0x1UL << 16)

AVDD BOD Interrupt enable

Definition at line 252 of file efr32mg21_emu.h .

#define EMU_IEN_AVDDBOD_DEFAULT ( _EMU_IEN_AVDDBOD_DEFAULT << 16)

Shifted mode DEFAULT for EMU_IEN

Definition at line 256 of file efr32mg21_emu.h .

#define EMU_IEN_EM23WAKEUP (0x1UL << 24)

EM23 Wake up Interrupt enable

Definition at line 262 of file efr32mg21_emu.h .

#define EMU_IEN_EM23WAKEUP_DEFAULT ( _EMU_IEN_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_IEN

Definition at line 266 of file efr32mg21_emu.h .

#define EMU_IEN_IOVDD0BOD (0x1UL << 17)

VDDIO0 BOD Interrupt enable

Definition at line 257 of file efr32mg21_emu.h .

#define EMU_IEN_IOVDD0BOD_DEFAULT ( _EMU_IEN_IOVDD0BOD_DEFAULT << 17)

Shifted mode DEFAULT for EMU_IEN

Definition at line 261 of file efr32mg21_emu.h .

#define EMU_IEN_TEMP (0x1UL << 29)

Temperature Interrupt enable

Definition at line 267 of file efr32mg21_emu.h .

#define EMU_IEN_TEMP_DEFAULT ( _EMU_IEN_TEMP_DEFAULT << 29)

Shifted mode DEFAULT for EMU_IEN

Definition at line 271 of file efr32mg21_emu.h .

#define EMU_IEN_TEMPHIGH (0x1UL << 31)

Temperature high Interrupt enable

Definition at line 277 of file efr32mg21_emu.h .

Referenced by updateInterrupts() .

#define EMU_IEN_TEMPHIGH_DEFAULT ( _EMU_IEN_TEMPHIGH_DEFAULT << 31)

Shifted mode DEFAULT for EMU_IEN

Definition at line 281 of file efr32mg21_emu.h .

#define EMU_IEN_TEMPLOW (0x1UL << 30)

Temperature low Interrupt enable

Definition at line 272 of file efr32mg21_emu.h .

Referenced by updateInterrupts() .

#define EMU_IEN_TEMPLOW_DEFAULT ( _EMU_IEN_TEMPLOW_DEFAULT << 30)

Shifted mode DEFAULT for EMU_IEN

Definition at line 276 of file efr32mg21_emu.h .

#define EMU_IF_AVDDBOD (0x1UL << 16)

AVDD BOD Interrupt flag

Definition at line 218 of file efr32mg21_emu.h .

#define EMU_IF_AVDDBOD_DEFAULT ( _EMU_IF_AVDDBOD_DEFAULT << 16)

Shifted mode DEFAULT for EMU_IF

Definition at line 222 of file efr32mg21_emu.h .

#define EMU_IF_EM23WAKEUP (0x1UL << 24)

EM23 Wake up Interrupt flag

Definition at line 228 of file efr32mg21_emu.h .

#define EMU_IF_EM23WAKEUP_DEFAULT ( _EMU_IF_EM23WAKEUP_DEFAULT << 24)

Shifted mode DEFAULT for EMU_IF

Definition at line 232 of file efr32mg21_emu.h .

#define EMU_IF_IOVDD0BOD (0x1UL << 17)

VDDIO0 BOD Interrupt flag

Definition at line 223 of file efr32mg21_emu.h .

#define EMU_IF_IOVDD0BOD_DEFAULT ( _EMU_IF_IOVDD0BOD_DEFAULT << 17)

Shifted mode DEFAULT for EMU_IF

Definition at line 227 of file efr32mg21_emu.h .

#define EMU_IF_TEMP (0x1UL << 29)

Temperature Interrupt flag

Definition at line 233 of file efr32mg21_emu.h .

#define EMU_IF_TEMP_DEFAULT ( _EMU_IF_TEMP_DEFAULT << 29)

Shifted mode DEFAULT for EMU_IF

Definition at line 237 of file efr32mg21_emu.h .

#define EMU_IF_TEMPHIGH (0x1UL << 31)

Temperature high Interrupt flag

Definition at line 243 of file efr32mg21_emu.h .

Referenced by disableInterrupts() .

#define EMU_IF_TEMPHIGH_DEFAULT ( _EMU_IF_TEMPHIGH_DEFAULT << 31)

Shifted mode DEFAULT for EMU_IF

Definition at line 247 of file efr32mg21_emu.h .

#define EMU_IF_TEMPLOW (0x1UL << 30)

Temperature low Interrupt flag

Definition at line 238 of file efr32mg21_emu.h .

Referenced by disableInterrupts() .

#define EMU_IF_TEMPLOW_DEFAULT ( _EMU_IF_TEMPLOW_DEFAULT << 30)

Shifted mode DEFAULT for EMU_IF

Definition at line 242 of file efr32mg21_emu.h .

#define EMU_LOCK_LOCKKEY_DEFAULT ( _EMU_LOCK_LOCKKEY_DEFAULT << 0)

Shifted mode DEFAULT for EMU_LOCK

Definition at line 212 of file efr32mg21_emu.h .

#define EMU_LOCK_LOCKKEY_UNLOCK ( _EMU_LOCK_LOCKKEY_UNLOCK << 0)

Shifted mode UNLOCK for EMU_LOCK

Definition at line 213 of file efr32mg21_emu.h .

Referenced by EMU_Unlock() .

#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10)

LEBOD1 Reset

Definition at line 529 of file efr32mg21_emu.h .

#define EMU_RSTCAUSE_AVDDBOD_DEFAULT ( _EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10)