WDOG Bit FieldsDevices > WDOG

Macros

#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL
#define _WDOG_CFG_CLRSRC_MASK 0x1UL
#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL
#define _WDOG_CFG_CLRSRC_SHIFT 0
#define _WDOG_CFG_CLRSRC_SW 0x00000000UL
#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL
#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL
#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL
#define _WDOG_CFG_DEBUGRUN_MASK 0x10UL
#define _WDOG_CFG_DEBUGRUN_SHIFT 4
#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL
#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL
#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL
#define _WDOG_CFG_EM2RUN_MASK 0x2UL
#define _WDOG_CFG_EM2RUN_SHIFT 1
#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL
#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL
#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL
#define _WDOG_CFG_EM3RUN_MASK 0x4UL
#define _WDOG_CFG_EM3RUN_SHIFT 2
#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL
#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL
#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL
#define _WDOG_CFG_EM4BLOCK_MASK 0x8UL
#define _WDOG_CFG_EM4BLOCK_SHIFT 3
#define _WDOG_CFG_MASK 0x730F071FUL
#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL
#define _WDOG_CFG_PERSEL_MASK 0xF0000UL
#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL
#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL
#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL
#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL
#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL
#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL
#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL
#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL
#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL
#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL
#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL
#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL
#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL
#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL
#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL
#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL
#define _WDOG_CFG_PERSEL_SHIFT 16
#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL
#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL
#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9
#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL
#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL
#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10
#define _WDOG_CFG_RESETVALUE 0x000F0000UL
#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL
#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL
#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL
#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL
#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL
#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL
#define _WDOG_CFG_WARNSEL_SHIFT 24
#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL
#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL
#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL
#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL
#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8
#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL
#define _WDOG_CFG_WINSEL_DIS 0x00000000UL
#define _WDOG_CFG_WINSEL_MASK 0x70000000UL
#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL
#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL
#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL
#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL
#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL
#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL
#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL
#define _WDOG_CFG_WINSEL_SHIFT 28
#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL
#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL
#define _WDOG_CMD_CLEAR_MASK 0x1UL
#define _WDOG_CMD_CLEAR_SHIFT 0
#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL
#define _WDOG_CMD_MASK 0x00000001UL
#define _WDOG_CMD_RESETVALUE 0x00000000UL
#define _WDOG_EN_EN_DEFAULT 0x00000000UL
#define _WDOG_EN_EN_MASK 0x1UL
#define _WDOG_EN_EN_SHIFT 0
#define _WDOG_EN_MASK 0x00000001UL
#define _WDOG_EN_RESETVALUE 0x00000000UL
#define _WDOG_IEN_MASK 0x0000001FUL
#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL
#define _WDOG_IEN_PEM0_MASK 0x8UL
#define _WDOG_IEN_PEM0_SHIFT 3
#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL
#define _WDOG_IEN_PEM1_MASK 0x10UL
#define _WDOG_IEN_PEM1_SHIFT 4
#define _WDOG_IEN_RESETVALUE 0x00000000UL
#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL
#define _WDOG_IEN_TOUT_MASK 0x1UL
#define _WDOG_IEN_TOUT_SHIFT 0
#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL
#define _WDOG_IEN_WARN_MASK 0x2UL
#define _WDOG_IEN_WARN_SHIFT 1
#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL
#define _WDOG_IEN_WIN_MASK 0x4UL
#define _WDOG_IEN_WIN_SHIFT 2
#define _WDOG_IF_MASK 0x0000001FUL
#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL
#define _WDOG_IF_PEM0_MASK 0x8UL
#define _WDOG_IF_PEM0_SHIFT 3
#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL
#define _WDOG_IF_PEM1_MASK 0x10UL
#define _WDOG_IF_PEM1_SHIFT 4
#define _WDOG_IF_RESETVALUE 0x00000000UL
#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL
#define _WDOG_IF_TOUT_MASK 0x1UL
#define _WDOG_IF_TOUT_SHIFT 0
#define _WDOG_IF_WARN_DEFAULT 0x00000000UL
#define _WDOG_IF_WARN_MASK 0x2UL
#define _WDOG_IF_WARN_SHIFT 1
#define _WDOG_IF_WIN_DEFAULT 0x00000000UL
#define _WDOG_IF_WIN_MASK 0x4UL
#define _WDOG_IF_WIN_SHIFT 2
#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000000UL
#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL
#define _WDOG_IPVERSION_IPVERSION_SHIFT 0
#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL
#define _WDOG_IPVERSION_RESETVALUE 0x00000000UL
#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL
#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL
#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL
#define _WDOG_LOCK_LOCKKEY_SHIFT 0
#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL
#define _WDOG_LOCK_MASK 0x0000FFFFUL
#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL
#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL
#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL
#define _WDOG_STATUS_LOCK_MASK 0x80000000UL
#define _WDOG_STATUS_LOCK_SHIFT 31
#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL
#define _WDOG_STATUS_MASK 0x80000000UL
#define _WDOG_STATUS_RESETVALUE 0x00000000UL
#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL
#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL
#define _WDOG_SYNCBUSY_CMD_SHIFT 0
#define _WDOG_SYNCBUSY_MASK 0x00000001UL
#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL
#define WDOG_CFG_CLRSRC (0x1UL << 0)
#define WDOG_CFG_CLRSRC_DEFAULT ( _WDOG_CFG_CLRSRC_DEFAULT << 0)
#define WDOG_CFG_CLRSRC_PRSSRC0 ( _WDOG_CFG_CLRSRC_PRSSRC0 << 0)
#define WDOG_CFG_CLRSRC_SW ( _WDOG_CFG_CLRSRC_SW << 0)
#define WDOG_CFG_DEBUGRUN (0x1UL << 4)
#define WDOG_CFG_DEBUGRUN_DEFAULT ( _WDOG_CFG_DEBUGRUN_DEFAULT << 4)
#define WDOG_CFG_DEBUGRUN_DISABLE ( _WDOG_CFG_DEBUGRUN_DISABLE << 4)
#define WDOG_CFG_DEBUGRUN_ENABLE ( _WDOG_CFG_DEBUGRUN_ENABLE << 4)
#define WDOG_CFG_EM2RUN (0x1UL << 1)
#define WDOG_CFG_EM2RUN_DEFAULT ( _WDOG_CFG_EM2RUN_DEFAULT << 1)
#define WDOG_CFG_EM2RUN_DISABLE ( _WDOG_CFG_EM2RUN_DISABLE << 1)
#define WDOG_CFG_EM2RUN_ENABLE ( _WDOG_CFG_EM2RUN_ENABLE << 1)
#define WDOG_CFG_EM3RUN (0x1UL << 2)
#define WDOG_CFG_EM3RUN_DEFAULT ( _WDOG_CFG_EM3RUN_DEFAULT << 2)
#define WDOG_CFG_EM3RUN_DISABLE ( _WDOG_CFG_EM3RUN_DISABLE << 2)
#define WDOG_CFG_EM3RUN_ENABLE ( _WDOG_CFG_EM3RUN_ENABLE << 2)
#define WDOG_CFG_EM4BLOCK (0x1UL << 3)
#define WDOG_CFG_EM4BLOCK_DEFAULT ( _WDOG_CFG_EM4BLOCK_DEFAULT << 3)
#define WDOG_CFG_EM4BLOCK_DISABLE ( _WDOG_CFG_EM4BLOCK_DISABLE << 3)
#define WDOG_CFG_EM4BLOCK_ENABLE ( _WDOG_CFG_EM4BLOCK_ENABLE << 3)
#define WDOG_CFG_PERSEL_DEFAULT ( _WDOG_CFG_PERSEL_DEFAULT << 16)
#define WDOG_CFG_PERSEL_SEL0 ( _WDOG_CFG_PERSEL_SEL0 << 16)
#define WDOG_CFG_PERSEL_SEL1 ( _WDOG_CFG_PERSEL_SEL1 << 16)
#define WDOG_CFG_PERSEL_SEL10 ( _WDOG_CFG_PERSEL_SEL10 << 16)
#define WDOG_CFG_PERSEL_SEL11 ( _WDOG_CFG_PERSEL_SEL11 << 16)
#define WDOG_CFG_PERSEL_SEL12 ( _WDOG_CFG_PERSEL_SEL12 << 16)
#define WDOG_CFG_PERSEL_SEL13 ( _WDOG_CFG_PERSEL_SEL13 << 16)
#define WDOG_CFG_PERSEL_SEL14 ( _WDOG_CFG_PERSEL_SEL14 << 16)
#define WDOG_CFG_PERSEL_SEL15 ( _WDOG_CFG_PERSEL_SEL15 << 16)
#define WDOG_CFG_PERSEL_SEL2 ( _WDOG_CFG_PERSEL_SEL2 << 16)
#define WDOG_CFG_PERSEL_SEL3 ( _WDOG_CFG_PERSEL_SEL3 << 16)
#define WDOG_CFG_PERSEL_SEL4 ( _WDOG_CFG_PERSEL_SEL4 << 16)
#define WDOG_CFG_PERSEL_SEL5 ( _WDOG_CFG_PERSEL_SEL5 << 16)
#define WDOG_CFG_PERSEL_SEL6 ( _WDOG_CFG_PERSEL_SEL6 << 16)
#define WDOG_CFG_PERSEL_SEL7 ( _WDOG_CFG_PERSEL_SEL7 << 16)
#define WDOG_CFG_PERSEL_SEL8 ( _WDOG_CFG_PERSEL_SEL8 << 16)
#define WDOG_CFG_PERSEL_SEL9 ( _WDOG_CFG_PERSEL_SEL9 << 16)
#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9)
#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT ( _WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9)
#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10)
#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT ( _WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10)
#define WDOG_CFG_WARNSEL_DEFAULT ( _WDOG_CFG_WARNSEL_DEFAULT << 24)
#define WDOG_CFG_WARNSEL_DIS ( _WDOG_CFG_WARNSEL_DIS << 24)
#define WDOG_CFG_WARNSEL_SEL1 ( _WDOG_CFG_WARNSEL_SEL1 << 24)
#define WDOG_CFG_WARNSEL_SEL2 ( _WDOG_CFG_WARNSEL_SEL2 << 24)
#define WDOG_CFG_WARNSEL_SEL3 ( _WDOG_CFG_WARNSEL_SEL3 << 24)
#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8)
#define WDOG_CFG_WDOGRSTDIS_DEFAULT ( _WDOG_CFG_WDOGRSTDIS_DEFAULT << 8)
#define WDOG_CFG_WDOGRSTDIS_DIS ( _WDOG_CFG_WDOGRSTDIS_DIS << 8)
#define WDOG_CFG_WDOGRSTDIS_EN ( _WDOG_CFG_WDOGRSTDIS_EN << 8)
#define WDOG_CFG_WINSEL_DEFAULT ( _WDOG_CFG_WINSEL_DEFAULT << 28)
#define WDOG_CFG_WINSEL_DIS ( _WDOG_CFG_WINSEL_DIS << 28)
#define WDOG_CFG_WINSEL_SEL1 ( _WDOG_CFG_WINSEL_SEL1 << 28)
#define WDOG_CFG_WINSEL_SEL2 ( _WDOG_CFG_WINSEL_SEL2 << 28)
#define WDOG_CFG_WINSEL_SEL3 ( _WDOG_CFG_WINSEL_SEL3 << 28)
#define WDOG_CFG_WINSEL_SEL4 ( _WDOG_CFG_WINSEL_SEL4 << 28)
#define WDOG_CFG_WINSEL_SEL5 ( _WDOG_CFG_WINSEL_SEL5 << 28)
#define WDOG_CFG_WINSEL_SEL6 ( _WDOG_CFG_WINSEL_SEL6 << 28)
#define WDOG_CFG_WINSEL_SEL7 ( _WDOG_CFG_WINSEL_SEL7 << 28)
#define WDOG_CMD_CLEAR (0x1UL << 0)
#define WDOG_CMD_CLEAR_CLEARED ( _WDOG_CMD_CLEAR_CLEARED << 0)
#define WDOG_CMD_CLEAR_DEFAULT ( _WDOG_CMD_CLEAR_DEFAULT << 0)
#define WDOG_CMD_CLEAR_UNCHANGED ( _WDOG_CMD_CLEAR_UNCHANGED << 0)
#define WDOG_EN_EN (0x1UL << 0)
#define WDOG_EN_EN_DEFAULT ( _WDOG_EN_EN_DEFAULT << 0)
#define WDOG_IEN_PEM0 (0x1UL << 3)
#define WDOG_IEN_PEM0_DEFAULT ( _WDOG_IEN_PEM0_DEFAULT << 3)
#define WDOG_IEN_PEM1 (0x1UL << 4)
#define WDOG_IEN_PEM1_DEFAULT ( _WDOG_IEN_PEM1_DEFAULT << 4)
#define WDOG_IEN_TOUT (0x1UL << 0)
#define WDOG_IEN_TOUT_DEFAULT ( _WDOG_IEN_TOUT_DEFAULT << 0)
#define WDOG_IEN_WARN (0x1UL << 1)
#define WDOG_IEN_WARN_DEFAULT ( _WDOG_IEN_WARN_DEFAULT << 1)
#define WDOG_IEN_WIN (0x1UL << 2)
#define WDOG_IEN_WIN_DEFAULT ( _WDOG_IEN_WIN_DEFAULT << 2)
#define WDOG_IF_PEM0 (0x1UL << 3)
#define WDOG_IF_PEM0_DEFAULT ( _WDOG_IF_PEM0_DEFAULT << 3)
#define WDOG_IF_PEM1 (0x1UL << 4)
#define WDOG_IF_PEM1_DEFAULT ( _WDOG_IF_PEM1_DEFAULT << 4)
#define WDOG_IF_TOUT (0x1UL << 0)
#define WDOG_IF_TOUT_DEFAULT ( _WDOG_IF_TOUT_DEFAULT << 0)
#define WDOG_IF_WARN (0x1UL << 1)
#define WDOG_IF_WARN_DEFAULT ( _WDOG_IF_WARN_DEFAULT << 1)
#define WDOG_IF_WIN (0x1UL << 2)
#define WDOG_IF_WIN_DEFAULT ( _WDOG_IF_WIN_DEFAULT << 2)
#define WDOG_IPVERSION_IPVERSION_DEFAULT ( _WDOG_IPVERSION_IPVERSION_DEFAULT << 0)
#define WDOG_LOCK_LOCKKEY_DEFAULT ( _WDOG_LOCK_LOCKKEY_DEFAULT << 0)
#define WDOG_LOCK_LOCKKEY_LOCK ( _WDOG_LOCK_LOCKKEY_LOCK << 0)
#define WDOG_LOCK_LOCKKEY_UNLOCK ( _WDOG_LOCK_LOCKKEY_UNLOCK << 0)
#define WDOG_STATUS_LOCK (0x1UL << 31)
#define WDOG_STATUS_LOCK_DEFAULT ( _WDOG_STATUS_LOCK_DEFAULT << 31)
#define WDOG_STATUS_LOCK_LOCKED ( _WDOG_STATUS_LOCK_LOCKED << 31)
#define WDOG_STATUS_LOCK_UNLOCKED ( _WDOG_STATUS_LOCK_UNLOCKED << 31)
#define WDOG_SYNCBUSY_CMD (0x1UL << 0)
#define WDOG_SYNCBUSY_CMD_DEFAULT ( _WDOG_SYNCBUSY_CMD_DEFAULT << 0)

Macro Definition Documentation

#define _WDOG_CFG_CLRSRC_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 125 of file efr32mg21_wdog.h .

#define _WDOG_CFG_CLRSRC_MASK   0x1UL

Bit mask for WDOG_CLRSRC

Definition at line 124 of file efr32mg21_wdog.h .

#define _WDOG_CFG_CLRSRC_PRSSRC0   0x00000001UL

Mode PRSSRC0 for WDOG_CFG

Definition at line 127 of file efr32mg21_wdog.h .

#define _WDOG_CFG_CLRSRC_SHIFT   0

Shift value for WDOG_CLRSRC

Definition at line 123 of file efr32mg21_wdog.h .

#define _WDOG_CFG_CLRSRC_SW   0x00000000UL

Mode SW for WDOG_CFG

Definition at line 126 of file efr32mg21_wdog.h .

#define _WDOG_CFG_DEBUGRUN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 161 of file efr32mg21_wdog.h .

#define _WDOG_CFG_DEBUGRUN_DISABLE   0x00000000UL

Mode DISABLE for WDOG_CFG

Definition at line 162 of file efr32mg21_wdog.h .

#define _WDOG_CFG_DEBUGRUN_ENABLE   0x00000001UL

Mode ENABLE for WDOG_CFG

Definition at line 163 of file efr32mg21_wdog.h .

#define _WDOG_CFG_DEBUGRUN_MASK   0x10UL

Bit mask for WDOG_DEBUGRUN

Definition at line 160 of file efr32mg21_wdog.h .

#define _WDOG_CFG_DEBUGRUN_SHIFT   4

Shift value for WDOG_DEBUGRUN

Definition at line 159 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM2RUN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 134 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM2RUN_DISABLE   0x00000000UL

Mode DISABLE for WDOG_CFG

Definition at line 135 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM2RUN_ENABLE   0x00000001UL

Mode ENABLE for WDOG_CFG

Definition at line 136 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM2RUN_MASK   0x2UL

Bit mask for WDOG_EM2RUN

Definition at line 133 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM2RUN_SHIFT   1

Shift value for WDOG_EM2RUN

Definition at line 132 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM3RUN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 143 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM3RUN_DISABLE   0x00000000UL

Mode DISABLE for WDOG_CFG

Definition at line 144 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM3RUN_ENABLE   0x00000001UL

Mode ENABLE for WDOG_CFG

Definition at line 145 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM3RUN_MASK   0x4UL

Bit mask for WDOG_EM3RUN

Definition at line 142 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM3RUN_SHIFT   2

Shift value for WDOG_EM3RUN

Definition at line 141 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM4BLOCK_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 152 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM4BLOCK_DISABLE   0x00000000UL

Mode DISABLE for WDOG_CFG

Definition at line 153 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM4BLOCK_ENABLE   0x00000001UL

Mode ENABLE for WDOG_CFG

Definition at line 154 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM4BLOCK_MASK   0x8UL

Bit mask for WDOG_EM4BLOCK

Definition at line 151 of file efr32mg21_wdog.h .

#define _WDOG_CFG_EM4BLOCK_SHIFT   3

Shift value for WDOG_EM4BLOCK

Definition at line 150 of file efr32mg21_wdog.h .

#define _WDOG_CFG_MASK   0x730F071FUL

Mask for WDOG_CFG

Definition at line 121 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_DEFAULT   0x0000000FUL

Mode DEFAULT for WDOG_CFG

Definition at line 188 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_MASK   0xF0000UL

Bit mask for WDOG_PERSEL

Definition at line 187 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL0   0x00000000UL

Mode SEL0 for WDOG_CFG

Definition at line 189 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL1   0x00000001UL

Mode SEL1 for WDOG_CFG

Definition at line 190 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL10   0x0000000AUL

Mode SEL10 for WDOG_CFG

Definition at line 199 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL11   0x0000000BUL

Mode SEL11 for WDOG_CFG

Definition at line 200 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL12   0x0000000CUL

Mode SEL12 for WDOG_CFG

Definition at line 201 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL13   0x0000000DUL

Mode SEL13 for WDOG_CFG

Definition at line 202 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL14   0x0000000EUL

Mode SEL14 for WDOG_CFG

Definition at line 203 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL15   0x0000000FUL

Mode SEL15 for WDOG_CFG

Definition at line 204 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL2   0x00000002UL

Mode SEL2 for WDOG_CFG

Definition at line 191 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL3   0x00000003UL

Mode SEL3 for WDOG_CFG

Definition at line 192 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL4   0x00000004UL

Mode SEL4 for WDOG_CFG

Definition at line 193 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL5   0x00000005UL

Mode SEL5 for WDOG_CFG

Definition at line 194 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL6   0x00000006UL

Mode SEL6 for WDOG_CFG

Definition at line 195 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL7   0x00000007UL

Mode SEL7 for WDOG_CFG

Definition at line 196 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL8   0x00000008UL

Mode SEL8 for WDOG_CFG

Definition at line 197 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SEL9   0x00000009UL

Mode SEL9 for WDOG_CFG

Definition at line 198 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PERSEL_SHIFT   16

Shift value for WDOG_PERSEL

Definition at line 186 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 179 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PRS0MISSRSTEN_MASK   0x200UL

Bit mask for WDOG_PRS0MISSRSTEN

Definition at line 178 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT   9

Shift value for WDOG_PRS0MISSRSTEN

Definition at line 177 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 184 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PRS1MISSRSTEN_MASK   0x400UL

Bit mask for WDOG_PRS1MISSRSTEN

Definition at line 183 of file efr32mg21_wdog.h .

#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT   10

Shift value for WDOG_PRS1MISSRSTEN

Definition at line 182 of file efr32mg21_wdog.h .

#define _WDOG_CFG_RESETVALUE   0x000F0000UL

Default value for WDOG_CFG

Definition at line 120 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WARNSEL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 224 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WARNSEL_DIS   0x00000000UL

Mode DIS for WDOG_CFG

Definition at line 225 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WARNSEL_MASK   0x3000000UL

Bit mask for WDOG_WARNSEL

Definition at line 223 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WARNSEL_SEL1   0x00000001UL

Mode SEL1 for WDOG_CFG

Definition at line 226 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WARNSEL_SEL2   0x00000002UL

Mode SEL2 for WDOG_CFG

Definition at line 227 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WARNSEL_SEL3   0x00000003UL

Mode SEL3 for WDOG_CFG

Definition at line 228 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WARNSEL_SHIFT   24

Shift value for WDOG_WARNSEL

Definition at line 222 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CFG_WDOGRSTDIS_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 170 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WDOGRSTDIS_DIS   0x00000001UL

Mode DIS for WDOG_CFG

Definition at line 172 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WDOGRSTDIS_EN   0x00000000UL

Mode EN for WDOG_CFG

Definition at line 171 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WDOGRSTDIS_MASK   0x100UL

Bit mask for WDOG_WDOGRSTDIS

Definition at line 169 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WDOGRSTDIS_SHIFT   8

Shift value for WDOG_WDOGRSTDIS

Definition at line 168 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CFG

Definition at line 236 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_DIS   0x00000000UL

Mode DIS for WDOG_CFG

Definition at line 237 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_MASK   0x70000000UL

Bit mask for WDOG_WINSEL

Definition at line 235 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SEL1   0x00000001UL

Mode SEL1 for WDOG_CFG

Definition at line 238 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SEL2   0x00000002UL

Mode SEL2 for WDOG_CFG

Definition at line 239 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SEL3   0x00000003UL

Mode SEL3 for WDOG_CFG

Definition at line 240 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SEL4   0x00000004UL

Mode SEL4 for WDOG_CFG

Definition at line 241 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SEL5   0x00000005UL

Mode SEL5 for WDOG_CFG

Definition at line 242 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SEL6   0x00000006UL

Mode SEL6 for WDOG_CFG

Definition at line 243 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SEL7   0x00000007UL

Mode SEL7 for WDOG_CFG

Definition at line 244 of file efr32mg21_wdog.h .

#define _WDOG_CFG_WINSEL_SHIFT   28

Shift value for WDOG_WINSEL

Definition at line 234 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define _WDOG_CMD_CLEAR_CLEARED   0x00000001UL

Mode CLEARED for WDOG_CMD

Definition at line 263 of file efr32mg21_wdog.h .

#define _WDOG_CMD_CLEAR_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_CMD

Definition at line 261 of file efr32mg21_wdog.h .

#define _WDOG_CMD_CLEAR_MASK   0x1UL

Bit mask for WDOG_CLEAR

Definition at line 260 of file efr32mg21_wdog.h .

#define _WDOG_CMD_CLEAR_SHIFT   0

Shift value for WDOG_CLEAR

Definition at line 259 of file efr32mg21_wdog.h .

#define _WDOG_CMD_CLEAR_UNCHANGED   0x00000000UL

Mode UNCHANGED for WDOG_CMD

Definition at line 262 of file efr32mg21_wdog.h .

#define _WDOG_CMD_MASK   0x00000001UL

Mask for WDOG_CMD

Definition at line 257 of file efr32mg21_wdog.h .

#define _WDOG_CMD_RESETVALUE   0x00000000UL

Default value for WDOG_CMD

Definition at line 256 of file efr32mg21_wdog.h .

#define _WDOG_EN_EN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_EN

Definition at line 116 of file efr32mg21_wdog.h .

#define _WDOG_EN_EN_MASK   0x1UL

Bit mask for WDOG_EN

Definition at line 115 of file efr32mg21_wdog.h .

Referenced by WDOGn_IsEnabled() .

#define _WDOG_EN_EN_SHIFT   0

Shift value for WDOG_EN

Definition at line 114 of file efr32mg21_wdog.h .

#define _WDOG_EN_MASK   0x00000001UL

Mask for WDOG_EN

Definition at line 112 of file efr32mg21_wdog.h .

#define _WDOG_EN_RESETVALUE   0x00000000UL

Default value for WDOG_EN

Definition at line 111 of file efr32mg21_wdog.h .

#define _WDOG_IEN_MASK   0x0000001FUL

Mask for WDOG_IEN

Definition at line 312 of file efr32mg21_wdog.h .

#define _WDOG_IEN_PEM0_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 331 of file efr32mg21_wdog.h .

#define _WDOG_IEN_PEM0_MASK   0x8UL

Bit mask for WDOG_PEM0

Definition at line 330 of file efr32mg21_wdog.h .

#define _WDOG_IEN_PEM0_SHIFT   3

Shift value for WDOG_PEM0

Definition at line 329 of file efr32mg21_wdog.h .

#define _WDOG_IEN_PEM1_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 336 of file efr32mg21_wdog.h .

#define _WDOG_IEN_PEM1_MASK   0x10UL

Bit mask for WDOG_PEM1

Definition at line 335 of file efr32mg21_wdog.h .

#define _WDOG_IEN_PEM1_SHIFT   4

Shift value for WDOG_PEM1

Definition at line 334 of file efr32mg21_wdog.h .

#define _WDOG_IEN_RESETVALUE   0x00000000UL

Default value for WDOG_IEN

Definition at line 311 of file efr32mg21_wdog.h .

#define _WDOG_IEN_TOUT_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 316 of file efr32mg21_wdog.h .

#define _WDOG_IEN_TOUT_MASK   0x1UL

Bit mask for WDOG_TOUT

Definition at line 315 of file efr32mg21_wdog.h .

#define _WDOG_IEN_TOUT_SHIFT   0

Shift value for WDOG_TOUT

Definition at line 314 of file efr32mg21_wdog.h .

#define _WDOG_IEN_WARN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 321 of file efr32mg21_wdog.h .

#define _WDOG_IEN_WARN_MASK   0x2UL

Bit mask for WDOG_WARN

Definition at line 320 of file efr32mg21_wdog.h .

#define _WDOG_IEN_WARN_SHIFT   1

Shift value for WDOG_WARN

Definition at line 319 of file efr32mg21_wdog.h .

#define _WDOG_IEN_WIN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IEN

Definition at line 326 of file efr32mg21_wdog.h .

#define _WDOG_IEN_WIN_MASK   0x4UL

Bit mask for WDOG_WIN

Definition at line 325 of file efr32mg21_wdog.h .

#define _WDOG_IEN_WIN_SHIFT   2

Shift value for WDOG_WIN

Definition at line 324 of file efr32mg21_wdog.h .

#define _WDOG_IF_MASK   0x0000001FUL

Mask for WDOG_IF

Definition at line 283 of file efr32mg21_wdog.h .

#define _WDOG_IF_PEM0_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 302 of file efr32mg21_wdog.h .

#define _WDOG_IF_PEM0_MASK   0x8UL

Bit mask for WDOG_PEM0

Definition at line 301 of file efr32mg21_wdog.h .

#define _WDOG_IF_PEM0_SHIFT   3

Shift value for WDOG_PEM0

Definition at line 300 of file efr32mg21_wdog.h .

#define _WDOG_IF_PEM1_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 307 of file efr32mg21_wdog.h .

#define _WDOG_IF_PEM1_MASK   0x10UL

Bit mask for WDOG_PEM1

Definition at line 306 of file efr32mg21_wdog.h .

#define _WDOG_IF_PEM1_SHIFT   4

Shift value for WDOG_PEM1

Definition at line 305 of file efr32mg21_wdog.h .

#define _WDOG_IF_RESETVALUE   0x00000000UL

Default value for WDOG_IF

Definition at line 282 of file efr32mg21_wdog.h .

#define _WDOG_IF_TOUT_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 287 of file efr32mg21_wdog.h .

#define _WDOG_IF_TOUT_MASK   0x1UL

Bit mask for WDOG_TOUT

Definition at line 286 of file efr32mg21_wdog.h .

#define _WDOG_IF_TOUT_SHIFT   0

Shift value for WDOG_TOUT

Definition at line 285 of file efr32mg21_wdog.h .

#define _WDOG_IF_WARN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 292 of file efr32mg21_wdog.h .

#define _WDOG_IF_WARN_MASK   0x2UL

Bit mask for WDOG_WARN

Definition at line 291 of file efr32mg21_wdog.h .

#define _WDOG_IF_WARN_SHIFT   1

Shift value for WDOG_WARN

Definition at line 290 of file efr32mg21_wdog.h .

#define _WDOG_IF_WIN_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IF

Definition at line 297 of file efr32mg21_wdog.h .

#define _WDOG_IF_WIN_MASK   0x4UL

Bit mask for WDOG_WIN

Definition at line 296 of file efr32mg21_wdog.h .

#define _WDOG_IF_WIN_SHIFT   2

Shift value for WDOG_WIN

Definition at line 295 of file efr32mg21_wdog.h .

#define _WDOG_IPVERSION_IPVERSION_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_IPVERSION

Definition at line 107 of file efr32mg21_wdog.h .

#define _WDOG_IPVERSION_IPVERSION_MASK   0xFFFFFFFFUL

Bit mask for WDOG_IPVERSION

Definition at line 106 of file efr32mg21_wdog.h .

#define _WDOG_IPVERSION_IPVERSION_SHIFT   0

Shift value for WDOG_IPVERSION

Definition at line 105 of file efr32mg21_wdog.h .

#define _WDOG_IPVERSION_MASK   0xFFFFFFFFUL

Mask for WDOG_IPVERSION

Definition at line 104 of file efr32mg21_wdog.h .

#define _WDOG_IPVERSION_RESETVALUE   0x00000000UL

Default value for WDOG_IPVERSION

Definition at line 103 of file efr32mg21_wdog.h .

#define _WDOG_LOCK_LOCKKEY_DEFAULT   0x0000ABE8UL

Mode DEFAULT for WDOG_LOCK

Definition at line 344 of file efr32mg21_wdog.h .

#define _WDOG_LOCK_LOCKKEY_LOCK   0x00000000UL

Mode LOCK for WDOG_LOCK

Definition at line 345 of file efr32mg21_wdog.h .

Referenced by WDOGn_Lock() .

#define _WDOG_LOCK_LOCKKEY_MASK   0xFFFFUL

Bit mask for WDOG_LOCKKEY

Definition at line 343 of file efr32mg21_wdog.h .

#define _WDOG_LOCK_LOCKKEY_SHIFT   0

Shift value for WDOG_LOCKKEY

Definition at line 342 of file efr32mg21_wdog.h .

#define _WDOG_LOCK_LOCKKEY_UNLOCK   0x0000ABE8UL

Mode UNLOCK for WDOG_LOCK

Definition at line 346 of file efr32mg21_wdog.h .

Referenced by WDOGn_Unlock() .

#define _WDOG_LOCK_MASK   0x0000FFFFUL

Mask for WDOG_LOCK

Definition at line 341 of file efr32mg21_wdog.h .

#define _WDOG_LOCK_RESETVALUE   0x0000ABE8UL

Default value for WDOG_LOCK

Definition at line 340 of file efr32mg21_wdog.h .

#define _WDOG_STATUS_LOCK_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_STATUS

Definition at line 274 of file efr32mg21_wdog.h .

#define _WDOG_STATUS_LOCK_LOCKED   0x00000001UL

Mode LOCKED for WDOG_STATUS

Definition at line 276 of file efr32mg21_wdog.h .

#define _WDOG_STATUS_LOCK_MASK   0x80000000UL

Bit mask for WDOG_LOCK

Definition at line 273 of file efr32mg21_wdog.h .

Referenced by WDOGn_Enable() , and WDOGn_IsLocked() .

#define _WDOG_STATUS_LOCK_SHIFT   31

Shift value for WDOG_LOCK

Definition at line 272 of file efr32mg21_wdog.h .

#define _WDOG_STATUS_LOCK_UNLOCKED   0x00000000UL

Mode UNLOCKED for WDOG_STATUS

Definition at line 275 of file efr32mg21_wdog.h .

#define _WDOG_STATUS_MASK   0x80000000UL

Mask for WDOG_STATUS

Definition at line 270 of file efr32mg21_wdog.h .

#define _WDOG_STATUS_RESETVALUE   0x00000000UL

Default value for WDOG_STATUS

Definition at line 269 of file efr32mg21_wdog.h .

#define _WDOG_SYNCBUSY_CMD_DEFAULT   0x00000000UL

Mode DEFAULT for WDOG_SYNCBUSY

Definition at line 357 of file efr32mg21_wdog.h .

#define _WDOG_SYNCBUSY_CMD_MASK   0x1UL

Bit mask for WDOG_CMD

Definition at line 356 of file efr32mg21_wdog.h .

#define _WDOG_SYNCBUSY_CMD_SHIFT   0

Shift value for WDOG_CMD

Definition at line 355 of file efr32mg21_wdog.h .

#define _WDOG_SYNCBUSY_MASK   0x00000001UL

Mask for WDOG_SYNCBUSY

Definition at line 353 of file efr32mg21_wdog.h .

#define _WDOG_SYNCBUSY_RESETVALUE   0x00000000UL

Default value for WDOG_SYNCBUSY

Definition at line 352 of file efr32mg21_wdog.h .

#define WDOG_CFG_CLRSRC   (0x1UL << 0)

WDOG Clear Source

Definition at line 122 of file efr32mg21_wdog.h .

#define WDOG_CFG_CLRSRC_DEFAULT   ( _WDOG_CFG_CLRSRC_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 128 of file efr32mg21_wdog.h .

#define WDOG_CFG_CLRSRC_PRSSRC0   ( _WDOG_CFG_CLRSRC_PRSSRC0 << 0)

Shifted mode PRSSRC0 for WDOG_CFG

Definition at line 130 of file efr32mg21_wdog.h .

#define WDOG_CFG_CLRSRC_SW   ( _WDOG_CFG_CLRSRC_SW << 0)

Shifted mode SW for WDOG_CFG

Definition at line 129 of file efr32mg21_wdog.h .

#define WDOG_CFG_DEBUGRUN   (0x1UL << 4)

Debug Mode Run

Definition at line 158 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CFG_DEBUGRUN_DEFAULT   ( _WDOG_CFG_DEBUGRUN_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 164 of file efr32mg21_wdog.h .

#define WDOG_CFG_DEBUGRUN_DISABLE   ( _WDOG_CFG_DEBUGRUN_DISABLE << 4)

Shifted mode DISABLE for WDOG_CFG

Definition at line 165 of file efr32mg21_wdog.h .

#define WDOG_CFG_DEBUGRUN_ENABLE   ( _WDOG_CFG_DEBUGRUN_ENABLE << 4)

Shifted mode ENABLE for WDOG_CFG

Definition at line 166 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM2RUN   (0x1UL << 1)

EM2 Run

Definition at line 131 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CFG_EM2RUN_DEFAULT   ( _WDOG_CFG_EM2RUN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 137 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM2RUN_DISABLE   ( _WDOG_CFG_EM2RUN_DISABLE << 1)

Shifted mode DISABLE for WDOG_CFG

Definition at line 138 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM2RUN_ENABLE   ( _WDOG_CFG_EM2RUN_ENABLE << 1)

Shifted mode ENABLE for WDOG_CFG

Definition at line 139 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM3RUN   (0x1UL << 2)

EM3 Run

Definition at line 140 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CFG_EM3RUN_DEFAULT   ( _WDOG_CFG_EM3RUN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 146 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM3RUN_DISABLE   ( _WDOG_CFG_EM3RUN_DISABLE << 2)

Shifted mode DISABLE for WDOG_CFG

Definition at line 147 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM3RUN_ENABLE   ( _WDOG_CFG_EM3RUN_ENABLE << 2)

Shifted mode ENABLE for WDOG_CFG

Definition at line 148 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM4BLOCK   (0x1UL << 3)

EM4 Block

Definition at line 149 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CFG_EM4BLOCK_DEFAULT   ( _WDOG_CFG_EM4BLOCK_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 155 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM4BLOCK_DISABLE   ( _WDOG_CFG_EM4BLOCK_DISABLE << 3)

Shifted mode DISABLE for WDOG_CFG

Definition at line 156 of file efr32mg21_wdog.h .

#define WDOG_CFG_EM4BLOCK_ENABLE   ( _WDOG_CFG_EM4BLOCK_ENABLE << 3)

Shifted mode ENABLE for WDOG_CFG

Definition at line 157 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_DEFAULT   ( _WDOG_CFG_PERSEL_DEFAULT << 16)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 205 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL0   ( _WDOG_CFG_PERSEL_SEL0 << 16)

Shifted mode SEL0 for WDOG_CFG

Definition at line 206 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL1   ( _WDOG_CFG_PERSEL_SEL1 << 16)

Shifted mode SEL1 for WDOG_CFG

Definition at line 207 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL10   ( _WDOG_CFG_PERSEL_SEL10 << 16)

Shifted mode SEL10 for WDOG_CFG

Definition at line 216 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL11   ( _WDOG_CFG_PERSEL_SEL11 << 16)

Shifted mode SEL11 for WDOG_CFG

Definition at line 217 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL12   ( _WDOG_CFG_PERSEL_SEL12 << 16)

Shifted mode SEL12 for WDOG_CFG

Definition at line 218 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL13   ( _WDOG_CFG_PERSEL_SEL13 << 16)

Shifted mode SEL13 for WDOG_CFG

Definition at line 219 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL14   ( _WDOG_CFG_PERSEL_SEL14 << 16)

Shifted mode SEL14 for WDOG_CFG

Definition at line 220 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL15   ( _WDOG_CFG_PERSEL_SEL15 << 16)

Shifted mode SEL15 for WDOG_CFG

Definition at line 221 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL2   ( _WDOG_CFG_PERSEL_SEL2 << 16)

Shifted mode SEL2 for WDOG_CFG

Definition at line 208 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL3   ( _WDOG_CFG_PERSEL_SEL3 << 16)

Shifted mode SEL3 for WDOG_CFG

Definition at line 209 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL4   ( _WDOG_CFG_PERSEL_SEL4 << 16)

Shifted mode SEL4 for WDOG_CFG

Definition at line 210 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL5   ( _WDOG_CFG_PERSEL_SEL5 << 16)

Shifted mode SEL5 for WDOG_CFG

Definition at line 211 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL6   ( _WDOG_CFG_PERSEL_SEL6 << 16)

Shifted mode SEL6 for WDOG_CFG

Definition at line 212 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL7   ( _WDOG_CFG_PERSEL_SEL7 << 16)

Shifted mode SEL7 for WDOG_CFG

Definition at line 213 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL8   ( _WDOG_CFG_PERSEL_SEL8 << 16)

Shifted mode SEL8 for WDOG_CFG

Definition at line 214 of file efr32mg21_wdog.h .

#define WDOG_CFG_PERSEL_SEL9   ( _WDOG_CFG_PERSEL_SEL9 << 16)

Shifted mode SEL9 for WDOG_CFG

Definition at line 215 of file efr32mg21_wdog.h .

#define WDOG_CFG_PRS0MISSRSTEN   (0x1UL << 9)

PRS Src0 Missing Event WDOG Reset

Definition at line 176 of file efr32mg21_wdog.h .

#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT   ( _WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 180 of file efr32mg21_wdog.h .

#define WDOG_CFG_PRS1MISSRSTEN   (0x1UL << 10)

PRS Src1 Missing Event WDOG Reset

Definition at line 181 of file efr32mg21_wdog.h .

#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT   ( _WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 185 of file efr32mg21_wdog.h .

#define WDOG_CFG_WARNSEL_DEFAULT   ( _WDOG_CFG_WARNSEL_DEFAULT << 24)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 229 of file efr32mg21_wdog.h .

#define WDOG_CFG_WARNSEL_DIS   ( _WDOG_CFG_WARNSEL_DIS << 24)

Shifted mode DIS for WDOG_CFG

Definition at line 230 of file efr32mg21_wdog.h .

#define WDOG_CFG_WARNSEL_SEL1   ( _WDOG_CFG_WARNSEL_SEL1 << 24)

Shifted mode SEL1 for WDOG_CFG

Definition at line 231 of file efr32mg21_wdog.h .

#define WDOG_CFG_WARNSEL_SEL2   ( _WDOG_CFG_WARNSEL_SEL2 << 24)

Shifted mode SEL2 for WDOG_CFG

Definition at line 232 of file efr32mg21_wdog.h .

#define WDOG_CFG_WARNSEL_SEL3   ( _WDOG_CFG_WARNSEL_SEL3 << 24)

Shifted mode SEL3 for WDOG_CFG

Definition at line 233 of file efr32mg21_wdog.h .

#define WDOG_CFG_WDOGRSTDIS   (0x1UL << 8)

WDOG Reset Disable

Definition at line 167 of file efr32mg21_wdog.h .

Referenced by WDOGn_Init() .

#define WDOG_CFG_WDOGRSTDIS_DEFAULT   ( _WDOG_CFG_WDOGRSTDIS_DEFAULT << 8)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 173 of file efr32mg21_wdog.h .

#define WDOG_CFG_WDOGRSTDIS_DIS   ( _WDOG_CFG_WDOGRSTDIS_DIS << 8)

Shifted mode DIS for WDOG_CFG

Definition at line 175 of file efr32mg21_wdog.h .

#define WDOG_CFG_WDOGRSTDIS_EN   ( _WDOG_CFG_WDOGRSTDIS_EN << 8)

Shifted mode EN for WDOG_CFG

Definition at line 174 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_DEFAULT   ( _WDOG_CFG_WINSEL_DEFAULT << 28)

Shifted mode DEFAULT for WDOG_CFG

Definition at line 245 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_DIS   ( _WDOG_CFG_WINSEL_DIS << 28)

Shifted mode DIS for WDOG_CFG

Definition at line 246 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_SEL1   ( _WDOG_CFG_WINSEL_SEL1 << 28)

Shifted mode SEL1 for WDOG_CFG

Definition at line 247 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_SEL2   ( _WDOG_CFG_WINSEL_SEL2 << 28)

Shifted mode SEL2 for WDOG_CFG

Definition at line 248 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_SEL3   ( _WDOG_CFG_WINSEL_SEL3 << 28)

Shifted mode SEL3 for WDOG_CFG

Definition at line 249 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_SEL4   ( _WDOG_CFG_WINSEL_SEL4 << 28)

Shifted mode SEL4 for WDOG_CFG

Definition at line 250 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_SEL5   ( _WDOG_CFG_WINSEL_SEL5 << 28)

Shifted mode SEL5 for WDOG_CFG

Definition at line 251 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_SEL6   ( _WDOG_CFG_WINSEL_SEL6 << 28)

Shifted mode SEL6 for WDOG_CFG

Definition at line 252 of file efr32mg21_wdog.h .

#define WDOG_CFG_WINSEL_SEL7   ( _WDOG_CFG_WINSEL_SEL7 << 28)

Shifted mode SEL7 for WDOG_CFG

Definition at line 253 of file efr32mg21_wdog.h .

#define WDOG_CMD_CLEAR   (0x1UL << 0)

WDOG Timer Clear

Definition at line 258 of file efr32mg21_wdog.h .

Referenced by WDOGn_Feed() .

#define WDOG_CMD_CLEAR_CLEARED   ( _WDOG_CMD_CLEAR_CLEARED << 0)

Shifted mode CLEARED for WDOG_CMD

Definition at line 266 of file efr32mg21_wdog.h .

#define WDOG_CMD_CLEAR_DEFAULT   ( _WDOG_CMD_CLEAR_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_CMD

Definition at line 264 of file efr32mg21_wdog.h .

#define WDOG_CMD_CLEAR_UNCHANGED   ( _WDOG_CMD_CLEAR_UNCHANGED << 0)

Shifted mode UNCHANGED for WDOG_CMD

Definition at line 265 of file efr32mg21_wdog.h .

#define WDOG_EN_EN   (0x1UL << 0)

Module Enable

Definition at line 113 of file efr32mg21_wdog.h .

Referenced by WDOGn_Enable() , WDOGn_Feed() , WDOGn_Init() , and WDOGn_IsEnabled() .

#define WDOG_EN_EN_DEFAULT   ( _WDOG_EN_EN_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_EN

Definition at line 117 of file efr32mg21_wdog.h .

#define WDOG_IEN_PEM0   (0x1UL << 3)

PRS Src0 Event Missing Interrupt Enable

Definition at line 328 of file efr32mg21_wdog.h .

#define WDOG_IEN_PEM0_DEFAULT   ( _WDOG_IEN_PEM0_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 332 of file efr32mg21_wdog.h .

#define WDOG_IEN_PEM1   (0x1UL << 4)

PRS Src1 Event Missing Interrupt Enable

Definition at line 333 of file efr32mg21_wdog.h .

#define WDOG_IEN_PEM1_DEFAULT   ( _WDOG_IEN_PEM1_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 337 of file efr32mg21_wdog.h .

#define WDOG_IEN_TOUT   (0x1UL << 0)

WDOG Timeout Interrupt Enable

Definition at line 313 of file efr32mg21_wdog.h .

#define WDOG_IEN_TOUT_DEFAULT   ( _WDOG_IEN_TOUT_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 317 of file efr32mg21_wdog.h .

#define WDOG_IEN_WARN   (0x1UL << 1)

WDOG Warning Timeout Interrupt Enable

Definition at line 318 of file efr32mg21_wdog.h .

#define WDOG_IEN_WARN_DEFAULT   ( _WDOG_IEN_WARN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 322 of file efr32mg21_wdog.h .

#define WDOG_IEN_WIN   (0x1UL << 2)

WDOG Window Interrupt Enable

Definition at line 323 of file efr32mg21_wdog.h .

#define WDOG_IEN_WIN_DEFAULT   ( _WDOG_IEN_WIN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_IEN

Definition at line 327 of file efr32mg21_wdog.h .

#define WDOG_IF_PEM0   (0x1UL << 3)

PRS Src0 Event Missing Interrupt Flag

Definition at line 299 of file efr32mg21_wdog.h .

#define WDOG_IF_PEM0_DEFAULT   ( _WDOG_IF_PEM0_DEFAULT << 3)

Shifted mode DEFAULT for WDOG_IF

Definition at line 303 of file efr32mg21_wdog.h .

#define WDOG_IF_PEM1   (0x1UL << 4)

PRS Src1 Event Missing Interrupt Flag

Definition at line 304 of file efr32mg21_wdog.h .

#define WDOG_IF_PEM1_DEFAULT   ( _WDOG_IF_PEM1_DEFAULT << 4)

Shifted mode DEFAULT for WDOG_IF

Definition at line 308 of file efr32mg21_wdog.h .

#define WDOG_IF_TOUT   (0x1UL << 0)

WDOG Timeout Interrupt Flag

Definition at line 284 of file efr32mg21_wdog.h .

#define WDOG_IF_TOUT_DEFAULT   ( _WDOG_IF_TOUT_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_IF

Definition at line 288 of file efr32mg21_wdog.h .

#define WDOG_IF_WARN   (0x1UL << 1)

WDOG Warning Timeout Interrupt Flag

Definition at line 289 of file efr32mg21_wdog.h .

#define WDOG_IF_WARN_DEFAULT   ( _WDOG_IF_WARN_DEFAULT << 1)

Shifted mode DEFAULT for WDOG_IF

Definition at line 293 of file efr32mg21_wdog.h .

#define WDOG_IF_WIN   (0x1UL << 2)

WDOG Window Interrupt Flag

Definition at line 294 of file efr32mg21_wdog.h .

#define WDOG_IF_WIN_DEFAULT   ( _WDOG_IF_WIN_DEFAULT << 2)

Shifted mode DEFAULT for WDOG_IF

Definition at line 298 of file efr32mg21_wdog.h .

#define WDOG_IPVERSION_IPVERSION_DEFAULT   ( _WDOG_IPVERSION_IPVERSION_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_IPVERSION

Definition at line 108 of file efr32mg21_wdog.h .

#define WDOG_LOCK_LOCKKEY_DEFAULT   ( _WDOG_LOCK_LOCKKEY_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_LOCK

Definition at line 347 of file efr32mg21_wdog.h .

#define WDOG_LOCK_LOCKKEY_LOCK   ( _WDOG_LOCK_LOCKKEY_LOCK << 0)

Shifted mode LOCK for WDOG_LOCK

Definition at line 348 of file efr32mg21_wdog.h .

#define WDOG_LOCK_LOCKKEY_UNLOCK   ( _WDOG_LOCK_LOCKKEY_UNLOCK << 0)

Shifted mode UNLOCK for WDOG_LOCK

Definition at line 349 of file efr32mg21_wdog.h .

#define WDOG_STATUS_LOCK   (0x1UL << 31)

WDOG Configuration Lock Status

Definition at line 271 of file efr32mg21_wdog.h .

#define WDOG_STATUS_LOCK_DEFAULT   ( _WDOG_STATUS_LOCK_DEFAULT << 31)

Shifted mode DEFAULT for WDOG_STATUS

Definition at line 277 of file efr32mg21_wdog.h .

#define WDOG_STATUS_LOCK_LOCKED   ( _WDOG_STATUS_LOCK_LOCKED << 31)

Shifted mode LOCKED for WDOG_STATUS

Definition at line 279 of file efr32mg21_wdog.h .

Referenced by WDOGn_Enable() , and WDOGn_IsLocked() .

#define WDOG_STATUS_LOCK_UNLOCKED   ( _WDOG_STATUS_LOCK_UNLOCKED << 31)

Shifted mode UNLOCKED for WDOG_STATUS

Definition at line 278 of file efr32mg21_wdog.h .

#define WDOG_SYNCBUSY_CMD   (0x1UL << 0)

Sync Busy for Cmd Register

Definition at line 354 of file efr32mg21_wdog.h .

Referenced by WDOGn_Enable() , and WDOGn_Feed() .

#define WDOG_SYNCBUSY_CMD_DEFAULT   ( _WDOG_SYNCBUSY_CMD_DEFAULT << 0)

Shifted mode DEFAULT for WDOG_SYNCBUSY

Definition at line 358 of file efr32mg21_wdog.h .