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#define | ACMP(n) |
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#define | ACMP0_DAC_INPUT 0x0UL /**> None */ |
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#define | ACMP0_EXT_OVR_IF 0x0UL /**> None */ |
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#define | ACMP1_DAC_INPUT 0x0UL /**> None */ |
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#define | ACMP1_EXT_OVR_IF 0x0UL /**> None */ |
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#define | ACMP_DAC_INPUT(n) |
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#define | ACMP_EXT_OVR_IF(n) |
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#define | ACMP_NUM(ref) |
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#define | AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */ |
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#define | AGC_POWER_WIDTH 0xCUL /**> New Param */ |
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#define | AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ |
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#define | BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */ |
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#define | BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */ |
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#define | BUFC_NUMOFBUFS 0x4UL /**> New Param */ |
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#define | BUFC_NUMOFINPUTS 0x1UL /**> New Param */ |
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#define | BURTC_CNTWIDTH 0x20UL /**> None */ |
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#define | BURTC_PRECNT_WIDTH 0xFUL /**> */ |
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#define | DMEM_ADDR_OVERRIDE_BITS 0x8UL /**> Override bits for remapping */ |
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#define | DMEM_BANK0_SIZE 0x4000UL /**> Bank0 Size */ |
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#define | DMEM_BANK1_SIZE 0x4000UL /**> Bank1 Size */ |
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#define | DMEM_BANK2_SIZE 0x4000UL /**> Bank2 Size */ |
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#define | DMEM_BANK3_SIZE 0x4000UL /**> Bank3 Size */ |
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#define | DMEM_BANK4_SIZE 0x4000UL /**> Bank4 Size */ |
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#define | DMEM_BANK5_SIZE 0x4000UL /**> Bank5 Size */ |
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#define | DMEM_BANK6_SIZE 0x0UL /**> Bank6 Size */ |
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#define | DMEM_BANK7_SIZE 0x0UL /**> Bank7 Size */ |
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#define | DMEM_NUM_BANK 0x6UL /**> Number of Banks */ |
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#define | DMEM_RAM_BWE_WIDTH 0x27UL /**> Bitwise write enable */ |
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#define | DMEM_RAM_DATA_WIDTH 0x27UL /**> Data width */ |
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#define | DMEM_RAM_DIV_PRESENT 0x0UL /**> Bank0 division present */ |
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#define | DMEM_RAM_ECC_EN 0x1UL /**> RAM_ECC_EN_PRESENT */ |
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#define | DMEM_RAM_ECCADDR_WIDTH 0x20UL /**> ECC Address width */ |
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#define | DMEM_RAMADDRBITS 0x11UL /**> Total address bits */ |
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#define | DMEM_RAMADDRMINBITS 0xEUL /**> address bits for one bank */ |
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#define | FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */ |
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#define | FRC_FCD_NUM 0x4UL /**> None */ |
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#define | FRC_INTELEMENTS 0x10UL /**> None */ |
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#define | FRC_RAMADDR_WIDTH 0x10UL /**> None */ |
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#define | GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ |
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#define | GPIO_NUM_EM4_WU 0xCUL /**> New Param */ |
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#define | GPIO_NUM_EVEN_PA 0x4UL /**> Num of even pins port A */ |
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#define | GPIO_NUM_EVEN_PB 0x1UL /**> Num of even pins port B */ |
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#define | GPIO_NUM_EVEN_PC 0x3UL /**> Num of even pins port C */ |
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#define | GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ |
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#define | GPIO_NUM_EXT_INT 0x8UL /**> New Param */ |
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#define | GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ |
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#define | GPIO_NUM_EXT_INT_U 0x0UL /**> New Param */ |
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#define | GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ |
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#define | GPIO_NUM_ODD_PA 0x3UL /**> Num of odd pins port A */ |
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#define | GPIO_NUM_ODD_PB 0x1UL /**> Num of odd pins port B */ |
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#define | GPIO_NUM_ODD_PC 0x3UL /**> Num of odd pins port C */ |
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#define | GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ |
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#define | GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ |
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#define | GPIO_PORT_A_WIDTH 0x7UL /**> Port A Width */ |
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#define | GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ |
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#define | GPIO_PORT_A_WL 0x7UL /**> New Param */ |
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#define | GPIO_PORT_A_WU 0x0UL /**> New Param */ |
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#define | GPIO_PORT_A_WU_ZERO 0x1UL /**> New Param */ |
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#define | GPIO_PORT_B_WIDTH 0x2UL /**> Port B Width */ |
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#define | GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ |
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#define | GPIO_PORT_B_WL 0x2UL /**> New Param */ |
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#define | GPIO_PORT_B_WU 0x0UL /**> New Param */ |
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#define | GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ |
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#define | GPIO_PORT_C_WIDTH 0x6UL /**> Port C Width */ |
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#define | GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ |
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#define | GPIO_PORT_C_WL 0x6UL /**> New Param */ |
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#define | GPIO_PORT_C_WU 0x0UL /**> New Param */ |
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#define | GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ |
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#define | GPIO_PORT_D_WIDTH 0x5UL /**> Port D Width */ |
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#define | GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ |
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#define | GPIO_PORT_D_WL 0x5UL /**> New Param */ |
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#define | GPIO_PORT_D_WU 0x0UL /**> New Param */ |
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#define | GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ |
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#define | GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ |
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#define | GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ |
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#define | HFRCO(n) |
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#define | HFRCO_NUM(ref) |
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#define | I2C(n) |
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#define | I2C0_DELAY 0x7D0UL /**> Delay cell selection */ |
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#define | I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ |
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#define | I2C1_DELAY 0x7D0UL /**> Delay cell selection */ |
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#define | I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ |
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#define | I2C_DELAY(n) |
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#define | I2C_DELAY_CHAIN_NUM(n) |
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#define | I2C_NUM(ref) |
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#define | IADC0_CONFIGNUM 0x2UL /**> CONFIG */ |
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#define | IADC0_ENTRIES 0x10UL /**> ENTRIES */ |
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#define | IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ |
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#define | IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ |
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#define | ICACHE0_ADDR_BITS 0x12UL /**> Address bits */ |
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#define | ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ |
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#define | ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ |
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#define | ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ |
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#define | ICACHE0_FLASH_START 0x0UL /**> Flash start */ |
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#define | ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ |
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#define | ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ |
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#define | ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ |
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#define | ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ |
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#define | ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ |
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#define | ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ |
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#define | ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ |
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#define | ICACHE0_SET_BITS 0x5UL /**> Set bits */ |
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#define | ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ |
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#define | ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ |
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#define | ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ |
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#define | ICACHE0_WAY_BITS 0x1UL /**> Way bits */ |
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#define | ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ |
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#define | ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ |
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#define | ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ |
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#define | LDMA_CH_BITS 0x5UL /**> New Param */ |
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#define | LDMA_CH_NUM 0x8UL /**> New Param */ |
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#define | LDMA_FIFO_BITS 0x5UL /**> New Param */ |
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#define | LDMA_FIFO_DEPTH 0x10UL /**> New Param */ |
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#define | LDMAXBAR_CH_BITS 0x5UL /**> None */ |
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#define | LDMAXBAR_CH_NUM 0x8UL /**> None */ |
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#define | LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ |
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#define | LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ |
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#define | LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ |
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#define | LFXO_CTUNE 0x1UL /**> CTUNE Present */ |
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#define | LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ |
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#define | MODEM_ADDR_WIDTH 0xBUL /**> New Param */ |
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#define | MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */ |
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#define | MODEM_ANT_NUM 0x2UL /**> Antenna Number */ |
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#define | MODEM_DEC0_SIZE 0xFUL /**> New Param */ |
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#define | MODEM_DEMOD_RAM_WIDTH 0xAUL /**> New Param */ |
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#define | MODEM_DEMOD_WIDTH 0x8UL /**> New Param */ |
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#define | MODEM_IN_SIZE 0x8UL /**> New Param */ |
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#define | MODEM_INTERNAL_SIZE 0x13UL /**> New Param */ |
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#define | MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */ |
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#define | MODEM_PHASE_SIZE 0x8UL /**> New Param */ |
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#define | MODEM_POWER_WIDTH 0xCUL /**> New Param */ |
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#define | MODEM_RAM_SIZE 0x100UL /**> New Param */ |
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#define | MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */ |
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#define | MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */ |
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#define | MSC_FDIO_WIDTH 0x40UL /**> None */ |
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#define | MSC_FLASH_BLOCK_INFO_PCOUNT 0x8UL /**> None */ |
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#define | MSC_FLASHADDRBITS 0x14UL /**> None */ |
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#define | MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ |
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#define | MSC_INFO_PSIZE_BITS 0xDUL /**> None */ |
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#define | MSC_INFOADDRBITS 0x10UL /**> None */ |
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#define | MSC_INFOBLOCKADDRBITS 0x10UL /**> None */ |
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#define | MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ |
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#define | MSC_REDUNDANCY 0x2UL /**> None */ |
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#define | MSC_YADDRBITS 0x6UL /**> None */ |
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#define | PER_REG_BLOCK_CLR_OFFSET 0x2000UL |
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#define | PER_REG_BLOCK_SET_OFFSET 0x1000UL |
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#define | PER_REG_BLOCK_TGL_OFFSET 0x3000UL |
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#define | PROTIMER_CC_NUM 0x8UL /**> None */ |
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#define | PROTIMER_PRS_NUM 0xBUL /**> */ |
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#define | PRS_ASYNC_CH_NUM 0xCUL /**> None */ |
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#define | PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ |
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#define | PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ |
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#define | PRS_SYNC_CH_NUM 0x4UL /**> None */ |
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#define | RAC_DPI_CHAN_COUNT 0x6UL /**> */ |
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#define | RAC_PRESC_BITS 0x7UL /**> None */ |
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#define | RAC_WAIT_BITS 0xAUL /**> None */ |
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#define | RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ |
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#define | RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ |
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#define | RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ |
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#define | RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ |
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#define | RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ |
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#define | RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ |
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#define | RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ |
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#define | RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ |
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#define | RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ |
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#define | RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ |
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#define | RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ |
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#define | RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ |
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#define | RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ |
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#define | RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ |
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#define | RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ |
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#define | RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ |
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#define | RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ |
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#define | RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ |
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#define | RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ |
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#define | RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ |
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#define | RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ |
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#define | RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ |
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#define | RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ |
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#define | RDMEM_SEQ_NUM_BANK 0x1UL /**> SEQ_NUM_BANK */ |
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#define | RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ |
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#define | RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ |
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#define | RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ |
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#define | RDMEM_SEQ_RAMADDRBITS 0xDUL /**> SEQ RAM ADDRBITS */ |
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#define | RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ |
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#define | RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ |
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#define | RTCC_CC_NUM 0x3UL /**> None */ |
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#define | SYNTH_CHPDACBITS 0x8UL /**> */ |
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#define | SYNTH_DACDEMBITS 0x3UL /**> */ |
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#define | SYNTH_MMDDENOMBITS 0x9UL /**> */ |
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#define | SYNTH_MOD_OUT_WIDTH 0x11UL /**> */ |
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#define | SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */ |
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#define | SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */ |
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#define | SYSCFG_CHIP_FAMILY 0x30UL /**> CHIP Family */ |
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#define | SYSCFG_CHIP_REV_MAJOR 0x1UL /**> Major revision */ |
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#define | SYSCFG_CHIP_REV_MINOR 0x0UL /**> Minor revision */ |
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#define | SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ |
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#define | SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ |
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#define | SYSCFG_RAM0_INST_COUNT 0x6UL /**> None */ |
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#define | SYSCFG_SEQRAM_INST_COUNT 0x1UL /**> None */ |
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#define | SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ |
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#define | TIMER(n) |
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#define | TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ |
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#define | TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ |
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#define | TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ |
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#define | TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ |
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#define | TIMER0_NO_DTI 0x0UL /**> */ |
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#define | TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ |
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#define | TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ |
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#define | TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ |
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#define | TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ |
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#define | TIMER1_NO_DTI 0x0UL /**> */ |
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#define | TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ |
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#define | TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ |
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#define | TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ |
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#define | TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ |
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#define | TIMER2_NO_DTI 0x0UL /**> */ |
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#define | TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ |
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#define | TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ |
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#define | TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ |
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#define | TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ |
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#define | TIMER3_NO_DTI 0x0UL /**> */ |
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#define | TIMER_CC_NUM(n) |
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#define | TIMER_CNTWIDTH(n) |
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#define | TIMER_DTI(n) |
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#define | TIMER_DTI_CC_NUM(n) |
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#define | TIMER_NO_DTI(n) |
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#define | TIMER_NUM(ref) |
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#define | USART(n) |
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#define | USART0_AUTOTX_REG 0x1UL /**> None */ |
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#define | USART0_AUTOTX_REG_B 0x0UL /**> None */ |
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#define | USART0_AUTOTX_TRIGGER 0x1UL /**> None */ |
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#define | USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ |
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#define | USART0_CLK_PRS 0x1UL /**> None */ |
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#define | USART0_CLK_PRS_B 0x0UL /**> New Param */ |
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#define | USART0_FLOW_CONTROL 0x1UL /**> None */ |
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#define | USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ |
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#define | USART0_I2S 0x1UL /**> None */ |
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#define | USART0_I2S_B 0x0UL /**> New Param */ |
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#define | USART0_IRDA_AVAILABLE 0x1UL /**> None */ |
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#define | USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART0_MVDIS_FUNC 0x1UL /**> None */ |
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#define | USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ |
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#define | USART0_RX_PRS 0x1UL /**> None */ |
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#define | USART0_RX_PRS_B 0x0UL /**> New Param */ |
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#define | USART0_SC_AVAILABLE 0x1UL /**> None */ |
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#define | USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART0_SYNC_AVAILABLE 0x1UL /**> None */ |
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#define | USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ |
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#define | USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ |
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#define | USART0_TIMER 0x1UL /**> New Param */ |
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#define | USART0_TIMER_B 0x0UL /**> New Param */ |
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#define | USART1_AUTOTX_REG 0x1UL /**> None */ |
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#define | USART1_AUTOTX_REG_B 0x0UL /**> None */ |
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#define | USART1_AUTOTX_TRIGGER 0x1UL /**> None */ |
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#define | USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ |
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#define | USART1_CLK_PRS 0x1UL /**> None */ |
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#define | USART1_CLK_PRS_B 0x0UL /**> New Param */ |
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#define | USART1_FLOW_CONTROL 0x1UL /**> None */ |
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#define | USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ |
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#define | USART1_I2S 0x1UL /**> None */ |
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#define | USART1_I2S_B 0x0UL /**> New Param */ |
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#define | USART1_IRDA_AVAILABLE 0x1UL /**> None */ |
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#define | USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART1_MVDIS_FUNC 0x1UL /**> None */ |
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#define | USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ |
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#define | USART1_RX_PRS 0x1UL /**> None */ |
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#define | USART1_RX_PRS_B 0x0UL /**> New Param */ |
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#define | USART1_SC_AVAILABLE 0x1UL /**> None */ |
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#define | USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART1_SYNC_AVAILABLE 0x1UL /**> None */ |
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#define | USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ |
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#define | USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ |
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#define | USART1_TIMER 0x1UL /**> New Param */ |
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#define | USART1_TIMER_B 0x0UL /**> New Param */ |
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#define | USART2_AUTOTX_REG 0x1UL /**> None */ |
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#define | USART2_AUTOTX_REG_B 0x0UL /**> None */ |
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#define | USART2_AUTOTX_TRIGGER 0x1UL /**> None */ |
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#define | USART2_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ |
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#define | USART2_CLK_PRS 0x1UL /**> None */ |
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#define | USART2_CLK_PRS_B 0x0UL /**> New Param */ |
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#define | USART2_FLOW_CONTROL 0x1UL /**> None */ |
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#define | USART2_FLOW_CONTROL_B 0x0UL /**> New Param */ |
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#define | USART2_I2S 0x1UL /**> None */ |
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#define | USART2_I2S_B 0x0UL /**> New Param */ |
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#define | USART2_IRDA_AVAILABLE 0x1UL /**> None */ |
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#define | USART2_IRDA_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART2_MVDIS_FUNC 0x1UL /**> None */ |
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#define | USART2_MVDIS_FUNC_B 0x0UL /**> New Param */ |
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#define | USART2_RX_PRS 0x1UL /**> None */ |
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#define | USART2_RX_PRS_B 0x0UL /**> New Param */ |
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#define | USART2_SC_AVAILABLE 0x1UL /**> None */ |
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#define | USART2_SC_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART2_SYNC_AVAILABLE 0x1UL /**> None */ |
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#define | USART2_SYNC_AVAILABLE_B 0x0UL /**> New Param */ |
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#define | USART2_SYNC_LATE_SAMPLE 0x1UL /**> None */ |
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#define | USART2_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ |
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#define | USART2_TIMER 0x1UL /**> New Param */ |
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#define | USART2_TIMER_B 0x0UL /**> New Param */ |
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#define | USART_AUTOTX_REG(n) |
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#define | USART_AUTOTX_REG_B(n) |
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#define | USART_AUTOTX_TRIGGER(n) |
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#define | USART_AUTOTX_TRIGGER_B(n) |
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#define | USART_CLK_PRS(n) |
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#define | USART_CLK_PRS_B(n) |
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#define | USART_FLOW_CONTROL(n) |
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#define | USART_FLOW_CONTROL_B(n) |
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#define | USART_I2S(n) |
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#define | USART_I2S_B(n) |
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#define | USART_IRDA_AVAILABLE(n) |
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#define | USART_IRDA_AVAILABLE_B(n) |
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#define | USART_MVDIS_FUNC(n) |
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#define | USART_MVDIS_FUNC_B(n) |
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#define | USART_NUM(ref) |
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#define | USART_RX_PRS(n) |
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#define | USART_RX_PRS_B(n) |
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#define | USART_SC_AVAILABLE(n) |
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#define | USART_SC_AVAILABLE_B(n) |
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#define | USART_SYNC_AVAILABLE(n) |
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#define | USART_SYNC_AVAILABLE_B(n) |
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#define | USART_SYNC_LATE_SAMPLE(n) |
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#define | USART_SYNC_LATE_SAMPLE_B(n) |
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#define | USART_TIMER(n) |
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#define | USART_TIMER_B(n) |
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#define | WDOG(n) |
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#define | WDOG0_PCNUM 0x2UL /**> None */ |
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#define | WDOG1_PCNUM 0x2UL /**> None */ |
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#define | WDOG_NUM(ref) |
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#define | WDOG_PCNUM(n) |
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